Maximum Clock Frequenc

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MaximumClockFrequency:StaticTimingAnalysis(STA)basic(Part5b)|VLSIConcepts
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Sunday,September30,2012
MaximumClockFrequency:StaticTimingAnalysis(STA)basic
(Part5b)
Part1
Part5b
Part2
Part6a
Part3a
Part6b
Part3b
Part6c
Part3c
Part7a
Part4a
Part7b
Part4b
Part7c
Part4c
Part8
Part5a
StaticTiminganalysisisdividedintoseveralparts:
Part1>TimingPaths
Part2>TimeBorrowing
Part3a>BasicConceptOfSetupandHold
Part3b>BasicConceptofSetupandHoldViolation
Part3c>PracticalExamplesforSetupandHoldTime/Violation
Part4a>DelayTimingPathDelay
Part4b>DelayInterconnectDelayModels
Part4c>DelayWireLoadModel
Part5a>MaximumClockFrequency
Part5b>ExamplestocalculatetheMaximumClockFrequencyfordifferentcircuits.
FeaturedPost
TypesOfClockSkew
ClassificationOfClockSkewInthepreviousArticle,we
havediscussedabouttheSkewandtheSourceofSkew.
Inthisarticlewewill...
Part6a>HowtosolveSetupandHoldViolation(basicexample)
Part6b>ContinueofHowtosolveSetupandHoldViolation(Advanceexamples)
Part6c>ContinueofHowtosolveSetupandHoldViolation(moreadvanceexamples)
Part7a>MethodsforIncrease/DecreasetheDelayofCircuit(EffectofWireLengthOntheSlew)
Part7b>MethodsforIncrease/DecreasetheDelayofCircuit(EffectofSizeoftheTransistorOntheSlew)
Part7c>MethodsforIncrease/DecreasetheDelayofCircuit(EffectofThresholdvoltageOntheSlew)
Part8>10waystofixSetupandHoldViolation.
Example1:MultipleFFsSequentialCircuit
Inatypicalsequentialcircuitdesignthereareoftenmillionsofflipfloptoflipfloppathsthatneedtobeconsideredincalculatingthe
maximum clock frequency. This frequency must be determined by locating the longest path among all the flipflop paths in the
circuit.Considerthefollowingcircuit.
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Therearethreeflipfloptoflipfloppaths(flopAtoflopB,flopAtoflopC,flopBtoflopC).UsinganapproachsimilartowhateverI
haveexplainedinthelastsection,thedelayalongallthreepathsare:
TAB=tClkQ(A)+ts(B)=9ns+2ns=11ns
TAC=tClkQ(A)+tpd(Z)+ts(C)=9ns+4ns+2ns=15ns
TBC=tClkQ(B)+tpd(Z)+ts(C)=10ns+4ns+2ns=16ns
Since the TBC is the largest of the path delays, the minimum clock period for the circuit is Tmin = 16ns and the maximum clock
frequencyis1/Tmin=62.5MHz.
Example2:CircuitwithminandmaxdelaySpecification
Letsconsiderfollowingcircuit.NowthiscircuitissimilartothenormalFFcircuitry,onlydifferencesare
Everyspecificationhas2values(MinandMax).
Thereisacombinationalcircuitintheclockpathalso.
Note: if you are wondering why there are min and max value (or like from where these values are coming, then you have to refer
anotherblog).
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Nowletsunderstandtheflow/circuitonceagain.
Everyinterconnectwirealsohassomedelay,soyoucanseeclockCLKwilltakesometimetoreachtheclockpinofthe
FF1.
Thats means with reference to original clock edge (lets assume at 0ns), clock edge will take minimum 1ns and
maximum2nstoreachtheclockpinoftheFF1.
Sointhesimilarfashion,ifwewillcalculatethetotalminimumdelayandmaximumdelay.
Indatapath:maxdelay=(2+11+2+9+2)ns=26ns
Indatapath:mindelay=(1+9+1+6+1)ns=18ns
Inclockpath:maxdelay=(3+9+3)ns=15ns
Inclockpath:mindelay=(2+5+2)ns=9ns
Inthelast2example,therewerenodelaysintheclockpath,soitwaseasytofigureouttheminimumclockperiod.But
inthisexamplewehavetoconsiderthedelayintheclockpathalso.
Soforminimumclockperiod,wejustwanttomakesurethatatFF2,datashouldbepresentatleasttsetuptimebefore
positiveclockedge(ifitsapositiveedgedtriggeredflipflop)attheFF2.
SoClockedgecanreachattheFF2after9ns/15ns(min/max)withthereferenceoforiginalclockedge.
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Anddatawilltaketime18ns/26ns(min/max)withthereferenceoforiginalclockedge.
Soclockperiodinallthe4combinationsare
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Clockperiod(T1)=(Maxdatapathdelay)(maxclockpathdelay)+tsetup=2615+4=15ns
April(2)
March(1)
February(5)
Clockperiod(T2)=(Mindatapathdelay)(maxclockpathdelay)+tsetup=1815+4=7ns
Clockperiod(T3)=(Maxdatapathdelay)(minclockpathdelay)+tsetup=269+4=21ns
2011(17)
Clockperiod(T4)=(Mindatapathdelay)(minclockpathdelay)+tsetup=189+4=11ns
2010(5)
Since we want that this circuit should work in the entire scenario (all combination of data and clock path delay), so we
havetocalculatetheperiodonthebasisofthat.
2008(1)
Now if you will see all the above clock period, you can easily figure out that if the clock period is less than
21ns,theneitheroneorallofthescenarios/cases/combinationsfail.
Sowecaneasilyconcludethatforworkingoftheentirecircuitproperly
Minimum Clock Period = Clock period (T3) = (Max data path delay)(min clock path
delay)+tsetup=269+4=21ns
Soingeneral:
MinimumClockPeriod=(Maxdatapathdelay)(minclockpathdelay)+tsetup
And"MaximumClockFrequency=1/(MinClockPeriod)
Example3:CircuitwithmultipleCombinationalpathsbetween2FFs:
Now same scenario is with this example. I am not going to explain much in detail. Just its like that if you have multiple paths in
betweenthe2flipflops,thenaswehavedoneinpreviousexamples,pleasecalculatethedelays.
Thencalculatethetimeperiodandseewhichoneissatisfyingallthecondition.OrdirectlyIcansaythatwecancalculatetheClock
periodonthebasesofthedelayofthatpathwhichhasbignumber.
MinClockTimePeriod=Tclkq(ofUFF1)+max(delayofPath1,delayofPath2)+Tsetup(ofUFF3)
Example4:CircuitwithDifferentkindofTimingpaths:
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SinceIhavementionedthatithasdifferentkindoftimingpath,soyoushouldknowaboutthetimingpaths.Forthatyoucanrefer
the(Postlink)post.AfterreadingtheTimingpath,youcaneasilyfigureoutthatintheabovecircuitthereare4typesofdatapaths
and2clockpaths
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1.RegistertoregisterPath
U2>U3>U1(Delay=5+8=13ns)
2.Inputpin/porttoRegister(flipflop)
3.Inputpin/porttoOutputpin/port
U7>U5>U6(Delay=1+9+6=16ns)
4.Register(flipflop)toOutputpin/port
U1>U5>U6(Delay=5+9+6=20ns)
U2>U5>U6(Delay=5+9+6=20ns)
Clockpath:
U8>U1(Delay=2ns)
U8>U2(Delay=2ns)
Now few important points This is not a full chip circuit. In general, recommendation is that you use registers at every input and
outputport.Butforthetimebeing,wewilldiscussthiscircuit,consideringthisasfullchipcircuit.Andyouwillhowmuchanalysis
you have to do in this case. Next example, I will add the FFs (registers) at input and output port and then you come to know the
difference.
NowletsStudythiscircuitinmoredetails.
Inthiscircuit,wehavetodotheanalysisinsuchawaythatifwewillapplyaninputatPortA,thenhowmuchtimeitwill
taketoreachatoutputPortY.Itwillhelpustofindoutthetimeperiodofclock.
Output pin Y is connected with a 3input NAND gate. So if we want a stable out at Y, we have to make sure that all 3
InputsofNANDgateshouldhavestabledata.
OneinputofNANDgateisconnectedwithInputpinAwiththehelpofU7.
TimetakebydatatoreachNANDgateis1ns(gatedelayofU7)
SecondinputpinofNANDgateisconnectedwithoutputpinQofFlipflopU2.
TimetakebydatawhichispresentatinputDofFFU2toreachNANDgate:
2ns(delayofU8)+5ns(Tc2qofFFU2)=7ns
ThirdinputpinofNANDgateisconnectedwiththeoutputpinQofFlipFlopU1.
TimetakebydatawhichispresentatinputDofFFU2toreachNANDgate:
2ns(delayofU8)+5ns(Tc2qofFFU1)=7ns
Note:
IknowyoumayhavedoubtthatwhydelayofU8comesinpicture.
WithreferencetotheclockedgeatCLKpin,wecanreceivethedataatNANDpinafter7nsonly(Dontask
mewhywecanttakereferenceinnegative?)
MaybeyoucanaskwhywehaventconsiderthesetuptimeofFFinthiscalculation.
If in place of NAND gate, any FF would there then we will consider the setup. We never consider the setup
and Tc2q (Clk2Q) values of same FF in the delay calculation at the same time. Because when we are
consideringClk2Qdelay,weassumethatDataisalreadypresentatinputPinDoftheFF.
SoTimerequiredforthedatatotransferfrominput(A)tooutput(Y)Pinisthemaximumof:
Pin2PinDelay=U7+U5+U6=1+9+6=16ns
Clk2Out(throughU1)delay=U8+U1+U5+U6=2+5+9+6=22ns
Clk2Out(throughU2)delay=U8+U2+U5+U6=2+5+9+6=22ns.
SooutofthisClk2OutDelayisMaximum.
FromtheaboveStudy,youcanconcludethatdatacanbestableafter7nsattheNANDgateandmaximumdelayis22ns.Andyou
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11/13/2016
FromtheaboveStudy,youcanconcludethatdatacanbestableafter7nsattheNANDgateandmaximumdelayis22ns.Andyou
canalsoassumethatthismuchdataissufficientforcalculatingtheMaxClockFrequencyorMinimumTimePeriod.Butthatsnot
thecase.StillouranalysisishalfdoneincalculatingtheMaxclockfrequency.
Aswehavedoneinourpreviousexample,wehavetoconsiderthepathbetween2flipflopsalso.Sothepathsare:
FromU1toU2(Reg1Reg2)
Path delay= 2ns (Delay of U8) + 5ns (Tclk2Q of U1)+7ns (Delay of U4)+3ns (Setup of U2) 2ns (Delay of
U8)=17ns2ns=15ns
FromU2toU1(Reg2Reg1)
Pathdelay=2ns(DelayofU8)+Tclk2QofU2(5ns)+DelayofU3(8ns)+setupofU1(3ns)DelayofU8
(2ns)=18ns2ns=16ns.
Note:
IamsureyouwillaskwhydidIsubtractDelayofU8fromtheabovecalculation:)becauseDelayofU8iscommonto
boththelaunchandcapturepath(IncaseyouwanttoknowwhatsLaunchandcapturepathpleasefollowthispost).So
wearenotsupposedtoaddthisdelayinourcalculation.Butjusttomakeitclear,Ihaveaddedasperthepreviouslogic
andthensubtractedittomakeitclear.
So now if you want to calculate the maximum clock frequency then you have to consider all the delay which we have discussed
above.
So
MaxClockFreq=1/Max(Reg1Reg2,Reg2Reg1,Clk2Out_1,Clk2Out_2,Pin2Pin)
=1/Max(15,16,22,22,16)
=1/22=45.5MHz
Example5:CircuitwithDifferentkindofTimingpathswithRegisteratInputandoutputports:
Inthisexample,wehavejustadded2FFsU8atInputpinandU9atoutputpin.Nowforthiscircuit,ifwewanttocalculatethemax
clockfrequencythenitssimilartoexample1.
Thereare7Flipfloptoflipfloppaths
1.U8>U4>U2
Delay=5ns+7ns+3ns=15ns
2.U8>U3>U1
3.U8>U5>U9
4.U1>U4>U2
5.U1>U5>U9
6.U2>U5>U9
7.U2>U3>U1
Sincethemaximumpathdelayis17ns,
TheMinimumclockperiodforthecircuitshouldbeTmin=17ns
AndtheMaximumclockfrequencyis1/Tmin=58.8MHz.
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58comments:
Anonymous October27,2012at4:00AM
Awesomestuff.Willyoualsotalkalittleaboutmulticyclepaths?
Reply
Replies
yourVLSI November8,2012at12:37PM
SureIwilldoinnextfewarticles.
Reply
Anonymous November7,2012at5:33PM
HelloSir,
Bigfanofyoursblog.
Ihaveaquery.
InExample3(CircuitwithmultipleCombinationalpathsbetween2FFs),uvementioned
MinClockTimePeriod=Tclkq(ofUFF1)+max(delayofPath1,delayofPath2)Tsetup(ofUFF3).
isthiscorrect?Ifyes,howcome?
Reply
Replies
yourVLSI November8,2012at12:30PM
Hi,
Theabovementionedstatementiscorrect.Forexplanation,Iwillpreferyoutoreadthepreviouspartofthisseriesandthe
first2example.
Evenafterthatifyouhaveanydoubt,justletmeknow.
Reply
ArpanSarkar November9,2012at12:27PM
Hi,
Istillcan'tunderstandExample3.MeansIthoughttheminclockperiodshouldbeDelayfromClktoQoff/f1+max(Tddelayofpath1,
Tddelayofpath2)+Tsoff/f3butwhythereisTsoff/f3?Normallyweshouldaddthesetuptimetogettheminclockperiod,buthere
youaresubtracting.Canyoupleaseexplainit,Iamgettingconfused.
Reply
Replies
ArpanSarkar November9,2012at12:59PM
MeansdatawhichreachestheDoff/f3,shouldgetstablebeforetheTstimeofthenextclockedge.So,Tsshouldget
addedtocompletetheclockperiod.Butwhyuaresubtracting.Pleaseexplainitlittle.Ireadtheblog,butdidn'tunderstood.
Reply
Anonymous November10,2012at1:59PM
Sir,
evenIhavesamedoubtaboutexample3.plzexplainsir...
Reply
Replies
yourVLSI November21,2012at10:48AM
Hi,
Canyoubemorespecificaboutyourdoubt?
Reply
Anonymous December14,2012at12:18PM
Hi,
Forcalculationgthemaxfrequencyyouhaveused
MaxClockFreq=1/Max(Reg1Reg2,Reg2Reg1,Clk2Out_1,Clk2Out_2,Pin2Pin)
IthinkMaxclockfrequency=1/Min(Reg1Reg2,Reg2Reg1,Clk2Out_1,Clk2Out_2,Pin2Pin)
Maxclockfrequency=1/Min(T).Pleasecorrectmeifiamwrong
Reply
Replies
yourVLSI December15,2012at12:40AM
:)..youknow,Iwasexpectingsomethingsimilartothisfromlongtime...:)
forthetimebeingdntthinkaboutmaxandminvalueofanyparameter.
5/12
11/13/2016
NowClockfrequency=1/Time_period
andTimeperioddependsonthedelayofthecircuit.
Now if in your circuit there are 2 paths between FFs one having 1sec delay and other 1.5s and you want that data
should reach from launching to capturing FF with in one clock cycle and it should satisfy both the condition (both the
delays),thenwhichonedoyouchoose?
IfIamcorrect,youhavetodecidethedelayasperthedelaypathof1.5s.MeansMinimumTimeperiodshouldbe1.5s.
Youcanhavemorethenthisbut1.5sshouldbetheminimumvalue.
andthenthefrequencywillbef=1/1.5.
NowifTimeperiodismorethenthis,thenfrequencywillbelessthen1/1.5andthatthereasonwearesayingthatf=1/1.5
istheMaximumfrequency.
Soyouarerightmax_frequency=1/min_T.
butasyouhaveseenthatMin_TdependsontheMaximumdelayinthecircuit.
IhopeyougotthereasonofchoosingMaximumdelayoutofallthepossibledelayvaluespresentbetweenthe2FFs.
Reasoniswewanttosatisfyallthedelaypath.
Letmeknowifstillyouhaveanyfollowonquestion.
Sandeep December17,2012at11:13AM
Thanksforthereplyiamcompletelysatisfiedwithyouranswer.
Reply
siva December26,2012at11:17AM
Hellosir,Intheexample2whilecalculatingmaximumfrequencyyouhavetosubtractskewofdestinationfilpflopw.r.tosourceflip
flop,
Therefore,Tmin=11+2+9+2+4((2+5+2)1)=20ns
Isn'tit?
amicorrectorwrong?
Reply
Replies
yourVLSI March15,2013at12:03AM
lookslikeyourcalculationislittlebitincorrect.Justcheckonceagain.
achintvats December20,2014at10:08AM
Tmin=2+11+2+9+2+4((2+5+2)1)=22nsisitcorrect?
Reply
Mantu January16,2013at4:40PM
Hi,
Forexample3:Minclockperiodcalculationiswrittenas,
MinClockTimePeriod=Tclkq(ofUFF1)+max(delayofPath1,delayofPath2)Tsetup(ofUFF3)
Butifeel,InsteadofsubtractingTsetup(ofUFF3)()itshouldhaveadded(+)intheaboveequation.
Correctmeifiamwrong.
Reply
Replies
Correct...andIhavecorrectedalso.thanksforcorrection
Reply
Anonymous January24,2013at4:03PM
Hi,
Inexample2,
"Indatapath:mindelay=(1+9+1+9+1)ns=21ns".
Isit"(1+9+1+6+1)ns=18ns?
Thanks.
Reply
Replies
yourVLSI March14,2013at11:57PM
100%correct.Ihavecorrectedalsoinmypost.thanksforcorrection.
Reply
Raj March11,2013at6:39AM
Hi,
Inexample3itisMinClockTimePeriod=Tclkq(ofUFF1)+max(delayofPath1,delayofPath2)+Tsetup(ofUFF3)
Reply
Replies
Correct...andIhavecorrectedalso.thanksforcorrection
Reply
6/12
11/13/2016
Anonymous September23,2013at8:03AM
hi,
whenyoucalculateMaxClockFreqinexample4,whydon'tyouconsiderthedelaybetweeninputpinandflipflop?thanks.
Reply
venkatakrishna November17,2013at12:35AM
sir,
Hereincalculationofmaximumfrequencywhyareyounotconsideringtheinputtoregdelay.pleaseexplain?
Reply
Anonymous January13,2014at3:45PM
I have the same question as venkata krishna, why you don't consider the input to register delay, when calculating the max. clock
frequency.Thanks.
Reply
Replies
yourVLSI January13,2014at11:18PM
The reason we are not considering in this example ... you have freedom to apply the input at any time before the first
positiveclockpulse.Evenifyouwanttocapturethesecondsetofinputdataatanyoftheflipflop...youdon'thaveany
restrictiontoapplythedataatinputport.soonwhatbaseyouwilldefinearelationshipbetweenclockfrequencyand"input
toflopdelay".
Letmeknow,ifstillyouhaveconfusion...
Anonymous January14,2014at3:24AM
IamnotsurewhetherIgetyourpoint.Asyoualsoconsidertheinputtooutputandregistertooutputdelayintheclock
frequencycalculation,youarebasicallyassumingtheinputsandtheoutputsaresampledbytheclock(probablywitha
samplingoffsetwithrespecttotherisingedgeoftheclock,assuminganidealclocknet).Aslongasthedataaresampled,
thereisarelationshipbetweeninput/outputandtheclock.AmIwrong?
yourVLSI January14,2014at11:59PM
IwasthinkingtoraisethepointofinputtooutputpathinmyreplybutsomehowIdeleted.Pointofincludingthatoneis
thereisaNANDgatewhichhas3input.Outof32arecomingfromaflopandthesignalwhichiscomingfromflophas
dependenceontheclock..AndIhavementionedthat
"OutputpinYisconnectedwitha3inputNANDgate.SoifwewantastableoutatY,wehavetomakesurethatall3Inputs
ofNANDgateshouldhavestabledata."
Andthat'sthereasonwehavetoconsiderthisinputtooutputpath.
Letssupposethisisjustasimplewire..andithasnorelationshipwiththeclock,thentherewasnoneedofthispathinour
calculation.
Youarerightifwearesamplingthedatathenthereisarelationshipbutwhetherthatsamplingisgoingtoeffectyouclock
frequencyornotthat'sthequestion.LetussupposethatIamaskingyoutocaptureatrain(anytrain)..thenyoucanstart
fromyourhomeatanytimeandyouwillnotbotheraboutthetimetakentoreachrailwaystationbutthemomentImention
thatyouhavetocaptureatrainat10PM,thenyouwillstartcalculatingthetimetakentotravelandmarginandsomany
things.
Soinourcase,youcanapplytheInputatanytimeandIhavenotmentionedanywherethatfirstflipflopshouldcapturethe
dataattime=2nsor1nsor0nsoranyothertime.Andthat'sthereasonIhavenottakentheinputtoflopintocalculation.
Ihopeyougotmypoint.Letmeknowifstillyouhaveconfusion.
Anonymous January15,2014at3:01AM
NowIgetyourpoint.Manythanksforyourdetailedexplanation.Ilikeyourblogverymuchandlearnedalot.
yourVLSI January15,2014at10:34AM
Welcome...andthanksforappreciating.
Reply
Anonymous April16,2014at11:50PM
Ihavestartedwiththeblogsandtheyareawesomeandveryinformative.Ihaveadoubtinexample2.Youhaveused
MinimumClockPeriod=Clockperiod(T3)=(Maxdatapathdelay)(minclockpathdelay)+tsetup
Pleasetellwhywearesubtractingminclockpathdelays,because,ifwearecalculatingclockperiodthenweshouldaccommodate
allthedelays?
Reply
Replies
yourVLSI April19,2014at11:11AM
we are calculating the Minimum required Clock period so that our circuit can work.. another thing these 2 path are
different.Clocktravelthroughclockpath,anditwilltakesometimetoreachthecaptureFF.NowDatatravellingalsotaking
sometoreachcaptureFF.Sonowifyouwanttocalculatetheeffectivetimedifference,youhavetosubtractTimetakenby
clocktoCaptureFFfromthetimetakenbydatatoreachcaptureFF.
NowthiseffectivetimedifferenceisgoingtohelpindecidingtheMinimumclockperiod.
Ihopeyougetmypoint.Ifnottrytovisualizethisandifstillhaveissue,letmeknow.
Anonymous April11,2015at3:37PM
ihavethesamedoubtandicantabletovisualizethis....ihavedoubtthatwewanttocalminclockperiod,,ithinkforthat
datapathcalculationissufficient...itgivestotaldelaysowhyweconsiderclkpathalso?
7/12
11/13/2016
VlsiExpertGroup April20,2015at9:42AM
Youarepartiallyright..thatDatapathdelayissufficientonlywhenClockpathisIdealmeansnodelay.
YouwanttocaptureadataatCaptureFlipflop...inthedatapaththereisadelayof10ns.Thatmeansyoucan'tcapturethe
data before that (10ns) (if there is no setup value). And as per your understanding it's sufficient. So as per your
understandingMinimumClockPeriodshouldbe10ns.AmIright?
Think,whatifClockpathhasadelayof2ns.SinceClockpathalreadyhaveadelay,soasperyourcalculation,Clock
period:10nmanddelayof2ns:Meanstotal12nsafterClockwillreachtoCaptureFlipflop.ButminimumTimeof10nsis
sufficient.
NowinsuchcasewecanreducetheClockperiodto8nm.Now8+2=10.
Ithink,NowyoucaneasilyvisualizethatwhyclockpathisalsoimportantforCalculatingMinimumClockPeriod.
Letmeknowifyoustillhavedoubt.
Reply
Anonymous April27,2014at1:13AM
whyhavewenotconsideredtheclktooutdelayinlastexample?
Thoughitsonly15ns(lessthanmaximum)butstillshouldbementioned.
amIrightthatweneedtoconsiderclktooutdelayornot?
Reply
Replies
Anonymous February16,2015at4:31PM
yaa..iamalsothinkingso..
Reply
Anonymous June25,2014at10:45AM
Hi,InExample2:FF1toFF2isRegistertoRegisterPath.
ForCalculatingRegtoRegpath,weconsideredTsofFlop2inExamples.
whyYouhereNotaddedtheTsincalculations??
Sointhesimilarfashion,ifwewillcalculatethetotalminimumdelayandmaximumdelay.
YourCalculations:
Indatapath:maxdelay=(2+11+2+9+2)ns=26ns
Indatapath:mindelay=(1+9+1+6+1)ns=18ns
MinimumClockPeriod=Clockperiod(T3)=(Maxdatapathdelay)(minclockpathdelay)+tsetup=269+4=21ns
MYCalculations:
Indatapath:maxdelay=(2+11+2+9+2+4[tsofFF2])ns=30ns
Indatapath:mindelay=(1+9+1+6+1+4[tsofFF2])ns=22ns
Inclockpath:maxdelay=(3+9+3+4[tsofFF2])ns=19ns
Inclockpath:mindelay=(2+5+2+4[tsofFF2])ns=13ns
MinimumClockPeriod=Clockperiod(T3)=309=21ns
FinallyAnswerisSame.
MyQuestionisasperTechnicalTerminology,minimumdelayandmaximumdelaymeansweshouldnotaddtheTsof2ndFlop????
ThanksfortheArticle.
Reply
Replies
yourVLSI June25,2014at1:55PM
HiFirstofall..youcan'taddsetupinbothplaces(clockpathanddatapath)...sowhateveryouhavedoneisnotcorrect.
Intheaboveexampleyoucanseethatlateronwhilecalculatingthetimeperiod,setuptimeisconsidered..
Clockperiod(T1)=(Maxdatapathdelay)(maxclockpathdelay)+tsetup=2615+4=15ns
Clockperiod(T2)=(Mindatapathdelay)(maxclockpathdelay)+tsetup=1815+4=7ns
Clockperiod(T3)=(Maxdatapathdelay)(minclockpathdelay)+tsetup=269+4=21ns
Clockperiod(T4)=(Mindatapathdelay)(minclockpathdelay)+tsetup=189+4=11ns
Nowifyouaretalkingaboutthedatapathonlyyoucandothecalculationasperthatalso..means
Indatapath:maxdelay=(2+11+2+9+2+4[tsofFF2])ns=30ns
Indatapath:mindelay=(1+9+1+6+1+4[tsofFF2])ns=22ns
andnowtheClockperiod(T3)willbe309=21ns.
Soyoucancalculateinthiswayalso.
RegardingtheTechnicalTerminologyfranklyspeakingIdon'tcarebecauseformeconceptisimportant.andnooneis
goingtoaskdefinition.
AssuchwhenIamsayingminormaxdelayofNetthenitdon'tconsiderthesetupandholdtime,whenyousayingmin
andmaxofcellthenonlycelldelayisconsideredandwhenyouaresayingminandmaxofwirethenonlywiredelayis
considered.
Ifyouaresayingthatminandmaxofdatapaththenyoumayincludesetupandholdtime.ButIalwaysconsiderthem
separateit'seasytoremember.
BTWniceobservationandgoodanalysis.
Reply
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11/13/2016
Anonymous June26,2014at2:54PM
Example3:CircuitwithmultipleCombinationalpathsbetween2FFs:
MinClockTimePeriod=Tclkq(ofUFF1)+max(delayofPath1,delayofPath2)+Tsetup(ofUFF3)
Buttherewas3pathsavailable.Path1&Path2wasDefinedinDiagram.
Path3:UFF1>UNAND0>UBUF2>UNAND6>UFF3.
then
MinClockTimePeriod=Tclkq(ofUFF1)+max(delayofPath1ordelayofPath2ordelayofPath3)+Tsetup(ofUFF3)
Right??
Reply
Replies
YesYouareright...ThereasonIdidn'tcapture..becauseweknowthatpath3delaywillbealwaysgreaterthenotherone
(becauseofmissingoneGATEthere...)
Reply
HI,InExample4Datapaths&ClockpathswasCalculated.
Datapath:
1.RegistertoregisterPath
oU2>U3>U1(Delay=5+8=13ns)
2.Inputpin/porttoRegister(flipflop)
3.Inputpin/porttoOutputpin/port
oU7>U5>U6(Delay=1+9+6=16ns)
4.Register(flipflop)toOutputpin/port
Clockpath:
U8>U1(Delay=2ns)
U8>U2(Delay=2ns)
AndCalculatedTimerequiredforthedatatotransferfrominput(A)tooutput(Y)Pinisthemaximumof:
SooutofthisClk2OutDelayisMaximum.
IsitMandatorytocalculate??
Normallywewillconsiderthepaths:1.i/ptoo/p2.i/ptoReg3.RegtoReg4.Regtoo/pforTimingCalculations.
IfItisMandatorytocalculatei/ptoo/p&Clk2Qtoo/pthen
Q1).ExplainmeIfsupposeExample2hasonemoreFloplikeFF3,SamedelaybetweenFF2toFF3&SameClockDelaybetween
FF2toFF3
Arewegoingcalculatethei/pofFF1too/pofFF3&Clk2QofFF1too/pofFF3???(IthinkNO)
YoucalculatedPin2PinDelay,Clk2Out(throughU1)delay&Clk2Out(throughU2)delay,becauseofgettingo/pY,3multiplei/p's
requiredfortheAND(U5)gate???
LetmeKnowInwhatcases,IshouldcalculatePin2PinDelay,Clk2Out(throughU1)delay&Clk2Out(throughU2)delay???
Q2).ExplainmeIfsupposeExample2hasonemoreFloplikeFF3,SamedelaybetweenFF2toFF3&SameClockDelaybetween
FF2toFF3ButFF1is@Posedgeclk,FF2is@Negedgeclk&FF3is@Posedgeclk
Q3).ExplainmeIfsupposeExample2hasonemoreFloplikeFF3,delaybetweenFF2toFF3Tmin=3ns,Tmax=12ns&ClockDelay
betweenFF2toFF3Tmin=2ns,Tmax=15ns
Q4).ExplainmeIfsupposeExample2hasonemoreFloplikeFF3,delaybetweenFF2toFF3Tmin=3ns,Tmax=12ns&ClockDelay
betweenFF2toFF3Tmin=2ns,Tmax=15nsButFF1is@Posedgeclk,FF2is@Negedgeclk&FF3is@Negedgeclk
Q5).InExample5isitnotrequiredtoCalculateTimerequiredforthedatatotransferfrominput(A)tooutput(Y)Pinisthemaximum
of:
Pin2PinDelay=???
Clk2Out(throughU1)delay=???
Clk2Out(throughU2)delay=???
MaybethesearelengthyQuestions....ButIwanttoKnow&ExpectingClearAnswersfromYou......ThanksinAdvance.
Reply
Replies
HAHAH...Somanyquestions...
CLK2Qisnecessarytocalculate...becausethat'salsoonetypeofdelaywhichcaneffecttimingcalculation.
Answer1:
If1moreFFispresentintheexample2andifthat'sconnectedtoFF1directly(meansnootherFFbetweenFF1andFF3)
thenwearegoingtocalculatealltheRegtoregdelay.
Alwaysrememberbasicconcept.
Answer2:ifit'spositiveedgeandnegativeedge,thenyoucanremove/addtheeffectofthatpart.SoiflaunchedFFisat
time0andcaptureFFisattimesameclockpulsethenegativeedgethenyoucanremovetheOFFtimeofclockwhileyou
arecalculatingtheclockrequirement.
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11/13/2016
Meansifdutycycleis50%,thenreplacemin_clock_time_periodwith2*min_clock_time_periodinabovecalculation.
ButifcaptureFFisattime1completclockpulse+Ontimeofsecondpulse(meansnegativeedgeofsecondpulse)then
equationwillbedifferent.
Ihopeyougetmypoint.
Answer3and4:Doyouthinkpracticallyit'spossible..???
LetmeKnowonething....
YoucalculateTimerequiredforthedatatotransferfrominput(A)tooutput(Y)Pinisthemaximumof:
YoucalculatedPin2PinDelay,Clk2Out(throughU1)delay&Clk2Out(throughU2)delaybecausetheFF1too/p&FF2to
o/ppathsavailable???Right
If the Flops are cascaded one to other flop like FF1 to FF2, FF2 to FF3, FF3 to FF4 ...etc then there won't be above
calculations???.Right
CanyouexplainQ2,Q3,Q4&Q5withthecalculationsPracticallyhere........IamExpectingcalculations.....
TheaboveExplanationisCorrectorNOT??
Reply
InExample4therewasClockdelay(U8)=2nsforBothFlopsU1&U2.
Q1).ForSupposeCKdelay(U8) = 2ns common for Both Flops U1,U2 & Extra Ck Delay (U8_Inverter) for Flop U2, then How will
calculateTmin&Fmax???
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Replies
Thenitwillbealmostsimilartoexample2..useexample2conceptandthentrytorecalculate....
Iamexpectingwithcalculations.....sothatIfwehaveanysetup&Holdviolations,HowwecanplaywiththeDelay's....
hiThat'swhatmypoint..pleasereadthedifferentpostandthentryyourselffirst.Comeupwithexactquestionsandwhat
haveyoutried..thenIcanhelpyou.
IfIwilldoeverythingforyou..thenitwillbedifficultforyoutolearn.
Ihopeyouaregettingmypoint.
Reply
Anonymous August14,2014at8:32PM
dearExpert,
ijustwanttoknowamongfourtypesofdatapaths,doesthepintopin(inputtooutput)pathmustnecessarilyhaveonlycombinational
blockbetweenpins?imean,canitnothaveanyregisterorflopinbetween?(or,willitnowbetreatedasinputtoregpath??)
Reply
Replies
youareright..Themomentitwillhavearegisteritwillbetreatedasinputtoregandregtooutputpaths.
Reply
RAVIKUMAR August22,2014at4:08PM
hi
ihaveasmalldoubtinexample4.
inexample4
withhowmuchfrequencyinputAischanging?
isitsameastheclockfrequencyornot?
Reply
Replies
Here we are not talking about the Frequency by which A is changing. But you are right The real life it will have a
dependency on frequency .. and the moment it will depend on frequency things will change So right now in this
examplejustconsiderthisasjustlikethat.
Reply
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11/13/2016
Anonymous September10,2014at10:55PM
GreatWork.Thanksalot.
Reply
Canyoupleaseexplainlastexample,5?Whymaximumpathdelayisnot22sameaspreviousexample.Whyareweconsideringonly
regtoregdelayandnototherdelays?
Reply
TanviSachdeva August4,2015at12:01PM
Hellosir,
Ihaveaverybasicquestiononsetupandholdtime.
Supposewehaveacriticalpathwhichconsistsof4ffandcombodelaysinbetweenthem.
Myquestionis:
Canwehavesetupandholdviolationonthesamepath?
Canwehavesetupandholdviolationsonthesameflop?
Pleaseletmeknowonthis.
REgards
Tanvi
Reply
Unknown May29,2016at3:10PM
Hi.InExample4,whyhaveyounotincluded2nsdelayfromtheclocksource?
Ithink,itshouldbeRegistertoRegisterdatapath=2ns+5ns+8ns=15ns(U2>U3>U1).
Pleaseclarifymydoubt
Reply
Vasanth June5,2016at10:31PM
Hi,IbelieveexternalI/Odelayswillalsolimitthemaxoperatingfrequencyofourcircuit.Canyouconfirmmyunderstandingplease?
Itwillbegreatifyoucanaddanexamplecircuitwithinputdelayandoutputdelay.OtherthanthatIbelieveyouhavecoveredallother
basiccircuits.
Thanks
Reply
Replies
Vasanth June5,2016at10:39PM
Hi,IhavealsonoticedthatinExample4inmaxoperatingfrequencycalculationonlyreg2reg,reg2outandpin2pindelays
areconsidered.Whyarewenotconsideringin2regpathalso(inputtoregister)?
Reply
Unknown August2,2016at11:57AM
whatismaxfreqwheninverterisplacedinsteadofbufferwith50%dutycyleisitremainssameoritwillchange?
Reply
AvinashSingh September23,2016at1:49AM
formaxpathdelaydowetakepathfromflipfloptoflipfloporclocktooutput??inexample5onlyR2Rpathsarecalculatedandc2q
notconsideredandinex4clocktooutputisconsidered!
pleasereply
Reply
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