Book 2 Module 4 Ps | TRANSISTORS INTEGRATED CIRCUITS PRINTED CIRCUIT BOARDS Licence By Post cence By Post © conrate 1B EASAG6 41.2t042 ISSUE 05 0010© Licence By Post Mo part of tie sd ok maybe re-prouced a buted in ang form or by emer ren dts ba etl those or mp tt ‘Books inthe LBP series are seul up datd/eserisen to keep pace withthe changing technolo, ‘Changing emanation requirements an shanging egal eeeAUTHORITY Itis IMPORTANT to note that the information in this book is for study /training purposes only. ‘When canying out a procedure/work on aircrall/aircraft equipment you MUST always, refer to the relevant aircraft maintenance manual or equipment manufacturer's handbook, ‘You should also fllow the requirements of your national regulatory authority (the CAA in the UK) and laid down company policy as regards local procedures, recording, report writing, documentation et. For health and safety in the workplace you should follow the regulations guidelines as specified by the equipment manufacturer, your company, national safety authorities ‘and national governments.conrents ‘Transistors ‘The transistor as an amplifier Directly coupled amplifiers Differentially connected amplifiers Classes of amplifiers Mulivibrators ‘Astable multivibrator Monostable multiibrator Flip-flops “The JK fip-op ‘The SR fhp- flap Field effect transistors ‘JUGEET MosFET cwos Feedback in amplifiers Oscillators ‘The transistor as a switch, Integrated cireuits Operational amplifiers Logie circuits ‘Clocks Printed circuit boards 14 15 16 20 2 22 23 23 28 24 25 a 28 29 an 33 33 35 2 55HOW TO TACKLE THIS BOOK ‘The same applies to this book as applies to book 1. This means that it s written to the 'B2 level and B1 people should check the How To Tackle This Book section in book 1 to ‘see what subjects should be learnt and to what depth. None of the contents applies to the A Line Mechanic For category B engineers the book will probably need to be read atleast twice to get ‘the information to sink in - in some cases it may need more.‘TRANSISTORS. ‘These are small electronic semi-conductor devices having three or more terminals connected to electrodes within the device. Current flowing between two electrodes is controlled by valiage or current applied at one or more of the other electrodes. They ‘work at very low voltages and can be used as switches and amplifiers Construction and Theory of Operation ‘The Bi-polar or Junction Transistor consists of two heavily doped ‘N’ regions separated by avery thin (0.1mm to Imm thick) lightly doped 'P' region in the one crystal. This is called an N-PN transistor and figure I shows the layout and its symbol and Sgure 2 Showts the relative voltage levels. The emitter (B) is more heavily doped than the collector (C). |AP-N-P transistor is similar except that the two P' regions are separated by a lightly doped centre ‘'N’ region. Two P-N junctions are fused together to form a very thin region (0.1 to Imim thick), The 'N'region is more lightly doped than the "regions, (gure 6). Figures 1 to 4 show the layout of the NPN transistor and its symbol. Note the clectrodes are called COLLECTOR (C), BASE (3) and EMITTER (B) - the one with the firrow in the symbol. The emitter is more heavily doped than the collector. i cousctor gy Fig. 1 NPN TRANSISTOR Note. For both the transistor types the arrows show the direction of conventional current flow and because the N-P-N transistor deals with the movement of electrons rather than holes itis faster and subsequently iti more common than the P-N-P type. ‘Action of the N-P-N Transistor (Ggures 2 and 3) For transistor action to occur the BASE-EMITTER junction must be forward biased {positive to base (P region) and negative to emitter (N region) and the COLLECTOR- [BASE junction must be reverse biased postive to collector (N region] and negative to ‘base (P region). Figure 2 shows the relative voltages for conduction to occur. In more detail figure 2 shows that battery voltage Eis smaller than the battery voltage E-but i must be suficient to overcome the barrier potential of 0.6V for silicon. a+ ee Fig. 2. NPN TRANSISTOR - RELATIVE VOLTAGES Tb keg ‘eh te Yeamcwons Vie —|I-4—ailit= FORWARD EWG REVERSE OAS Fig. 3 NPN TRANSISTOR OPERATION ‘Under the influence of the electric field due to battery voltage E electrons cross the junction into the base, A small proportion (I to 2%) combine with holes in the base fue to it being very thin and lightly daped, Most of the electrons (98 to 99%), under the strong positive influence of battery Ea, are swept through the base to the collector to Eto formn the collector eurrent in the external circuit, Electrons are the majority carriers in the N-P-N transistor. ‘The small amount of electron-hole combination in the base gives it a momentary negative charge, which is immediately corrected by battery E,. Remember, electron flow is shown in figure 3 and conventional current flow isin the opposite direction, ‘So transistor action is the controlling of @ large current in the high resistance (reverse biased) collector-hase junction by a small current through the low resistance (forward Diased) base-emitter junction. ‘The unit is used as an amplifier to produce Gain and is also used as a switch with the ‘base current acting as the switch. Current Gain is called Beta (). B keFig. 4 CONVENTIONAL CURRENT FLOW IN AN ‘NPN TRANSISTOR ‘Action of P-N-P Transistor Figure 6) ‘Again the base-emitter junction is forward biased and the collector-base junction is Feverse biased, Under the influence ofthe electri field due to battery Fe, holes cr03s the junction into the base. Only 1 to 2% of holes recombine with free electrons in the base duce to it being very thin and lightly doped. The majority of the holes 98 to 99% dare accelerated towards the very strong negative influence of battery Fe. Holes are the mmajonty carriers in the PAP transistor, UJ couscron g Fig. 5 PNP TRANSISTOR ie y ahseevor ig Atl Mimnows ROCATEECTRON FON Pig. 6 PNP TRANSISTOR OPERATIONDue to recombination of holes and electrons in the base, the base loses free electrons ‘and will therefore exhibit a positive charge. The electrons will be attracted by battery Er into the base to ‘malce-up' for those lost by recombining with holes. Figure 7 shows the conventional current flows through the transistor Fig. 7 CONVENTIONAL CURRENT FLOW 'PNP TRANSISTOR ‘Since the carriers in the N-P-N and P-N-P transistors originate atthe emitter and distribute themselves between base and collector, the sum ofthe base and collector currents must always be equal tothe emitter current, therefore: hekth TYPE: ise acion 77900 2NaTOS aABOSS A OFT TER fumioeTo1e LINES) To#a TOR METAL CAN (Pash) (metaL) (Puastic)” (PLASTIC) CONNECTED Too) Fig. 8 TYPICAL TRANSISTORS ‘The transistor can be used as an amplifier circuit and also as a switch - a very fast ‘acting switch, The amplifier action is based on applying a low current to the base ‘emitter with a higher current flowing through the collector-emitte. ‘The switching action is the effect of applying a small current to the base for the unit (N-P-N) to ‘witch on’ allowing current to flow between the collector-emiter. Removing the base-emitter current will eause the unit to switch off. These switching times can bbe very fast (say 2ne or 2x 10° seconds oF 0,000 000 002 seconds) (ns = nano seconds), Fast switching times are needed in computing,Testing Transistors Using an analogue multimeter switched to the ohms range. On most analogue rmultimeters on the olume range the negative (terminal has a positive polarity and the ‘positive terminal (+) has a negative polarity. This i an important point with regards to identifying N-P-N and P-N-P transistors. If digital multimeter is used then check the polarities ofthe terminals on the ohms range. Figure 9 shows the readings you would expect using an analogue multimeter. = a2 4 © ce e ig. 9 TESTING TRANSISTORS USING A MULTIMETER Liner ches are ampliing pest. They wi have analogue inputs nd the output will vary continuously and be more or less an exact but amplified copy of the Input, je the output is @ linear representation of the input, Many class A transistor amplifiers, eg audio frequeney and radio frequency amplifiers, are linear circuits. ‘THE TRANSISTOR AS AN AMPLIFIER First ofall we need to look at how the bias is applied in a practical circuit. In our previous examples batteries were used for the bias.If dc only is applied to the cireuit shown figure 11 then Rand Ry will divide the “supply voltage into the same ratio asthe Value of the resistors. So ifthe resistor values were SOKO and 20K0 then with a supply Voltage of 10V the voltages across Ri and Re ‘would be BV and 2V respectively. 44 Fig. 11 AMPLIFIER CIRCUIT - 2 ‘The voltage across the transistor must be 0.6V to overcome the barrier potential. This Could be achieved by removing Re and making R, of such a value so that 0.6V is, ‘dropped across it, however, he problem here would be Rs would have to be quite low ‘and the amplification would be restricted, ‘The voltage across the base emitter junction (Vee) must be O.6V and is the difference between the voltage across Ry and Re, Vow = Via ~ Vie Tat wae Fig. 12 AMPLIFIER CIRCUIT - 8 ‘So Remust be ofa value that when the standing de current is flowing 1.4V will be dropped across Rr leaving Vac to be 0.6V. ‘Soin the static condition, ie de only applied, a standing current (quiescent current) ows through the circuit and TR, Ry, Rs and Re provide the bias necessary to operate TRI and allow current to ow.Fig. 19 AMPLIFIER CIRCUIT - 4 With current flow through R. and TRI there will be a voltage drop across R. Assume this vollage drop is SV so that the standing voltage is 10-5 = 5Y, ‘This is the condition that when de is applied to the amplifier, all bias voltages are applied and a standing voltage is at the collector of TRI. This transistor is said to be in ‘ts quiescent (quiet ~ no signal input) state [Now applying a signal to the amplifier. This will be a small ac signal (which may be superimposed on a de level), so only ac must be applied to the amplifier. Capacitor C) will block any de component, and aiso the output amplified ac value rust only be passed onto the next stage if again C, blocks a de component. These capacitors are known as COUPLING CAPACITORS. Its also essential that the voltage across Re remains constant, and therefore Vas remains constant so that the ac input signal adds to and subtracts from the steady Vee bias. Fig. 14 AMPLIFIER CIRCUIT WITH COUPLING/ ‘DECOUPLING CAPACITORS ‘To ensure this, a capacitor is connected across Re, This capacitor will have a ‘capacitive reactance at the operating frequency very much lower than Re This means that ifthe ac by-pasees’ Re it will eave a steady de across Re. This capacitor Cs is known as a DECOUPLING CAPACITOR,Note the figures quoted are purely explanatory, and actual values will depend on the individual circuits, Also, the transistor used is an N-P-N but everything applies equally fas well when using a P-A-P transistor except the positive rail would be at the bottom, Action With an ae Signal [Assume that with de applied the voltage at the collector is SV. Ifa 2.SmmV signal is applied as the input then when the ac signal goes positive it will add to the de bias ‘The transistor will switeh on more and the current through the transistor will increase and the voltage drop across R wil increase, so the collector voltage will fall. Assume it Ialls by 0.25V. +10 Fig. 15 AMPLIFIER ACTION - 1 ‘When the ae voltage goes negative, it opposes the bias and the transistor conducts Tess, the current through R, i lees so the volts drop is less and the collector voltage Fig. 16 AMPLIFIER ACTION - 2 So, with an input voltage of 2.5m¥ we get an output swing of 0.25V so therefore there isa gain of output) = O.25V = 100. input) 2.5m Note again the values used are for explanatory purposes only‘Also note the function of R, load resistor} without it there would be no voltage ‘changes atthe collector and no amplification. [Another purpose, (probably its more well known one) for Re, the resistor in the emitter lead, is a temperature compensating resistor. If the temperature increases, the resistance of the transistor decreases, this causes {greater current through the transistor and therefore a greater voltage drop across Re. Ifyou remember the voltage across the base-emitter junction is Via-Voe an this will ‘decrease thus reducing the forward bias, reducing the current, compensating for the original increase NB, A limit on transistor performance is Saturation Voltage. When additional increases in base eurrent no longer produce further increases in collector current, the transistor is said to be saturated, ie the transistor is turned ‘on’ as much as it can be. ‘This amplifier configuration is known as a COMMON EMITTER AMPLIFIER, As you have seen ithas a VOLTAGE GAIN Van. typically of 100 to 600, also has CURRENT GAIN ty = Le typically of 50 t0 300, Sa i So it isa current amplifier as well as a voltage amplifier, there is a current gain and voltage gain then there must be a power gain which equals Power out typically in the thousands, Power in ‘The input impedance is (2 Vi) typically 600 to 20000. And the outpt impedance is (2c Vas) typically 10 to SOKO, ‘Also note the phase relationship between the input and the output is 180" ‘The COMMON EMITTER amplifier i used for the majority of amplifier applications, “There are two other amplifier configurations, the COMMON BASE and the COMMON COLLECTOR. ‘Common Base Amplifier \With reference to figure 17, Ifthe input goes positive then the emitter is positive to the base and this reduces the bias voltage and the current through the transistor falls ‘The volts drop across R. falls and the voltage at the collector rises. When the input goes negative the emitter is negative with respect to the base and the bias increases, the current increases and the volts drop across R, will increase and the collector voltage falls,Fig. 17 COMMON BASE AMPLIFIER ‘Other characteristics ofthe common base amplifier are Current Gain (leis Less than 1, typically 0.98. Voltage Gain ‘Typically 500 t0 800. Power Gain Medium Compared to common emitter. Input impedance Low ‘Typically 500 to 2000. Output impedance High ‘Typically 100k2 to 10. Input and Output signals are in phase. Because oftheir very low input impedance and high output impedance they are used as impedance matching devices. Common Collector Amplifier (Emitter Follower) ‘When the input goes positive this will increase the bias, the transistor will conduct more and the volts drop across Re will increase and the top of Re will {go more positive, When the signal goes negative the bias will decrease, the transistor ‘wll conduct less the voltage across Re will decrease and the top of Re goes more negative Fig. 18 COMMON COLLECTOR AMPLIFIER -10-Other characteristics are: Current Gain (e/b) Voltage Gain Power Gain Low Input Impedance High Output Impedance Low ‘Typically 20 to 200, Less than 1 ‘Compared to Cy and Ce 20k0 to 100%9. 2081 to 5002, ‘The input and output signals are in phase, Because ofits high input impedance and low output impedance it again is used for impedance matching, Figure 19 shows the comparison between the three amplifiers. Each amplifier has the ‘word common in front. This means that the input and output signals are common to Whichever electrode is stated. COMMON EMITTER COMMON BASE COMMON COLLECTOR TEMITTER FOLLOWER) Ifyou have difficulty then: Identify SIGNAL IN ‘What is left is what itis all about: SIGNAL IN on base SIGNAL OUT on collector ce Hence common emitter. INPUT BETWEEN BASE & EMITTER ‘OUTPUT BETWh EN COLLECTOR & EMITTER INPUT BETWEEN EMITTER & BASE (OUTPUT BETWEEN COLLECTOR & BASE INPUT BETWEEN BASE & COLLECTOR OUTPUT BETWEEN EMITTER & COLLECTOR identify SIGNAL OUT } What's left? - emitter blank cue5 8 Fig. 19 TABLE OF COMPARISONS In many cases the amplifications of a single stage amplifier is insufficient and several Stages have to be used, If this is so the output of one stage is the input to the nest, ie they are connected in cascade, Fig. 20 TWO STAGE RC COUPLED AMPLIFIER sia.Figure 20 shows a resistor (Rs) and a capacitor (C:} coupled two stage common emitter amplifier, Another method of coupling stages of an amplifier i by using transformers. Using the Correct tums ratio the high output impedance of stage | can be matched to the low Input impedance of stage 2, thus giving a considerable increase in gain over RC coupled stages. However, due to the change in impedance with frequency, its frequency response is poor compared with the RC coupled amplifier. The uneven, response, shown in figure 20, causes distortion, However, they are often used hetween the output stage and a loudspeaker load. (High to low impedance matching} ow f FREQUENCY (cle) Pe Fig. 21 TRANSFORMER & RC COUPLED RESPONSE CURVES I the gain of stage 1 85 and the gain of stage 2 is 20 then the overall gain is 100 (5 x 20), The overall gain is the product of the individual gains.DIRECTLY-COUPLED AMPLIFIERS ‘Coupling amplifier stages to one another via capacitors or transformers makes it easy to couple together points with differing de voltage levels. However, this form of nupliier wall only amplify an alternating signal, completely ignoring de voltages and ‘wil respond poorly to signals of very low frequencies. Many control systems found in aircraft produce signals that vary only infrequently and this makes it necessary to se direetly-coupled amplifiers in order to amplify those variations, Careful matching of transistors and associated components is. tssential if these amplifiers are to perform correctly. They are particularly sensitive to ‘oltage and temperature variations. ‘Simple Direct Coupling of two Bi-polar Transistor Amplifiers With reference to figure 23. The emitter bias resistor in TR2's circuit (R} produces series current negative feedback, reducing the averall gain of the amplifier to a Fig. 22 DIRECT COUPLED BIPOLAR ‘TRANSISTOR AMPLIFIER Direct Coupling with Zener Diode Bias [A Zener diode in the emitter circuit of TR2 (Sigure 24) maintains a constant voltage at the emitter and thus increases the overall gain of the amplifier. It also goes some way towards decreasing the eflects of any variation in supply voltage. 4ae “K Fig. 24 DIRECT COUPLING WITH ZENER DIODE BIAS DIFFERENTIALLY CONNECTED AMPLIFIERS 1f two identical dreetly-coupled amplifiers have the same power source, then a change in supply voltage will not cause a change in the difference of their outputs. There is similarly no change in the difference of their autputs ifthe ambient temperature changes, The only thing that wil produce a change in the difference at their output is ‘variation in thet signal inputs. ‘The ‘Long-Tailed Pai Differential Amplifier Figure 25 shows the arrangement ofthe ‘ong tailed pair. Note the output is across the collectors of the two transistors, and that they have a common efitter via resistor Ri Fig. 25 THE LONG TAILED DIFFERENTIAL AMPLIFIERW SM WN ‘The Darlington Pair ‘This arrangement (figure 26) gives a high current gain. It can also be used in the Common Collector or Emitter Follower eonfiguration with currents in the order of nnlliamps, in which case its main benefit the increase in input impedance due to the redtiction of current taken by the first transistor. CLASSES OF AMPLIFIERS When @ transistor is used as an amplifier the input circuit is normally biased to some particular working point, There are three basic classes of bias, named according to the ‘working point chosen, (Class A. The amplitude of the input signal and bias are such that there is an output current forthe fill eyele ofthe input signal. This is the most commonly used class of Dias in amplifier circuits. Class B, The bias is such that current flows for only half ofthe cycle of input signal, for the other half of the input eycle the transistor is ‘cut off. This is usually employed in poser amplifiers, Class C, The bias and amplitude of input signal are such that current flows for less than half of each cycle. Used in oscillators and selective amplifiers Efficiency “This is defined by __ae power output to load x 100%, de power taken from supply An amplifier which produces low power output has an efficiency which is no greater ‘than 30%, ‘This is Because itis working under Class A conditions and the de standing {no input) current is large and produces wasted de power. -16-‘To overcome this problem in power amplifiers the push-pull amplifier was introduced, cuss Sorat Fig. 27 GRAPHS OF INPUTS & OUTPUTS FOR CLASSES A, B, & C AMPLIFIERS Push-Pull Amplifier Figure 28 shows a simple push-pull power amplifier using an N-P-N type and P-N-P type transistors, The load is a loudspeaker and is connected to both emitters vin a de blocking capacitor. Operation When an input is applied, assuming at this moment in time that the input at Ais positive to B (positive half eyele), the base emitter junction of TR is forward biased ‘There is therelore an output to the loudspeaker (positive half eycles). During this time ‘TR0 is reverse biased (base negative with respect to emitter) 7.Fig. 28 PUSH-PULL AMPLIFIER Negative half eycles ofthe input (B positive to A) will reverse bias TR, and it will cutoff and forward bias TRo, this time there is again an output; this time on the negative half cycles, AAs each transistor conducts for one half of each complete input eyce, the amplifier is ‘working in Class B conditions. When there is no input, neither transistor conducts, therefore no de power is wasted. ‘The masimium efficiency of a Class B power amplifier is high (78%) when compared with a Class A amplifier (50% Cone disadvantage ofthe simple circuit is that each transistor does not turn on until the input is about 0.6V. Asa result there is a dead zone producing ‘cross-over" distortion (see figure 25) blank 218Von Fig. 29 CROSSOVER DISTORTION ‘This is overcome by forward biasing the base-emitter junctions of both transistors, Figure 30 shows a push-pull amplifier with this biasing to the two transistors being provided by resistors R,, Rs and Ry vis the secondary winding of transformer T1, f= a Fig. 90 PUSH-PULL AMPLIFIER -19-Operation, Under static [no input signal) conditions, equal currents will low through the two halves of T2's primary winding and through the two transistors and RS to the -ve rail ‘There wil therefore be no resultant Mux in T2 from this de source. Therefore no de ‘power is wasted and its efficiency is high (78%) ‘Transformer‘T1 is a phase-splitter, providing inputs to the transistors which are equal but in antiphase, ‘When the top of T1's secondary winding is positive, TRI will be switched ON (eirewit ‘va base-emitter ~ Cl) and TR2 will be switched OFF. As the collector eurrent of TRL Jnereases, that of TR2 decreases. More current will low from the +ve rail through the {op half of 72's primary winding, collector ~ emitter TRI and RS to the ~ve rail, When the bottom of T1's secondary is positive, TR2 will be switched ON (circuit via ‘base-emitter Cl) and TRI will be sitched OFF. As the collector current of TR ‘mereases, that of TRI decreases. Current will low from the 4ve rail through the bottom half of 72's primary winding, collector ~ emitter of TR2 and RS to the -ve ral, ‘The changing currents in the primary of T2 results in an output which is an amplification of each balf of te input signal. ‘This is then operating in Class AB conditions, being a compromise between the low Gistortion, low efficiency Class A ampliier and the higher efficiency, higher distortion (Class B amplifier MULTIVIBRATORS ‘These ae transistor switching circuits of two stages with the output of one stage being fed back to the input of the other by coupling resistors or capacitors. The output of One is ‘high’ the other is Tow and this occurs alternatively producing a square wave ‘output, There are three basic types: 1, stable or fee running multivibrator. 2. Bistable or fip-flop, 3. Monostable of ‘one-shot: Figure 31 shows the basic circuit of a Bistable Multivbrator. Operation When the de supply is switched on then, because ofthe slight differences in manufacture, one transistor will conduct more than the other. This causes say, TR: to ‘switch fully on while TR, switehes off -20-BISTABLE Fig. 31 BISTABLE MULTIVIBRATOR cov [AC this point TR, collector voltage is low (high voltage drop across Ro), there is therefore insufficient voltage to drive current through Ry to the base of TR. TR: remains off and its collector voltage being high there is current flow through Roto ‘maintain TR, switehed on, The output at Qis high (logic state 1) and the output at] Js low (logic state 0) By applying a positive signal to the base of TR via Re (shown on the diagram as a Switeh but ina practical circuit would be a temporary input signal) TR: would Conduct, causing it collector voltage to fall to a low valve lower than 0.64). TR: base current ceases and TR) switches off, its collector voltage rises to a high value and this fs feq through R; to the base of TR Keeping it switched on. Q is therefore low (logic 0} and Qi high and therefore at logic state 1 Bach transistor can be made to ‘ip' toa high collector voltage oF flop’ to a low collector voltage changing the outputs on Q and Q. The switching can also be achieved by applying a negative voltage to the base of the transistor that is conducting ‘The inputs R & $ would be supplied by a trigger pulse and thie circuit is the basis of the SR flip-flop Q = 0, Q~ 1 reset condition. Q lused in memory circuits and binary counters in digital computers, ASTABLE MULTIVIBRATOR ‘When the supply is connected as before one transistor conducts faster than the other (due to slight manufacturing differences) and cuts the other one off. In this, Imultivibrator each transistor then switches atstomaticaly to its other state and then back to its first state, producing an output of square wave pulses. Action With reference to figure 92. Assume TR: ON and TR: OFF. The base of TR: is negative at the moment, but is approaching cut on (base voltage going positive) on atime ‘constant determined by C2 Ro, sane8, % Fig. 32 ASTABLE MULTIVIBRATOR ‘When TR conducts, its collector voltage falls to a low value and since eapacitor C1 cannot change its charge instantancously there is no change of capacitor voltage during the rise of conduction of TR, “Therefore the fall of collector voltage at TR; causes TR: base to fall by the same amount causing TR, to cut off, causing TR: collector voltage to rise ‘This multivibrator produces a continuous stream of almost square wave pulses, ie itis {a square wave oscillator. It requires no input tigger and is ‘Sometimes called a relaxation oscillator. It is extensively used for producing timing (clock) pulses for digital systems. Remember, everything in computing works in synchronisation with a (very fast) clectronie clock MONOSTABLE VIBRATOR With reference to figure 33. Again, when the supply is switched on the cireuit settles into the state TR, OFF and TR: ON, therefore Q= 0. A positive trigger pulse, represented by the switeh in the diagram will switch TR; ON, Cy right hand plate falls Fapidly switching off TR, making the outpat Q go high. Now the capacitor charges up through Re making the right hand plate go low TR) is switched on again and the Q ‘output goes low. on Jaourmer Liv Fig. 33 MONOSTABLE MULTIVIBRATOR -22-‘This muttivibrator has one stable state and one unstable state. It can be switched into its unstable state fora certain time (determined by the values of C and R) and then returns to its stable state. It ean be used to create a pulse of known timing to act as a delay circuit in digital eystems, ‘The Multivibrators we have seen are using junction transistors, however, they ean be constructed using Pield Effect Transistors (FETs) logic gates and operational ‘amplifiers (tobe discussed later) FUP-FLOPS ‘THE JK FLIP-FLOP Figure 34 shows the JK flip-Nop. Study it for a few minutes and note the layout of the system inchuding the inputs at J and K. Operation ‘Suppose that TR# is conducting and that TR3 is cut off. Q is at logic 0. Iflogic 1 is Applied to.) and logic Oto K, there would be no effect because there would be no ‘change to the diodes DI and D2. A Tallin (1-0) signal at T will cause the transistors to ‘change over in the usual Way, so Q now goes to logic 1. However, a further falling pilse at T will have no effect on the eieuit if! is stl at logie 1. Te follows, therefore, thata trigger pulse at T will only change the state ifthe ogic levels at J and K are reversed. From this it can be seen that A TRIGGER PULSE AT ‘T WILL ONLY CHANGE THE STATE IF THE LOGIC LEVELS AT XI’ AND ‘Q' ARE DIFFERENT. 1t also follows that a Logic O or a Logic 1 can be stored at J until a trigger pulse arrives at T, ‘when it will be released at Q -23-‘THE RS FLIP FLOP With reference to gure 35 (circuit and symbol). When power is applied, current- biasing will be applied to each transistor base-emitter by way of 2-R4 to Tl and RI- Ra to 72, Although the two ‘sides’ are identical, mis-matching will mean that one transistor wil start to conduct before the other. If silicon transistors are being used, (0.6 valts is needed across the base-emitter for switching ON. Fig. 35 RS FLIP-FLOP CIRCUIT & SYMBOL ‘Suppose that T2 reaches the point of switch-on before T1. When T2 conducts, the volts drop across R2 becomes almost 6 volts and the T2 collector voltage now applied via Ré to the base of 71 becomes almost 2er9, forcing TI into a ‘cut-off non- ‘conducting condition ‘The volts drop across RI is almost zero and $0 6 volts is applied via RS to the base of ‘72, keeping it switched hard-on, Under these conditions, the two outputs are: ‘Teix volts (Logic 1) and Q zero volts (Logic 0) {A positive pulse at $ (SET) will cause Tl to conduct and the ensuing volts drop across. RI will switch 72 off. The two outputs will now be: ‘Tero volts )Logie 0) and Q six volts (Logie 1). A positive pulse at R (RESET) will end the outputs back again to the original Condition. 80, a pulse at $ sete Q at Logic 1 and a pulse at R sets Q at Logic 0. ‘These devices are widely used in storage and timing device circuits FIELD EFFECT TRANSISTORS. ‘There are two basic types of Field Effect Transistors (FET's). A Junction Gate FET (JUGFEN and a Metal Oxide Semiconductor FET (MOSFET)JuoreT With reference to figure 36. The bar of N-type matcril provides the medium through Which the majority carriers (electrons) pass. In doing 80, they have to pass between. the two sections of P-type material, known as the Gate. Fig. 36 JUGFET ‘The two P-type sections are usually connected together electrically (so are atthe same potential) and are used as the Control electrode, Current enters at the SOURCE, tlectrode and leaves at the DRAIN electrode. As in any semiconductor device containing P.N junctions, depletion zones exist at these junctions, In this device, the P-type gate Sections are more heavily doped than the N-type channel. This results in the depletion zone extending further into the ‘channel than it does into the gate Note. The opposite arrangement of a P-type channel and N-type gate is also available wow =P, Fig. 37 JUGFET SYMBOLS Operation With reference to figure 38. The Drain-Source voltage Vos sets up a current fow of majority carriers through the channel, The Gate-Source voltage Vos reverse-biases the gate-channel junction, thus increasing the width ofthe depletion zones, As can be seen in the diagram, these zones are not uniform in shape 25‘This is because the potential gradient between drain and source produces a grester potential diference between the gate and the channel towards the drain than it does fowards the source. Thus we have characteristic wedge’ shaped depletion zones. | |e" ests sance_! love © 8S nun Jeece 2 ee 1 Pec mS ove | Le (isweeeetXe® Ld ors zone Vos pemeieare |______4, J Fig. 38 JUGFET SCHEMATIC Since no majority carriers exist in the depletion zones, the width ofthe channel through which they can flow is dependent on the size of these zones and hence on the valle of Vos Its in this way that Vos controls the current flow. Under normal Operating conditions, the gate-channel junction is reverse-biased so that only a very Small leakage current flows in the gate-source circuit. It has, therefore, got avery high Input impedance ‘The JUGFET can be used as an amplifier or a ¢witch and the next diagram shows it ‘connected as an amplifier. Its input resistance is very high compared with that of a transistor (1x 10090 compared to 1 to 5kOt for a transistor). ts output impedance is SOKO to1M@ compared to a transistors output impedance of 10-50%. NOTE: Rg Maintains a High Input Impedance. Fig. 39 JUGFET AMPLIFIER -26-MosrEr Also called an Insulated Gate Field Elect Transistor (IGFET) The basie construction of fan n-channel MOSFET and symbol is shown in figure 40. =a Fig. 40 MOSFET CONSTRUCTION & SYMBOL (N CHANNEL DEPLETION) ‘The main difference between this device and the JUGFET is that there is no direct éleetrical connection between the gate terminal and the semiconductor material. Instead they are insulated from one another by a very thin layer of highly insulative silicon oxide Fig. 41 MOSFET OUTPUT CURVE (N CHANNEL DEPLETION) ‘The voltage between the gate and the source [Vas) controls the electron concentration in the channel. Ifthe drain (D) is made positive to the Source (S) and Vos is zer0 & ‘current will low. IfVos is made negative, positive holes are atracted into the channel 0 reducing the numberof fee electrons in the channel and therefore channel current ‘decreases, This is known as the DEPLETION MODE. If Vos is positive, electrons are attracted into the channel from the P substrate increasing current flow - this is known ‘as the ENHANCEMENT MODE. If P-channel FET (Sgure 42] was used in the ‘enhancement mode, the condition is by holes. sarAU 3: Fig. 42 MOSFET CONSTRUCTION & SYMBOL (8 CHANNEL ENHANCEMENT) ‘The MOSFET has a higher input impedance than the JUGFET > 1 x10™2, however its Output impedance is similar to that of a bi-polar transistor 10 to SOKA. When used as ‘switch te ewitehing time is very fast. ‘ma Vos = 200 Fig. 49. MOSFET OUTPUT CURVE (N CHANNEL ENHANCEMENT) ‘The MOSFET structure is compact an widely used in integrated circuits. Great care has to be taken to protect MOSFETS from electrostatic charges which could brealt down the insulated oxide layer. They are supplied with a metal clip short circuiting the feads, which should be left in place until connected in the circuit, CMOS (Complementary Metal Oxide Semiconductor} ‘This is one of the most important families oflogic gates which uses a P-channel and an N-channel MOSFET to create all the relevant logic gates. An example of an invertor gate is shown in figure 44, ‘The great advantage of CMOS is that in both the HIGH and LOW states the current constimption is very small (1 x 10%). Power consumption is therefore low and the fan, ‘out is high (typically 50), The speed af operation is poorer than TTL. -28-——— Moo - 10 te Va Fig. 44 CMOS INVERTOR GATE, FEED-BACK IN AMPLIFIERS Feedback is the return of a portion of the output signal of an amplifier back into the input signal ofthe same system. There are many variations on this but the following deals with the broader principles, 7 = Fig. 45 FEEDBACK AMPLIFIER ‘There are generally two types of feedback - which, incidentally, occurs in all forms of control systems whether mechanical, electrical, electronic etc, these are Positive Feedback and Negative Feedback.Positive Feedback \When the returned portion ofthe output signal assists the input signal, itis called Positive Feedback, This causes an increase in the overall gain. It can be many times larger than the gain without feedback, but can also lead to instability and oscillation. ‘The Gain of an amplifier with Positive feedback is given by Where Ar= Gain with feedback ‘A = Gain without feedback B = Feedback fraction ‘Output tunity, the gain is infinite and oscillation "Negative Feedback ‘When the returned portion ofthe output signal opposes or tres to cancel the input ‘Signal, i is called Negative Feedback. ‘This is the most common form of feedback (in all control systems), having several advantages and uses, ‘The Gain of an amplifier with Negative feedback is given by: A= _A__ which gives @ reduction in overall gain. Tea Negative Feedback is used to: (o) Improve the stability ofthe gain, [¢ is less affected by changes in {ansistor parameters and temperature changes. (b) Effectively change the input and output impedances. le} Reduce ‘noise’ and distortion, {a} Increase bandwidth (see below Frequency Response and Bandwidth ‘The GAIN of an electronic amplifier is determined by such things as the type of amplifying device being used and by te associated circuit components. Any particular Circuit arrangement will provide maximum gain at a single frequency (or over a narrow band of frequencies) and less gain at all other frequencies. Since many amplifiers are Fequired (o provide amplification over a wide range of frequencies itis common practice to provide each amplifier with a graph showing how its gain varies with frequency. This i known as the amplifer’s Frequency Response Cure. Figure 46 shows an exampleaawoworn Fig. 46 FREQUENCY RESPONSE CURVE ‘The Effects of Negative Feedback on Bandwidth, An amplifiers gain is generally considered to be adequate as long as itis equal to, or freater than, half the Maximum Power Gain, ‘OR An amplifiers gain is generally considered to be adequate as long as itis equal t0, or freater than, 0.707 of the Maximum Voltage Gain, ‘The range of frequencies over which this requirement is satisfied is kmown as the amplifiers BANDWIDTH. As stated above, negative feedback has the effect of reducing the gain of an amplifier but it also has the very valuable effect of increasing its bandwidth. Figure 46 shows graphs of an amplifiers gain and associated bandwidth, both with and without, negative feedback. OSCILLATORS. ‘With reference to figure 47 assume the capacitor is charged from an external supply: ‘When the switch is closed the capacitor will discharge, thus changing magnetic field cautses an induced voltage into the coll. The back emf opposes this discharge and this therefore takes some time. Eventually the capacitor discharges and its electrical energy has been transferred to the coil. At this time the magnetic field begins to collapse, current now flows to charge up the capacitor, lower plate *ve. -a1-‘once charged the capacitor discharges in the opposite sense creating a magnetic fetd ‘of opposite polarity Fig. 47 SIMPLE OSCILLATOR CIRCUIT ‘This oscillation would continue indefinitely ifthe circuit had no resistance, but the coil, hhas resistance, so the oseillations gradually decrease. To maintain the oscillation some nergy must be continuously fed into the LC circuit. Most oscillators are amplifiers, Wwith postive feedback which means the feedback is in phase with the input and Imalees good the energy losses in the oscillatory circuit, Radio Frequency Oseillators ‘With reference to figuee 48, the basic operation ofthis circuit is as follows: ‘Switching on the power supply charges up the capacitor and starts the oscillations. Feedback is obtained by the changing magnetic feld jn Ll inducing an emf into L2. ‘Thus em is applied between the base and emitter, which causes more collector current and therefore more current in LI, this continues until oscillation is maintained © Vee Fig. 48 OSCILLATOR CIRCUIT “The feedback from L2 being enough to draw de from the supply to make good the energy losses and keep the oscillation going. So the oscillator converts de to ac. For very high frequency stability crystal oscillators are used in the range 1 to 10MHz Audio frequency oscillators using resistors and capacitors are used up to SOME. You have already seen the commonest square wave type oscillator, that is the Astable Multvibrator -92-‘THE TRANSISTOR AS A SWITCH ‘The transistor has no moving parts and can switch at very high speeds. 1n switching applications the transistor is treated as a two state device, ie the transistor is either fully conducting or cut-off In figure 49, when the input voltage reverse biases the base-emitter junction and the transistor is cutoff and acta as an open switch, Ifthe input voltage switches to a large forward bias the transistor will conduct and act asa closed switch. Fig. 49. THE TRANSISTOR AS A SWITCH Fast switching is desirable and N-P-N types are preferred because their majority carriers, which are electrons, travel faster than the majority carriers (holes) in P-N-P types, MOSFETS can be used as switches, their switching speed being about ten times {ister than a transistor. INTEGRATED CIRCUITS Aan integrated circuit (Cis a complete electronic circuit on a chip of silicon about ‘Smm square and 0.5mm thick. Figure 50 shows a typical IC cutaway so you can see the silicon chip in the centre and the connectors radiating from it tothe pins. The diagram shows a dual in-line package, but eircular packages are also available. -33-ICs are assembled this way to allow their fitment to PCBs (Printed Circuit Boards) ete Otherwise they would be too small for handling and connection purposes, he x8) Fig. 51 SILICON WAFER Silicon is the base material used, as it has a high degree of purity and a continuous regular monocrystaline structure. A silicon wafer (igure 51) about 10cm in diameter fs produced onto which hundreds ofIC’s can be formed. Figure 52 shows how areas of silicon oxide deposited on the silicon are selectively removed. [tis basically a photographic process where areas of the chip are masked land then the surface is subject to uv light. The unmasked areas are ‘eaten’ away using ‘solvent leaving those areas that are required. Finally the unmasked silicon oxide farea is removed by etching, Figure 59 shows how a transistor is made using the diffusion process, ie exposing the wafer at high temperature to the vapour of boron or phosphorus so their atoms diffuse through the window producing a P'or 'N'type area. Monolithic integrated circuits are manufactured by an extension ofthe planar diffusion process, The active elements (transistors), and the passive elements (diodes, resistors and capacitors) are all created by modifying the conductive properties of the silicon -34-wr —plell le rerum i peer pruurrarcuieoraro ig. 62 1¢ PRODUCTION -1 “Seo pm omnes oo SI east fL 1 nsceynoon Ps een eens weocmrmere, (Ld) rea Fig. 53 IC PRODUCTION - 2 Integrated diodes are made by forming a P-N junction similar to that previously deseribed, Integrated resistors are thin layers, the resistance being defined by the length and width of the ayer. integrated capacitors are made by using the Capacitance of reverse biased P-N junctions, -35-Hybrid integrated cireuits use film techniques to form passive components and interconnections on an insulating layer. However, the active components are produced separately and designed for direct attachment to the interconnections ofthe film ‘There are two basic types of IC, 1, Linear (analogue) and 2. Digital (logic) Most Linear IC's are based on bi-polar transistors but in some cases FET's are used exchisively or in addition to bi-polar types. The majority of today’s linear integrated circuits use operational amplifiers (op-amps) (OPERATIONAL AMPLIFIERS. Atypical op-amp contains twenty transistors as wel as resistors and small capacitors, ‘The chief properties of op-amps are: 1, Very high open loop gain, 2, High input impedance (1 x 10° to 1 x 10°29). 3, Low output impedance (typically 10000), ret ; tor. Le Pe Lee 2 a @Pr@ Of Lele Fig. 54 CIRCUIT - OPERATIONAL AMPLIFIER =36seg [avec 21 Ibe ved are Fig. 85 SYMBOL With reference to figure 56, the basic op-amp has one output and two inputs. The NON-INVERTING (NI input is marked + (PLUS) and the INVERTING () input is ‘marked ~ (NEGATIVE), In the diagram point E is the common reference for the input ‘and output volts, The de power supply is typically #5V to +15V with OV being the reference level. ‘With the N1 input grounded (chassis potential), an input at I, causes a voltage of opposite polarity to appear at the output. ‘To achieve the high gain necessary Darlington pairs are used and usually two oF more differential amplifiers are putin series to increase the gain stil farther. This is done tusing two differential outputs to drive the differential inputs of the next stage. The last amplifier ie usually a complimentary class B amplifier. | ] ae ig. 56 BASIC OP-AMP CIRCUIT USED, eT out soos Ja Hoa of an ae eee eee “37\With the T input grounded and an input at NI, causes a voltage ofthe same polarity to appear at the output. ‘when signals are applied to both input terminals the output is the difference between to the two inpits fe two identical signals wil produce zero output. The op- amp is basicaly a differential amplifier. Fig. 58 OP-AMP SYMBOL Although the power supplies positive and negative are shown in the basic ‘op-amp symbol they are usually omitted on wiring diagrams, Most op-amps use negative feedback, ie feeding some of the output back to the inverting input. The coupling between the stages is direct coupling. In practice even ‘when de bias conditions are met and no input signal is applied, there may be a small Voltage at the input, called the differential input offeet voltage. it may be caused by Uifferent manufacturing tolerances of the components ofthe op-amp. This offset voltage produces a voltage at the output (ith no input signal remember) and in Certain applications is undesirable. For the 741 op-amp this is achieved by placing a ‘arlable resistor across the offset null pins (1 and 5) and adjusting it until the output jg zero when the input is zero Im ac operation a coupling capacitor at the output removes any de component caused by the affect voltage, Slew rate is the maximum rate of change of large amplitude ‘output voltages that an op-amp can allow before it behaves non-linearly, itis ‘measured in volts per micro-second (Vt). As previously stated the op-amp is basicaly a differential amplifier soit is useful —- ig. 68 TWO INPUT ‘AND’ GATE SYMBOL -43=o tH Fig. 69 ELECTRICAL ‘AND’ GATE CIRCUIT ‘The AND gate can be made up electrically by two switches in series. The lamp will only light when switches A AND Bare bath made. Irany one switch is open the lamp will pot light. ‘The operation of the logic gate can be described by means of a TRUTH TABLE, When switch A is open (logic 0} and switch B lamp Gogic 0) open (logic 0) there is no output the When switch A is made logic 1) and switch B is open (logic 0} there is still no output to lamp (logic 0}, ‘When switch A is open (logic 0) and switch B is made (logic 1) ~ still no output to the lamp (logic 0) When switch A is made (logic 1) and switch B is made (logic 1) there is an output to the lamp flogie I). So when A and B are logic 1 then there is an output, ‘This is summarised in the truth table. a 0 1 ° 1 Where A and B are the inputs and S is the output, only 2 inputs are shown but there may be mote A, B,C, D ete ‘The Boolean expression for this gate is written A.B = S. The dot means AND, and the expression is read a8 “A AND B equals S” fin some books the output is called 2), For a three input AND gate the three inputs would be A, Band C and the Boolean expression would be A.B.C= 8. ‘The OR Gate ‘This can have 2 or more inputs and will give an output if any one input is logie 1 Fig. 70 ‘OR’ GATE SYMBOL -44-- _ Fig. 71 ELECTRICAL ‘OR’ GATE CIRCUIT Atwo input OR gate circuit can be made up by two switches in parallel, The lamp will light if switch A OR'B is closed, So the truth table is Both stitches open Switch A closed Switch B closed Switches A and B closed meece ‘The Boolean expression is A + B = Sand the + means OR and the expression is read a "A ORB equals S” ‘The NOT Gate ‘This gate has one input and one output po ox Fig. 72 SYMBOL FOR A‘NOT’ GATE ‘This gate produces an inversion of the input signal, so when the input is A the output is NOT A, which is symbolised by a bar on top of the A= A. So the output ofthis gate is the opposite to i's input. So input logic 1, output logi 0. Input logic O, output logic 1. The truth table is ays io ofa ‘The Boolean expression is: S =A ‘The line above the A means NOT; the expression read as “S equals NOT A”. 245‘The NAND Gate ‘This is short for NOT AND and works similar to a NOT gate except that it has more [ »— Fig. 72 SYMBOL FOR A NAND GATE ‘The bubble on the end of what is an AND gate has the same function as in the NOT {gate it inverts the signal, except that in this case more than one input is involved. In this gate when A is 0 and B is 0 then the output is 1, In the AND gate this would be 0. So the NAND gate is an inverted AND gate, ‘The truth table is aAyB Is ojo |i neo la ofa fa Aor lo ‘The Boolean expression is: KH =S The bar over AB gives NOT AND and is read as "NOT (A and B) equals S” ‘The NOR Gate ‘This is short for NOT OR and is simply'a negated OR gate 2 Fig. 74 SYMBOL FOR A NOR GATE Again an input A = 0 and B = 0 would, for an OR gate, give 0 as an output, but for the NOR gate it would give a 1 as an output. The truth table is: vorem ‘The Boolean expression is: AVB+S The bar over A+ B gives NOT OR and is read as *NOT (A ORB) equals 5" =46-‘The XOR Gate ‘The OR gate gives an output when A ORB = 1 and when A AND B= 1, The XOR gate only gives an output when A ORB are 1 not when A AND B ae 1. This means itis exclusively an OR gate and will not work with the AND function, itis read as a two syllable word x then or. Fig. 75 SYMBOL FOR XOR GATE, “The truth table: ale |s ol e. leo 1 |o fa oe | r|a fo ‘The Boolean expression: RB+AB=s Which is read as "NOT A AND B, OR A AND NOT B, EQUALS S*. It should be appreciated that for all of the above we have assumed logic to be postive {about =SV de) and logic Oto be zero (about OV). This is called positive logic fand is the notation most frequently used. However, negative logic may be used, and this means that logic O is positive (+5V) and logic 1 is zero (OV). Positive logic i used throughout this book Note. Any bubble (small circle) at the end of a logic line as it connects toa gate inverts or negates that signal before it enters the gate [As a consolidation exercise, work through the following example and then try the logic circuits Activity section that follows, df): 1 2 Loaic cIRcUT 1 Example. With reference to logic circuit 1. What is the output logic level Sif A = logic 1, B= logic 0 and C= logic 0? With A = 1 and B = 0. Bis inverted because of the bubble so the inputs to gate 1 is 1 and 1 80 the output is 1. The inputs to gate 2is 0 and 0 (0 from Cand the 1 is, inverted) s0 S must equal 0. a.‘What would be the Boolean expression for this circuit? Working from the first gate ‘The output from gate 1 is A AND NOT B= AB ‘The output ftom gate 2 is NOT (A AND NOT B] AND C = AB.C acTiviTy Study the following logic circuits and determine the output logic level foreach, tp | =>—p— LD. Loic ciRCUTT 3 “There are two main types of logic circuit: 49] TTL (Transistor Transistor Logic) 1b) CMOS (Complimentary Metal Oxide Semiconductor ‘The following shows the scales of integration which refer to the number of gates contained in a single package: + Small Scale Integration (SSI) not more than 11 gates, * Medium Scale Integration (MSI) = up to 100 gates. * Large Scale Integration (LS!) between 100 ~ 1000 gates, * Very Large Scale integration (VLSI) containing over 1000 gates. ‘The fllowing diagrams show some TTL and CMOS gates -48-Fig. 77 TTL‘NAND’ GATE, Figure 77 shows a two input NAND gate which uses a multiple emitter N-P-N transistor. IF both inputs to TI are high, then no current lows from the base to the emitter. Current does flow through the base collector circuit to switch on T2. The output F is near zero volts. Ifeither input A or B go low then TI conducts. As a result TI passes a momentary collector current to ground in the form of positive charges stored in the base of T2, which goes negative. 72 switches off, output goes high. blank 49.ot 2 . a: : p 7 io “ls 1B. . Fig. 78 CMOS ‘NOR’ GATE, “sv a ae] {Ae i Fig. 79. CMOS ‘NAND’ GATE Properties of TTL and CMOS ‘TTL uses bi-polar transistors along with diodes and transistors formed to microscopic dimensions on a slice of silicon (chip). TTL must have a steady SV de supply, while ‘CMOS will work on de voltages between 3 and 15V and usually requires much less power. CMOS uses tni-polar Field Effect Transistors (FET) with metal-oxide-silicon technology; this lends itself to VLSI as they take up less room on a chip, compared to the TTL, CMOS has a much higher input impedance. (One important point with CMOS is that if state electric charges are allowed to build upon i's input pins, these voltages can break down the thin layer of silicon oxide Instlation between the gate and the other electrodes of MOSFETs and this will destroy the IC. So antistatic protection is important.Gate operating parameters include: a) Speed of operation, >) Fanin. Fan out. 9) Noise margin ©) Power dissipation, Speed of operation ~ the time that elapses between the application of a signal to an input terminal and the resulting change in the logical state at the output terminals Fan in - number of inputs coming from similar circuits that can be connected to the gate without adversely affecting its performance. Fan out - the maximum number of similar circuits that can be connected to i's output terminals without the output falling outside the limits at which logic levels 1 and 0 are specified. Noise margin - this is maximum noise voltage (unwanted voltage that can appear at it's input terminals without producing a change in output state. Power dissipation ~ as in any circuit, supply voltage multiplied by the current (Power = Vx) gives the power in the eircuit and this heat must be dissipated ‘Typical figures for TTL and CMOS are shown below. Speed of Fan Fan Noise Power Operation in’ out margin dissipation ‘Standard TTL ons 810 av somw cmos sons 8501 Sy 0.001mw Ifyou look back at the diagrams for the TTL AND gate and the TTL NAND gate you will see that the NAND gate uses fewer components and is therefore cheaper to produce. ‘This also applies tothe NOR gate, ic it is cheaper to produce than the OR gate. [NAND gates can be connected together to form any of the other basic gates ~ thus reducing production costa by manufacturing one type of gate only. The following drawings show how the various gates ean be formed. ah Nor GATES pve} pp tp St Do h th aaa al [> 5 b> > Fig. 80 USE OF NAND GATES: Figure 81 shows the pin connections of ICs for different gate configurations. There is, ‘no need to remember them but it does give a good idea of how the chip (with the gates in) is connected ~ although the chip itself is 0 small that it looks like a piece of silver metal 4 or Smm square. s2-“HEE oo i) Pa be q g & & & q # 4 a Sct é a] a fa) = je) 1) 7 5 i be d oF q q is q 5 fc é fe) ja a] a] fe) 7 oa a 4 q q q 6 aq & g a By a 3] By [5 eo LS p I a Ua Wo ee Fig. 81 IC PIN CONNECTIONS IC’s are made which also perform the function of encoding, decoding, performing binary addition (adders) and multiplexers. ‘In sequential logic circuits fip-Nops are extensively used all of which are manufactured on IC's‘The SR Flip-Flop ‘The SR fip-fop has two output terminals Q and’@. Figure 82 shows the SR flip-lop ‘using NAND gates, With reference to figure 82 When $= 1 R=0 Q=1 Q=0 the fipsop is SET. a When $0 R=1Q 1 the flip-flop is RESET, When $= 0 R= 0 then no change occurs Q and @ will be what they were before. When $= 1 and R= 1 then Q= 1 and Q equals 1. The circuit is stable while S= R= I, butif they are changed simultancously from 1 to 0 then due to different ‘switching times of the gates we cannot predict whether Q or Q will be ‘The output state is said to be indeterminate so S = R= J should not be allowed to coeur. The truth table is shown below. s RQ 9 1 0 1 0 o 1 0 4 0 0 Depends on state before inputs applied 11 Indeterminate ‘So basically the Aip-lop can exis in two stable states: Q=1(9=0) or Q=01G=1)Clocks In sequential logic circuits where there may be a large number of ip-lops, itis important they all act atthe same time, so no circuit operates out of sequence. ‘This is achieved by @ CLOCK pulse from a high frequency pulse generator. The cicuita may be triggered when the clock pulse changes from 1 to 0 or whem it changes from 0 ta I (edge triggered) of when the level is 1 or 0. Figure 83 shows a clocked Si. flip-flop and gure 84 shows i's truth table nan | Tei ne ees . [= pH Ld | ‘orAWNG SrMABOL, Fig. 83 CLOCKED SR FLIP-FLOP ‘OUTPUTS [OUTPUTS pura | BeKoRE | “AFTER puts | clock cLock cock comments. PULSE PULSE PULSE Sale peagealere: oop fa to io NO CHANGE [a IN OUTPUTS, a ae ees fis gee] el | PLU TL OW BETS) po fof 1 [of 1 Pr fo] wig-1 & +0 Ooo 0 P-FLOP RESETS [SS ee A se a9 ee eae oe ceo ‘THIS INPUT Dro foe 1] Is Nor aLLowen, Fig. 84 TRUTH TABLE - CLOCKED SR FLIP-FLOP D Type SR Flip-lop ‘This is a modified SR fip-flop, The D stands for Delay. With reference to the truth table, when the clock pulse changes (rises), whatever is at D is transferred to Q, when the ciock pulse falls Q stays at that level ~ no matter what is applied to D will only ‘change state at the next clock pulse,‘The truth table shows that the output equals the input one clock pulse earlier, ie the data is held back until the clock pulse = 1. 1 PL exevoon Fig. 65 CLOCKED D TYPE FLIP-FLOP OUTPUTS ‘OUTPUTS, INPUT BEFORE, AFTER CLOCK PULSE. | CLOCK PULSE \-o}-lelo| 0 o r lolo|~|-[x Fig. 86 TRUTH TABLE CLOCKED D TYPE FLIP-FLOP, ‘The JK Flip-op Figure 87 shows the layout of the JK Flip-flop using NAND gates and figure 88 shows the truth table. eK ycL0ck) Per AL aleeOUTPUTS | DURING] —OUTOUTS 1 wrurs | ‘erore | ‘cock | °arrer cuock | PULSE Gtock | comments PULSE fuse _| | Ix alae ooo eo RO RANET ooo ours [steal eee is ee emo aa sO me TAYE AT OR SETS) pre peo fo toe tata oo oo sav ar on: OPT] opt] ttf of 1 RESETS To Om ee pea po 5 a ea ee Fig. 88 TRUTH TABLE JK FLIP-FLOP “The two inputs are called J and K and the operation is described in the truth table. J = K = | is allowed (unlike S = R= 1 in a SR flip-flop) and toggles (changes state) when this input is applied. Shift Registers, which store a binary number and shifts it out when required usually consist of a number of fiplops and manufactured in IC's as are counters and. ‘The Astable, Monostable and Ristable multivibrators are also manufactured on IC's using op-amps as shown in the diagrams below. -87-mmecer weur ‘rmocer nour Fig. 91. BISTABLE MULTIVIBRATOR PRINTED CIRCUIT BOARDS (PCBs) Im this technique metallic fol is bonded onto @ base board made from insulting material, and a pattern is printed onto the foil and chemical etching on to the fil forms a series of current conducting paths. The components are then mounted to the board and soldered to the appropriate points to make-up the circuit required. The boards are usually made-up of layers of phenolic resin impregnated paper, or epoxy resin impregnated glass-fbre cloth. ‘The thickness ofthe boards depends in the strength and stiffness required. The boards are manufactured in three basic configurations: 1) Single layer = These boards contain al printed ‘conducting paths on one side with the components mounted on the opposite side. 2) Multilayer + These have printed conducting, paths on both sides and the ‘components may also be mounted ‘on both sides.3) Multilayer sandwich = These boards are many thin boards laminated together with the components mounted on one or both external sides ‘The most commonly used conducting material is copper foil. Te bond the copper to the board, copper foil sheets are cut tothe sizeof the board and steel separate plates are ‘interposed between the layers as shown in figure 92. Fig. 92 MAKE UP OF PCBS ‘The layered sheets are bonded in a hot press. The heat during the pressing operation imclts the resin in the base material so that it flows and fully wets the material and the Copper foil. As polymerisation ofthe resin mix proceeds, each layer of base material reaches the flly cused state with the copper fail is bonded to it. When cooled each ‘board is trimmed to the required size, inspected and packed in polythene bags. [Next a master diagram must be produced to show clearly the conductor pattern (a sort ‘of wiring pattern) required and where the components are to be located. ‘This is ‘usually done by computer aided design techniques. “The printing process may be by the etching or additive process. In the etching proces the copper felis cleaned and coated with a photo-sensitive solution known as @ ‘resist, this solution has the property of becoming soluble when exposed to strong Tight ‘The master diagram is then placed over the board and exposed for a time in a printing machine. The resist ja washed away to leave the resist etched away around the circuit, pattern. The board is then placed in a bath of ferric chloride to etch away all the ‘unprotected copper,Fig. 93 ETCHING PROCESS An alternative process is the additive method. In this process the copper is deposited nig in the areas where conductors are required, Again the board is coated with a photo resist solution. A negative of the master diagram is then screen printed onto the board, exposing the areas for the conductor layout. These exposed areas are Chemically activated and the whole board is immersed in a copper plating solution, ‘when the required thickness is obtained the board is withdrawn from the solution, ‘The components are soldered to the board by two main methods (a) by hand, (6) mass soldering. In mass soldering all joints are soldered simultaneously by bringing the board into contact with an oxide free surface of molten solder, which is contained in a special ‘bath, The solder apecifieation for mass soldering is 60/40 tin/lead. To prevent fonidation a flux is used and in the automated mass soldering system a fuxer unit is Incorporated, removal of any flix residue is by solvents. ‘The zero vots line on a PCB is usually identified by having a wider track than any other track on the board, After manufactured organic costings (sometimes called conformal coatings) are applied to the surfaces. The type of coating depends on the protection required, i¢ temporary for permanent. Temporary protection is usually in the form ofa resin based compound Permanent protection is provided by epoxide or polyurethane based resins having very low oxygen absorption rates. They also have good resistance to humid conditions; are resistant to cracking and discolouration. Coatings are applied by brush, spray, roller or dipping 60(cee oaleron FRONT REAR Fig. 95 A TYPICAL DOUBLE SIDED PCB Fig. 96 BOARD COMPONENTS Flexible printed wiring circuits are available and usually serve as a means of interconnecting units and are basically copper foil conductors bonded to a base of thin flexible insulator (polyester, epoxy glass cloth and polyamide) and covered with the same material Printed circuit boards are widely used in components on a modern large transport aircraft. When removing or replacing these boards strict precautions must be observed, ‘The reason for this is that the static electricity or charge that we have in our body can cautse serious damage to the software of the components on the boards. The table ‘shows typical electrostatic voltages that may be developed. oi.ELECTROSTATIC VOLTAGES MEANS OF STATIC GENERATION RELATIVE HUMIDITY [5] I TOTO 20, 165.70 90 ‘WALKING ON CARPET 35,000 7,500) [WALKING on vIWWL FLOOR 12,000. 250, ‘WORKING AT BENCH, 6,000. 100 VINYL (PLASTIC) DOCUMENT ENVELOPES, eo Ges) | (POLY BAG'PICKED UP FROM BENCH | 30,000 1200) ‘CHAIR PADDED WITH POLYURETHANE Line 18,000 1,500) Fig. 97 TABLE OF TYPICAL ELECTROSTATIC CHARGES we were to touch the edge connectors or some other exposed metal part then a surge of current due to the dilference in potential between our body and the PCB would tautse damage to the components. The following table lists static ¢ Sensitive devices and voltages that can cause damage. These devices are often referred to as ESD's (electrostatic sensitive devices) RANGE WHERE ‘TYPE OF DEVICE DAMAGE CAN OCCUR o MOS FET 75070 1,000 ‘Mos 25070 1,000 BIPOLAR TRANSISTOR 4,000 TO 15,000, ‘SILICON CONTROLLED RECTIFIER ee 4,000 TO 15,000 ‘THIN FILM RESISTORS 150 T0 1,000 Fig. 98 TABLE OF VOLTAGE SENSITIVITY ‘To identify components fitted with ESD's a symbol is used on the line replacement unit (LRU) and associated documentation, transport bags etc. ‘To overcome the static discharge problem the person removing the PCB must use & conducting wrist strap which is connected to a convenient grounding point on the fircraft and the person, to initally discharge any energy within the body. -62-Sv & ‘TyPrcA. syMe0.S When removing an ESD PCB: (or any PCE for that matter electrical power is removed, the earthing wrist strap is connected to the ground (there is usually'a convenient point nearby on the aircraft) attach strap to your wrist and remove the PCB using the extractors provided. Place the PCE immediately into a special conductive bag (designed for ESD components) and identify with @ label, do NOT use staples or adhesive tape, Remove wrist strap if not immediately refitting a new PCB. Do not forget any documentation such as EASA form 1 and consulting the AMM and the IPC. you are removing the complete LRU then itis important you do not touch the ‘connector pis and place dust caps on all connectors. REMEMBER STATIC DISCHARGE CAN CAUSE DAMAGE!