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in
eg
) b
er
lex or b
p
i
a
t
or
mul
2:1 @(sel <= b;
/
/
) z
ays
alw (sel <= a;
f
i
e z
els
end
Ga
on
cti ry
t
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u
Lib Instremo
r ar M
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A
02/14/05
L05 Synthesis 1
configurations;
Transistor-level simulators;
Software generators to create dense transistor layouts;
1980 : Circuits had 100K transistors
In 80s designers moved to the use of gate arrays and
standardized cells, pre-characterized modules of circuits, to
increase productivity.
Tools:
To automatically place and route a netlist of cells from
a predefined cell library
The emphasis in design shifted to gate-level schematic
entry and simulation
02/14/05
L05 Synthesis 2
History continued...
IBM and other companies had internal tools that emphasized top
down design methodology based on logic synthesis.
Two groups of designers came together in 90s: Those who
wanted to quickly simulate their designs expressed in some HDL
and those who wanted to map a gate-level design in a variety of
standard cell libraries in an optimized manner.
6.884 - Spring 2005
02/14/05
L05 Synthesis 3
Synthesis Tools
Idea: once a behavioral model has been finished why not use
it to automatically synthesize a logic implementation in much
the same way as a compiler generates executable code from a
source program?
a.k.a. silicon compilers
02/14/05
L05 Synthesis 4
Simulation vs Synthesis
02/14/05
L05 Synthesis 5
Logic Synthesis
assign z = (a & b) | c;
a
b
c
a
b
c
a
b
// dataflow
assign z = sel ? a : b;
1
0
sel
a
sel
b
02/14/05
L05 Synthesis 6
sum[0]
sum[1]
sum[2]
sum[3]
full
adder
full
adder
full
adder
full
adder
x[0] y[0]
x[1] y[1]
x[2] y[2]
x[3] y[3]
cout
As a default + is implemented as
a ripple carry editor
02/14/05
L05 Synthesis 7
module parity(in,p);
parameter WIDTH = 2;
// default width is 2
input [WIDTH-1 : 0] in;
output p;
// simple approach: assign p = ^in;
reg p;
integer i;
parity
reg parity = 0;
word[2]
for (i = 0; i < WIDTH; i = i + 1)
parity = parity ^ in[i];
p <= parity;
word[1]
word[0]
end
endmodule
XOR with 0 input has
been optimized away
02/14/05
L05 Synthesis 8
reg q;
d
// D-latch
always @(g or d) begin
if (g) q <= d;
end
// D-register
always @(posedge clk) begin
q <= d;
end
6.884 - Spring 2005
02/14/05
clk
L05 Synthesis 9
reg q;
// register with synchronous clear
d
always @(posedge clk) begin
reset
if (!reset) // reset is active low
q <= 0;
clk
else
q <= d;
end
reg q;
// register with asynchronous clear
always @(posedge clk or negedge reset)
begin
if (!reset) // reset is active low
q <= 0;
else
// implicit posedge clk
q <= d;
end
// warning! async inputs are dangerous!
// theres a race between them and the
// rising edge of clk.
6.884 - Spring 2005
02/14/05
clk
reset
L05 Synthesis 10
Technology-independent* optimizations
02/14/05
L05 Synthesis 11
02/14/05
L05 Synthesis 12
3-terms:
8, 9,10,11
10,11,14,15
10--[D]
1-1-[E]
Y
0
0
1
0
0
1
1
1
1
0, 8
5, 7
7,15
8, 9
8,10
9,11
10,11
10,14
11,15
14,15
label
0
5
7
8
9
10
11
14
15
-000[A]
01-1[B]
-111[C]
10010-0
10-1
1011-10
1-11
111-
1-terms:
X
0
1
1
0
0
0
0
1
1
0-terms:
W
0
0
0
1
1
1
1
1
1
Z
0
1
1
0
1
0
1
0
1
none!
02/14/05
L05 Synthesis 13
0000
0101
0111
1000
1001
1010
1011
1110
1111
A
X
.
.
X
.
.
.
.
.
B
.
X
X
.
.
.
.
.
.
C
.
.
X
.
.
.
.
.
X
D
.
.
.
X
X
X
X
.
.
E
.
.
.
.
.
X
X
X
X
A is essential
B is essential
D is essential
E is essential
02/14/05
L05 Synthesis 14
Dominated Columns
Some functions may not have essential primes (Fig. 1), so make
arbitrary selection of first prime in cover, say A (Fig. 2). A
column U of a prime term table dominates V if U contains every
row contained in V. Delete the dominated columns (Fig. 3).
1. Prime table
0000
0001
0101
0111
1000
1010
1110
1111
A
X
X
.
.
.
.
.
.
B
.
X
X
.
.
.
.
.
C
.
.
X
X
.
.
.
.
E
.
.
.
.
.
.
X
X
F
.
.
.
.
.
X
X
.
G
.
.
.
.
X
X
.
.
H
X
.
.
.
X
.
.
.
0101
0111
1000
1010
1110
1111
B
X
.
.
.
.
.
C
X
X
.
.
.
.
D
.
X
.
.
.
X
E
.
.
.
.
X
X
F
.
.
.
X
X
.
G
.
.
X
X
.
.
H
.
.
X
.
.
.
CC dominates
dominates B,
B,
GG dominates
H
dominates H
0101
0111
1000
1010
1110
1111
C
X
X
.
.
.
.
D
.
X
.
.
.
X
E
.
.
.
.
X
X
F
.
.
.
X
X
.
G
. C is essential
.
X G is essential
X
.
.
Selecting
Selecting CC and
and GG
shows
shows that
that only
only EE isis
needed
needed to
to complete
complete
the
cover
the cover
02/14/05
L05 Synthesis 15
functions.
time.
02/14/05
L05 Synthesis 16
02/14/05
L05 Synthesis 17
Mapping Example
Example due to
Kurt Keutzer
6.884 - Spring 2005
02/14/05
L05 Synthesis 18
DAG Covering
02/14/05
L05 Synthesis 19
8
13
13
10
11
6.884 - Spring 2005
02/14/05
L05 Synthesis 20
Possible Covers
02/14/05
L05 Synthesis 21
Complexity:
Complexity:
To
To determine
determine the
the optimal
optimal cover
cover for
for
aa tree
tree we
we only
only need
need to
to consider
consider aa
best-cost
best-cost match
match at
at the
the root
root of
of the
the
tree
tree (constant
(constant time
time in
in the
the number
number
of
of matched
matched cells),
cells), plus
plus the
the optimal
optimal
cover
cover for
for the
the subtrees
subtrees starting
starting at
at
each
each input
input to
to the
the match
match (constant
(constant
time
time in
in the
the fanin
fanin of
of each
each match)
match)
O(N)
O(N)
6.884 - Spring 2005
P
Best cover for
this match uses
best covers for
P & Z
02/14/05
L05 Synthesis 22
02/14/05
L05 Synthesis 23
Example (II)
02/14/05
L05 Synthesis 24
Example (III)
02/14/05
L05 Synthesis 25
Technology-dependent optimizations
Logic Synthesis
Gate
netlist
HDL logic
map to target library
optimize speed, area
Mask
02/14/05
L05 Synthesis 26