VLSI Testing and

Testability
Fault Modeling

Outline
Vocabulary: defects, errors and faults
Functional vs. structural testing

Fault models
Single stuck-at fault

Fault equivalence
equivalence collapsing

Fault dominance
Additional fault models
Exercise Problems

Defects, errors and faults

Defect unintended difference between the implemented hardware

and its intended design
hardware, physical level

Error wrong output signal produced by a defective system

Fault representation of a defect at the abstracted function level
functional level

VDD

Two-input NAND gate

A
C

Defect:
B

T2

Fault: stuck-at logic 0

Error:

T1

short to ground

if A=1 and B=1 then C=1

correct output is C=0

fault model a collection of identical electrical behaviors caused by

various defects are gathered into a model that is used for simulation
of large systems

Fault models
Real defects (and the variations thereof) are too numerous and
diverse, and still may differ in small respects, however preventing
possible thorough analysis
Bridge the gap between a physical cause and a functional effect
cause in the analog domain manifestation in the digital domain

Testing can not address any sort of defect, a subset of target fault
must be derived. The testing algorithms will target to detecting this
subset
generation and evaluation of test vectors

Fault models are independent of technology

Fault models levels

increasing level of abstraction

layout level

geometric information
accurately reflects reality, but too complex

transistor level

circuit description
modeled for analog circuit testing; transistors, R, L, C faults
feasible for small circuits

register-transfer
level

structural description (netlist of gates)

stuck-at faults are the most popular models at this level
bridging faults, delay faults also apply at this level

behavioral level

behavioral description
faults at this level no longer have obvious correlation with
manufacturing defects

across levels

do not fit into any of the previous level

e.g. quiescent current (IDDQ)

Examples of defects in chips

bridged or missing metal

contamination by particles
missing contact window
oxide breakdown
over etching, or incomplete etching
mechanical damage, or scratches
defective mask
defective photoresist
incomplete removal of photoresist
cracks, crystal imperfections
defective connection on the bonding pads
etc.

Scaling and complexity testing issue

Our testing problem can be devised as depicted

we know the functionality, the topology (netlist)

we suspect some defects may disrupt correct circuit operation
but
we can only access inputs (primary inputs) and outputs (primary
outputs), i.e. no internal node

Functional vs. structural testing

Functional test of a 10-input AND gate would demand testing for all
input patterns, i.e. 210
1
0
1
0
1
0
1
0
1
0

what can be concluded out of this test ?

Gate under test is

an AND
not a NAND
not an OR
not a NOR

test is and AND, and not any of the others. The number of Boolean
functions that can be generated with a 10-input gate equals 21024

Functional vs. structural testing (2)

1
0
1
0
1
0
1
0
1
0

Functional test of a 10-input AND gate would demand testing for all input
patterns, i.e. 210

These are the only valid conclusions that may be

taken, since the output violates the truth table of
NAND and OR

what can be concluded out of this test ?

Gate under test is

an AND
not a NAND
not an OR
not a NOR

The full functional test must allow to conclude that the gate under test is
and AND, and not any of the others. The number of Boolean functions that
can be generated with a 10-input gate equals 21024
The full functional test of the M6800 8-bit microprocessor (1975, 2MHz, 75 instructions, 7000
transistors) was estimated to take about
two million years !

Functional vs. Structural Testing (3)

Structural test do not focus on the fonction implemented by a
circuit, but on its structure
gates
interconnects
netlist

Function A
out
Function B
in1
in2

out

A basic assumption is that the design is correct

The focus on the structure, makes it possible to develop algorithms
that are independent of the design. These algorithms are based on
fault models. Several will be presented in this course.

Single stuck-at fault

Single stuck-at-value (value=0, or value=1), represents a single
line which is permanently tied to 0 or 1, i.e. GND or VDD
most commonly applied fault model
two possible faults may occur on a line, namely stuck-at-0 and stuckat-1
representations:
s-a-0, s-a-1
a0, a1 line a s-a-0, s-a-1 respectively
SA0, SA1

Properties of single stuck-at fault

Only one line is faulty
The logic state of a primary input, primary output or internal gate input
or output is permanently stuck to logic 1 or logic 0

Single stuck-at fault (2)

example: following Boolean circuit has 9 fault sites ( ) and 18
single stuck-at faults
test
vector

0
1

1
g
e

s-a-0
z

0 (1)
f

1 (0)

notice that the stem (b) and fanout branches (e and f) of a net are
considered independently

Single stuck-at fault model applied in

a NAND gate
VDD

preliminary remark: in the rest of this class, we will apply stuck-at models one abstraction level
higher, i.e. RTL or gate-level

A
Z
B

We can observe the following:

controlling value some values which are present at one gate input determine
on their own the output value; e.g. A=0 is a cont

an input vector can detect a specific set of faults rolling value

sensitized path some values which are present at one gate input, e.g. B, let the
value of the other input, e.g. A propagate to the output; if a fault is present
stucking A, than it can be detected with an appropriate input vector; the path is
sensitized to the fault
the minimum set of vectors needed to test the circuit is smaller then the
exaustive number of input vectors

Single stuck-at fault model applied in

a NAND gate
VDD

A
Z
B

We can observe the following:

controlling value some values which are present at one gate input determine
on their own the output value; e.g. A=0 is a controlling value
an input vector can detect a specific set of faults
sensitized path some values which are present at one gate input, e.g. B, let the
value of the other input, e.g. A propagate to the output; if a fault is present
stucking A, than it can be detected with an appropriate input vector; the path is
sensitized to the fault
the minimum set of vectors needed to test the circuit is smaller then the
exaustive number of input vectors

Single stuck-at fault model applied in

a NAND gate
VDD

1
Z

We can observe the following:

controlling value some values which are present at one gate input determine
on their own the output value; e.g. A=0 is a controlling value
an input test vector can detect a specific set of faults
sensitized path some values which are present at one gate input, e.g. B, let the
value of the other input, e.g. A propagate to the output; if a fault is present
stucking A, than it can be detected with an appropriate input vector; the path is
sensitized to the fault
the minimum set of vectors needed to test the circuit is smaller then the
exaustive number of input vectors

Single stuck-at fault model applied in

a NAND gate

s-a-0

We can observe the following:

controlling value some values which are present at one gate input determine
on their own the output value; e.g. A=0 is a controlling value
an input test vector can detect a specific set of faults
sensitized path some values which are present at one gate input, e.g. A, let the
value of the other input, e.g. B propagate to the output; if a fault is present
stucking B, than it can be activated with an appropriate input vector, and
propagate to the output; the path is sensitized to the fault
the minimum set of vectors needed to test the circuit is smaller then the
exaustive number of input vectors

Single stuck-at fault model applied in

a NAND gate
VDD

A
Z
B

We can observe the following:

controlling value some values which are present at one gate input determine
on their own the output value; e.g. A=0 is a controlling value
an input test vector can detect a specific set of faults
sensitized path some values which are present at one gate input, e.g. A, let the
value of the other input, e.g. B propagate to the output; if a fault is present
stucking B, than it can be activated with an appropriate input vector, and
propagate to the output; the path is sensitized to the fault
the minimum set of vectors needed to test the circuit is smaller then the
exhaustive number of input test vectors

Single stuck-at fault: fault detection

Fault detection requires:
a test t that activates fault f
the error that has been activated must propagate to an observation point, a
primary output or a latch where it is memorized
in order to propagate to an observation point, all off-path gate inputs must be
set to non-controlling values

0
0

G1

True response
Faulty response

e
0
G3

Only vector 11 will

activate the fault:
10, 01, 00 will not.

1
1

f
G2

1 (0)

1 (0)

s-a-0

A circuit with n lines can have at most 2n single-stuck-at faults

this circuit has 7 lines, and can be affected by 14 single-stuck-at faults

Fault equivalence (1)

The number of fault sites in a Boolean circuit is given as:
#PI + #gates + # (fanout branches)

PI: primary inputs

#: number of

This number can grow to a significantly large value; as we will see in

a later lecture, test vectors need to be found for every fault
reducing the number of faults would be beneficial

Fault equivalence Two faults f1 and f2 are equivalent if all tests that
detect f1 also detect f2

Fault equivalence (2)

Considering an n-bit input, single output, fault-free circuit which performs

f0 (V), where V is an n-bit input Boolean vector
In the presence of two individual faults 1 and 2, the circuit output function
changes to f1 (V) and f2 (V) respectively

i.e. V activates fault 1 and fault 2

The two faulty functions are indistinguishable iff the faults have the same
set of tests:

f
(
VfV
)

()0

1
2

: XOR

for all 2n V vectors

Fault equivalence: analysis of NAND

a
b

sa0 sa1
sa0 sa1

NAND gate has k+1 s-a-0 faulty inputs

and output
sa0 sa1

Each s-a-0 transforms the NAND gate

output to a constant 1 value, regardless
of the input test vector

Thus, A0, B0 and Z1 are equivalent

Equivalence rules

Fault collapsing
All faults in a circuit are partitioned into disjoint equivalence sets. All
faults in an equivalence set are equivalent
Selecting one fault in each equivalence set is called fault collapsing
equivalent
collapsed set

equivalence set
fault

fault collapsing

The set of selected faults is known as equivalence collapsed set

Equivalence fault collapsing

procedure

Circuit must be levelized, i.e. the level to which each gate is

participating must be defined, which should guarantee that every
gate inputs are defined before the gate output is processed

all the gates belonging to one layer are processed at a time

Equivalence collapsing rules are applied to each gate
A Boolean gate has several faults located at its inputs and output
only one of the faults determined to be equivalent is kept
a fault located at the output of the gate is kept, if it is determined to be
equivalent to faults located at any input of the gate

s
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t
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f
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e
r
a
t
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=
s
e
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f
a
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l
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a
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l
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s

Fault collapsing example

equivalence
collapsing layer 1:

sa1 sa0

equivalence
collapsing layer 3:

sa1 sa0

equivalence
collapsing layer 2:

sa0
sa1

sa1 sa0
e
sa1
sa0

sa0 sa1
c

g
z
h

sa1 sa0

f
sa1 sa0

sa1 sa0

1
0
1
8

collapse ratio = =
0
.5
5
5

Fault dominance
If all tests of fault F1 detect another fault F2, then F2 is said to
dominate F1
All tests of F2

F1
s-a-1

001

F2
s-a-1

110

010
000

101

All tests of F1 (single)

also detects F2

011
100

F2 dominates F1

Dominance fault collapsing:

if fault F2 dominates fault F1, then F2 can be removed from the list
in the example shown above, F2 s-a-1 is removed from the output
t is sufficient to consider only the input faults of Boolean gates

If two faults dominate each other then they are equivalent

Fault dominance: analysis of NAND

list of vectors that detect A0 = {11}

list of vectors that detect B0 = {11}
list of vectors that detect Z1 = {11}

A0, B0, Z1 are equivalent

list of vectors that detect A1 = {01}

list of vectors that detect B1 = {10}

Z0dominates A1, and B1
list of vectors that detect Z0 = {00, 01, 10}
a
b

sa0 sa1
z
sa1

Fault dominance collapsing

procedure
the number of single stuck-at faults to be modeled for a Boolean gate is equal
to n+1, I.e. number of inputs plus one
the algorithm proceeds from output through the netlist to the inputs
1. receipt for collapsing the faults of a gate by dominance
1. remove all faults from output
2. for all inputs, keep one type: s-a-1 for AND and NAND, s-a-0 for OR and
NOR
3. to any one of the inputs add one fault of the other type (s-a-0 for AND,
NAND, s-a-1 for OR, NOR)
1. NOT, buffer, wire: remove output faults, keep both fault types on input
2. no collapsing is possible for fanout
Dominance fault collapsing in a 3-input AND gate

s-a-1
s-a-1
s-a-1 s-a-0

Checkpoints

Primary inputs and fanout branches of a combinational circuit are called

checkpoints

Checkpoint theorem: A test set that detects all single (multiple) stuck-at
faults on all checkpoints of a combinational circuit, also detects all single
(multiple) stuck-at faults in that circuit
a

g
e

Total fault sites = 9

z

f
c

Checkpoints ( ) = 5
h

Thus dominance fault collapsing reduces to:

only input faults are kept in the case of fanout-free circuit
in the case of circuit with fanout, checkpoints are also included
further reduction by equivalence collapsing is possible

Dominance fault collapsing example

(1)
equivalence
dominance
dominance
collapsing layer 1:

sa1 sa0

collapsing layer 3:

sa1 sa0

collapsing layer 2:

sa0
sa1

sa1 sa0
e
sa1
sa0

sa0 sa1
c

g
z
h

f
sa1 sa0

sa1 sa0

sa1 sa0

Dominance fault collapsing example

(2)
dominance
dominance
dominance
collapsing layer 1:

sa1 sa0

collapsing layer 3:

sa1 sa0

collapsing layer 2:

sa0
sa1

sa1 sa0
e
sa1
sa0

sa0 sa1
c

g
z
h

sa1 sa0

f
sa1 sa0

sa1 sa0

9
=0
.5
1
8

collapse ratio =

Checkpoints

Primary inputs and fanout branches of a combinational circuit are called

checkpoints

Checkpoint theorem: A test set that detects all single (multiple) stuck-at
faults on all checkpoints of a combinational circuit, also detects all single
(multiple) stuck-at faults in that circuit
a

g
e

Total fault sites = 9

z

f
c

Checkpoints ( ) = 5
h

Thus dominance fault collapsing reduces to:

only input faults are kept in the case of fanout-free circuit
in the case of circuit with fanout, checkpoints are also included
further reduction by equivalence collapsing is possible

Multiple stuck-at faults

Multiple stuck-at fault many faults may occur simultaneously in a
circuit, thus multiple combinations of the lines being stuck-at logic 1
or logic 0 are possible

Are usually not considered in practice, because

the number of multiple stuck-at faults becomes huge, even for a
reasonably small circuit, and thus impractical to simulate. The number
of multiple stuck-at faults in a circuit with n single fault sites is 3n-1,
which is too large a number even for circuits of moderate size.
tests for single stuck-at faults usually cover more than 99% of multiple
stuck-at faults

so, why bother ?

Multiple stuck-at faults (2)

Multiple stuck-at faults may cause problems when considered in
combination
s-a-1
F2
A
B

s-a-1
s-a-1
F1

Z=AB
F3

Y=A+B

redundant faults
do not propagate
to the output

vector 11 detects
multiple stuck-at
faults

all other individual single

stuck-at faults are
detected by vectors 00,
01 and 10

multiple stuck-at faults

(F2, F3) and (F1, F2, F3)
are detected by vector
11, which is not in the
initial vector list, thus
remain undetected

Multiple stuck-at faults (3)

functional masking introduced by multiple stuck-at faults prevents
the detection of single stuck-at faults
s-a-1
A 0

1 (0)
1

B 1

1 s-a-0
0 (1)

the only test that detects C s-a-0 is 011

however, A s-a-1 will mask it

Transistor-level faults
The MOS transistor is considered to operate as an ideal switch,
which may be perturbed in its correct operation by two types of
faults:
Stuck-open: one single transistor is permanently stuck in the open state,
where is can not conduct any current
Stuck-short: one single transistor is permanently shorted irrespective of its
gate voltage, and thus can not be set into a non current-conducting state

The detection of a stuck-open fault requires two vectors to be

applied to the circuit
The detection of a stuck-short fault requires the measurement of
the circuit quiescent current (IDDQ)

Stuck-open example
Stuck-open: transistor cannot be placed into current conducting state
Vector 1, time = t:
initialization vector
VDD

Vector 2 (test for T3 stuck-open)

T4

T3

vector 2
time=t+1

vector 1
time=t

Z
B
T2

T1

Two-vector stuck-open test

can be constructed by
ordering two stuck-at tests

Stuck-short example
Stuck-short: impossible to turn transistor out of current conducting state;
thus, in some configurations of the input, a short is created,
which should not be the case in CMOS

Vector 1: turnT1 and T2 on

VDD

T4

IDDQ path in
faulty circuit

T3
Z

vector 1
time=t

B
T2

T1

Bridging faults
A bridging fault represents a short between a group of signals

In case a feedback path is created by the bridging fault, a memory

effect may result, i.e. a combinational circuit may be converted into
a sequential circuit

Model of a bridging fault: 1-dominant

A+C
A
B
C

D
E
A+C

Redundancy and untestable faults

Redundant fault any fault that does not modify the input-output function
of the circuit is called redundant fault

Untestable fault
a fault for which no test can be found is called an
untestable fault; redundant faults are untestable faults
A
B

s-a-1

AB

Reconvergent fanout structure

Identification and removal of redundant faults is complex

A

AB

B
The circuit after removing the redundant fault

Redundancy is not always undesirable

Practice Problems (1)

Problem 1: Implement a full adder using AND, OR and NOT gates,
and determine the total number of
(i) single stuck-at faults, (ii) multiple stuck-at faults.
Problem 2. Generate a minimum set of test vectors to detect all
single stuck-at faults for an n-bit parity checker implemented as a
cascade of (n-1) exclusive-OR gates. Repeat the exercise where
each exclusive-OR gate is implemented by elementary logic
gates (AND, OR, NAND, NOR, NOT

Practice Problems (2)

Problem 3. For a 2-input CMOS NAND circuit:
a. Find a two-pattern test for each single-transistor stuck-open fault.
b. Rearrange the eight vectors in a compact set, and show that this set
can be constructed from the single stuck-at faults tests for the
NAND gate.
c. For each stuck-at fault of the NAND gate, find an equivalent
transistor (stuck-open, stuck-short or combination) fault.

Problem 4. Find the minimum number of test vectors required to

test for all single stuck-at faults in thefollowing circuits:
a. A 289-input exclusive-OR gate
b. A 76-input exclusive-OR gate
c. A 12-input exclusive-NOR gate
d. A 75-input exclusive-NOR gate
e. An 8-input NAND gate
f. A 6-input OR gate
g. A full adder implemented using AND, OR and NOT gates

Practice Problems (3)

Problem 5: Using functional fault modelling, determine the test sets
for the following:
a. A 8-line-to-1-line multiplexer
b. A 3-to-8 decoder

Problem 6: Consider the following circuit.

Determine the fault equivalences among the three faults, H s-a-0, J

s-a-0, and K s-a-0. That is, are these three faults equivalent? If
not, is any pair of these three faults equivalent? Prove your
answer.

Practice Problems (3)

Problem 5: Using functional fault modelling, determine the test sets
for the following:
a. A 8-line-to-1-line multiplexer
b. A 3-to-8 decoder

Problem 6: Consider the following circuit.

Determine the fault equivalences among the three faults, H s-a-0, J

s-a-0, and K s-a-0. That is, are these three faults equivalent? If
not, is any pair of these three faults equivalent? Prove your
answer.

Practice Problems (4)

Problem 7: Equivalent fault collapsing has been applied to the
following circuit and collapsed faults are indicated with an X.
Apply dominance fault collapsing and list the faults that remain!

Practice Problems (5)

Problem 8: For the circuit below:
a. What is the number of all potential fault sites?
b. Derive the equivalence collapsed fault list. What is the collapse
ratio?
c. Derive the dominance collapsed fault list (on top of the
equivalence). What is the collapse ratio?

Practice Problems (4)

Problem 5: Equivalent fault collapsing has been applied to the
following circuit and collapsed faults are indicated with an X.
Apply dominance fault collapsing and list the faults that remain!

Practice Problems (4)

Problem 5: Equivalent fault collapsing has been applied to the
following circuit and collapsed faults are indicated with an X.
Apply dominance fault collapsing and list the faults that remain!

Additional readings and references

M. L. Bushnel and W. D. Agrawal, Essential of Electronic Testing for

Digital, Memory, and Mixed Signal VLSI Circuits, Springer, 2005