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=32'h0000_0001
for the Same register for lower lane register it reset value getting 0x0000_0000
as per the EDS reset value should be 32'h0200_0001
pcie_Dwell_Timer offset(0x04) :
For all lanes(0-16) reset values should be same where lower lanes(0-7) its reset
values
behave differently always showing 0x0000_0000 where expecting 32'h0000-00064
sas_Dwell_Timer offset(0x08)
For all lanes(0-16) reset values should be same where lower lanes(0-7) its reset
values
behave differently always showing 0x0000_0000 where expecting 32'h0000-00064
Protocol Control Common reg :
Protocol control Refclk swtich count register offset(0x2c) :
When num_chan_sas_16 & num_chan_pcie_16 , upper and lower protocol control commo
n register are aCtive
when i check the reset values of protocol control low for refclk switch count re
gister(0x2c) 0x0000_0000 as per
rtl its 0x0000_0100
Hi Chris
During Ral testing when NUM_CHAN_SAS_16 & NUM_CHAN_PCIE_16 Most of the lowe lane
s are not working
properly due to multiple driver issue ,
Below Assign Satatment APB_PRDATA_int[160:32] 160th bit always driving x which i
s not using
This make Lower lane register driving always x not reading writing register
Snippet code Path: guinness/rtl/TopWrappers/TrimodeSerdes.v (Line number 607)
// PSEL[4:0] are all used by Sbus bridge, so replicated its response to lanes[4:
1] so APB read mux can find it.
assign APB_PRData_int[160:32] = {4{APB_PRData_int[31:0]}};
resoultion :
assign APB_PRData_int[159:32] = {4{APB_PRData_int[31:0]}};
Locally i tried with updated its working
Wave snap shot :