Gigabit Ethernet,

10 Gigabit Ethernet
Metro Ethernet

Agenda

Introduction
Ethernet Technology
10/100 Ethernet
1/10 Gigabit Ethernet
Gigabit Ethernet Technology & 10 Gigabit Ethernet Technology

Metro Ethernet
Consortium
Competing Technologies
Products / Equipment
Ethernet Block Diagrams
Xilinx Solutions for 1/10 GbE Products
Summary

10 Gigabit Ethernet

What is Ethernet?
Developed by Xerox in cooperation with
in 1976
Ethernet specification is the basis for the
IEEE 802.3 standard

DEC & Intel

Specifies the layer 1 (physical) and layer 2 (data-link) of the OSI reference
model
Ethernet uses a bus or star topology

Simple, very high speed, low cost

Scalable data rates: 10/100 Mbps, 1/10 Gbps
Low-cost technology will always win: VHS vs. Betamax

10 Gigabit Ethernet

Ethernet History
1970s - ALOHA
1973 - Robert Metclafes
research at Xerox
2.94 Mbps, CSMA/CD

1976 - Star Computer defined

a 10 Mbps version
1979 - DIX Consortium
DEC - Transceivers
Intel - Controller chips
Xerox - Ethernet

1980-83: Standards Path

From DIX to 802.3

10 Gigabit Ethernet

1980 - Ethernet - DIX v1.0

1982 - Ethernet - DIX v2.0
1983 - IEEE 802.3 Standard
Approved
1995 - IEEE 802.3u - 100
Mbps
1998 - IEEE 802.3z 1000
Mbps
2002* - IEEE 802.3ae 10
Gbps

Ethernet Dominance
Ethernet won the LAN wars: default layer 2 protocol

Quality standards - interoperable products

Several manufacturers with competing standards
Lower costs with aggressive chip development
Evolved with the market needs - features, performance
Ethernet has displaced Token Ring, VGAnyLAN, FDDI, ATM

Power of installed base

Estimated 250 million Ethernet interfaces
> 95% of Internet traffic is transported over Ethernet

Ethernet is moving beyond the enterprise to WAN, MAN, SAN,

home and access technologies (Long-Reach Ethernet/Ethernet in
the First Mile)

10 Gigabit Ethernet

Shifting the Decimal Point Ethernet Migration

10 Mb/s to 100 Mb/s
Shrink the collision domain
Only two repeaters

100 Mb/s to 1000 Mb/s

Extend carrier to allow meaningful collision domain
Only one repeater

1 Gb/s to 10 Gb/s
Make 10 GbE full duplex only, no collision domain

10 Gigabit Ethernet

Ethernet Economics

10 Gigabit Ethernet

Ethernet
Technology
Basics and Framing

Ethernet Basics
Defines layers 1 and 2 specifications
Physical layer (layer 1)
Provides the electrical, mechanical & procedural specs for the
transmission of bits through a communication link, medium or
channel
Data link layer (layer 2)
Ensures error control & synchronization between two entities
Includes Medium Access Control (MAC) & Logical Link Control
(LLC) sub-layers

10 Gigabit Ethernet

PHY Layer Functions

Circuit establishment and release

Bit synchronization
Service data unit
Data transfer sequencing - serialization & latency
Fault condition notification
Network management
Medium specific control functions
Electrical signals, light pulses, frequencies,
Wire destinations, connector types,
Signal strengths, timings, latency, distances,

10 Gigabit Ethernet

10

Analog
Digital

10/100 Ethernet PHY

Manchester
Encode

Transmitter

Scrambler

4B/5B

M
I
I

Chip

10 Mb/s TX
Filter

125 MHz

5B/4B

Descrambler

25 MHz

TX
Freq Synch

Baseline
Restore

Clk
Recovery
Manchester
Decoder

10 Gigabit Ethernet

11

20 MHz
Adoptive
Equalization

10Clk
Recovery

Link Polarity

Auto
Negotiation

Board

Data Link Layer Functions

Data link connection
establishment and release
Service data units
Framing
Data transfer
Frame synchronization
Frame sequencing

10 Gigabit Ethernet

12

Error detection
Identification & parameter
exchange
Flow control
Physical layer services
Network management

Ethernet MAC
Provides all functions necessary to attach an Ethernet physical
layer to the host interface
Any physical layer chip that supports
MII standard can attach to the 10/100 MAC
GMII standard can attach to the 1 GbE MAC
XGMII standard can attach to the 10 GbE MAC
Processor
Host Interface
Statistic
Generator

FIFO
10/100 MAC
Ethernet PHY

10 Gigabit Ethernet

13

Ethernet MAC
Ethernet MAC
Tx Data Flow

Tx
Buffer

Transmit
MAC
Handler
Management
Register
Counter

Rx
Buffer

Rx Data Flow

Media
Independent
Interface
Receive
MAC
Handler

Address
Match
Serial
Interface

10 Gigabit Ethernet

14

PHY

MAC Types
There are 2 MAC protocols defined for Ethernet
Half-Duplex, Full-Duplex

Half-Duplex is the traditional form of Ethernet

Refers to data transmission in one direction at a time
Uses CSMA/CD protocol
Assumes that all the "normal" rules of Ethernet are in effect on
the local network

Full-Duplex bypasses the CSMA/CD protocol

Full-duplex mode allows two stations to simultaneously
exchange data over a point to point link that provides
independent transmit and receive paths
10 Gigabit Ethernet

15

CSMA/CD (Half-Duplex)
Carrier Sense Multiple Access w/ Collision Detect
The network is monitored for presence of a transmitting
station (carrier sense)
Transmission is deferred if an active carrier is detected
Station continues to monitor the network until carrier ceases

If an active carrier is not detected, and the period of no

carrier is equal to or greater than the interframe gap, then
the station immediately begins transmission of the frame

10 Gigabit Ethernet

16

CSMA/CD - Collisions
While the transmitting station is sending the frame, it monitors the
medium for a collision
If a collision is detected, the transmitting station stops sending the
frame data & sends a 32-bit jam sequence
Jam sequence is transmitted to ensure that the length of the collision is
sufficient to be noticed by other transmitting stations
After sending the jam sequence the transmitting station waits a random
period of time - called "back-off

If repeated collisions occur, then transmission is repeated

But the random delay is increased with each attempt
Process repeats until station transmits frame without collision

Once a station successfully transmits a frame, it clears the collision

counter used to increase the back-off time after repeated collisions
10 Gigabit Ethernet

17

CSMA/CD Flow
Station is ready
to send
New Attempt

Wait according to
Backoff Strategy

Sense Channel
Channel Busy
Channel Free

Transmit data &

sense channel

Collision Detected

No Collision Detected

Transmit Complete

10 Gigabit Ethernet

18

Transmit Jam
Signal

Variations of CSMA Protocol

(Half-Duplex)
1-persistent CSMA
When a station has frames to
transmit, it first listens to the
channel, if the channel is idle,
the frame is sent
If the channel is busy, the station
waits & transmit its frame as
soon as the channel is idle
If a collision occurs, the stations
waits a random interval and
starts over again
Station transmits with a
probability of 1 whenever it finds
the channel idle
10 Gigabit Ethernet

19

Non-persistent CSMA
When the channel is busy, the
station simply gives up and tries
at a later time

P-persistent CSMA
When the channel is busy, the
station will keep listening until
the channel becomes idle (like
1- persistent)
Then the station transmits the
frame with a probability of p
The station backs off with the
probability of q = 1 - p

Slot Time (Half-Duplex)

The "slot time" is a key parameter for half-duplex Ethernet
network operation
Defined as 512 bit times for Ethernet operating at 10/100
Mbps, and 4096 bit times for 1 Gbps
The 512 bit slot time establishes the minimum size of an
Ethernet frame as 64-bytes
The 4096 bit slot time establishes the minimum size of a Gigabit
Ethernet frame as 512-bytes

The minimum transmission time for a complete frame

must be at least one slot time
10 Gigabit Ethernet

20

Slot Time (Half-Duplex)

Slot time establishes a limit on size of a network in terms
of the maximum cable segment lengths & number of
repeaters that can be in a path
If the size of a network grows too big, a phenomenon known as
"late collisions" can occur
Late collisions are considered a failure in the network

The slot time ensures that if a collision is going to occur, it

will be detected within the first 512 bits (4096 for GbE) of
the frame transmission

10 Gigabit Ethernet

21

Full-Duplex (FD) MAC Types

Based on the IEEE 802.3x standard, FD MAC type
bypasses the CSMA/CD protocol
FD mode allows two stations to simultaneously exchange
data over a point to point link
Aggregate throughput of the link is effectively doubled
FD 100 Mb/s station provides 200 Mb/s of bandwidth

FD operation is restricted to point to point links connecting

exactly two stations
Used in 1/10 Gb E only
10 Gigabit Ethernet

22

Ethernet (IEEE802.3) Frames

62 bits

Preamble - A series of alternating 1's and 0's used by the

Ethernet receiver to acquire bit synchronization.

2 bits

Start Of Frame Delimiter - Two consecutive 1 bits used to acquire

byte alignment.

6 bytes

Destination Ethernet Address - Address of the intended receiver.

The broadcast address is all 1's.

6 bytes

Source Ethernet Address -The unique Ethernet address of

the sending station.

2 bytes

Length or Type field - For IEEE 802.3 this is the number of bytes
of data. For Ethernet I&II this is the type of packet.

46 to
1500
bytes

Data - Short packets must be padded to 46 bytes.

Frame Check Sequence - The FCS is a 32 bit CRC calculated
using the AUTODIN II polynomial.

4 bytes

10 Gigabit Ethernet

23

Ethernet (802.3) Frames

Preamble
A sequences of 64 bits used for synchronization
Give components in the network time to detect the presence of a signal
Begin reading the signal before the frame data arrives

Destination & Source MAC Addresses

The Destination MAC Address field identifies the station or stations that are to receive the
frame
The Source MAC Address identifies the station that originated the frame

Length/Type
If the value of this field is less than or equal to 1500, then the Length/Type field indicates
the number of bytes in the subsequent MAC Client Data field
If the value of this field is greater than or equal to 1536, then the Length/Type field
indicates the nature of the MAC client protocol (protocol type)

MAC Client Data

Contains the data transferred from the source station to the destination station or stations
If the size < 46 bytes, then use of the subsequent "Pad" field is necessary to bring the
frame size up to the minimum length

10 Gigabit Ethernet

24

Ethernet (802.3) Frames

Pad
If necessary, extra data bytes are appended in this field to bring the frame length up to its
minimum size

Frame Check Sequence

Contains a 4-byte CRC value used for error checking
Source station performs CRC when assembling a MAC frame from the Destination MAC Address
through the Pad fields
Destination station performs CRC when receiving a frame

Interframe Gap (IFG)

A minimum idle period between transmission of Ethernet frames
Provides a brief recovery time between frames to allow devices to prepare for
reception of the next frame
The minimum interframe gap is 96 bit times
= 9.6 microseconds for 10 Mb/s Ethernet
= 960 nanoseconds for 100 Mb/s Ethernet
= 96 nanoseconds for 1 Gb/s Ethernet
= 9.6 nanoseconds for 10 Gb/s Ethernet
10 Gigabit Ethernet

25

Ethernet Frame Format Extensions

Extension Field
Added to the end of the Ethernet frame to ensure it would be long enough for
collisions to propagate to all stations in the network
The extension field is appended as needed to bring the minimum length of the
transmission up to 512 bytes
It is required only in half-duplex mode, as the collision protocol is not used in fullduplex mode

Frame Bursting
Allows a station to transmit a series of frames without relinquishing control of the
transmission medium
Burst mode applies to half-duplex mode only
Improves the performance of GbE when transmitting short frames

10 Gigabit Ethernet

26

Ethernet Frame Format Extensions

Jumbo Frames
Increase the maximum size of the MAC Client Data field from 1500-bytes to
9000-bytes
Larger frames would provide a more efficient use of the network bandwidth while
reducing the number of frames that have to be processed

VLAN Tagging
Frame format extensions to support Virtual Local Area Network (VLAN)
Tagging
The VLAN protocol permits insertion of an identifier, or "tag", into the Ethernet
frame format
VLAN Tagging provides various benefits
Easing network administration
Allowing formation of work groups
Enhancing network security
The 4-byte VLAN tag is inserted between the Source MAC Address field
and the Length/Type field
10 Gigabit Ethernet

27

VLAN Concept

Source: Intel
10 Gigabit Ethernet

28

VLAN Frame
802.1Q
Start
Tag Control Length
Destination Source
Tag
Preamble Frame
Information Type
Address Address
Type
Delimiter
7-bytes

1-bytes

6-bytes

6-bytes

2-bytes

2-bytes

2-bytes

MAC
Client
Data

Padding

FCS

0-n bytes

0-p bytes

4 bytes

1st 2 bytes - 802.1Q Tag Type which is set to 0x8100

replaces the normal Length/Type Field

Next 2 bytes
User Priority Field (3 bits) - indicates frame priority level
Canonical Format Indicator (1 bit) - indicates presence of a Routing
Information Field
VLAN Identifier (12 bits) - the VID uniquely identifies the VLAN to which the
Ethernet frame belongs
10 Gigabit Ethernet

29

VLAN Protocol (802.1q)

802.3ac standard defines the frame format extension to
support VLAN tagging on Ethernet networks
New max frame became 1522 instead of 1518 (+ 4 bytes)

802.1q standard defines the VLAN protocol

Allows insertion of a 4-byte identifier, or tag, into the Ethernet
frame format to identify the VLAN to which the frame belongs

10 Gigabit Ethernet

30

8B/10B Coding Technique

Invented by IBM - for low cost implementations - Ethernet
Simplifies the requirements on bandwidth & clock jitter for devices
Has an excellent DC balance property with a maximum run-length of 5 and a
good transition density

Input/output bit rate of 8/10 improves transmission reliability

Built-in special characters for commands, synchronization, and delineation

Drawback
25% overhead and less bandwidth efficiency
Line rate of 12.5 Gbps is needed to implement a transmission rate of 10
Gbps with 8b/10b
For a serial implementation this is a significant disadvantage because
currently there are a large number of devices that support 10 Gbps, but very
few that support 12.5 Gbps

10 Gigabit Ethernet

31

Scrambled Encoding
SONET/WAN applications
Allows a lower line rate for extended reach
Virtually has no overhead & better efficiency

Simple - can be done in hardware

Drawbacks
Maximum run-length is non-deterministic, has no guarantee of DC balance,
and no built-in special characters
Cost of the devices with this encoding scheme is typically higher

Makes using this technique less attractive for a LAN

unless extended reach is needed
8B/10B encoding most likely will be used in LAN/MAN while
scrambled encoding will likely be specified in the WAN
10 Gigabit Ethernet

32

10/100 Ethernet

10/100 Ethernet MAC

Provides

All functions necessary to connect to the host bus

Both bus master and slave functions
Host buffer chaining capability for higher system performance
Internal FIFO management necessary for efficient bus utilization
MAC is on the lower half of the data link layer which deals with
getting the data on and off the wire

Half-duplex - based on CSMA/CD protocol

10 Gigabit Ethernet

34

10/100 Ethernet Interfaces

MII - Media Independent Interface
Standard specification for the interface between the network controller chips
& associated media interface chips
MII automatically senses 10 and 100 Mbps Ethernet speeds

AUI - Attachment Unit Interface

802.3 interface between the MAU and the NIC
Also refers to the rear panel port to which an AUI cable might attach

MAU - Media Attachment/Access Unit

Provides interface between AUI port of station & common medium of
Ethernet
Can be built into the station or be a separate device
Performs PHY layer functions including conversion of digital data from
Ethernet interface, collision detection, injection of bits onto the network

10 Gigabit Ethernet

35

1/10 GbE
Faster, Cheaper, Simpler

GbE & 10 GbE - Still Ethernet

An IEEE 802.3 standards project
Evolution from a 10 Mbps shared coaxial connection to a
dedicated 10 Gbps optical connection

Ethernet ubiquity leads to rapid development & adoption

Leverages features of its Ethernet predecessors
No change to Ethernet frames
Support Ethernet enhancements (e.g., link aggregation)
Specify implementation interfaces to enable interoperability
Minimizes user learning curve and support costs
Same management architecture
Compatibility with familiar tools
10 Gigabit Ethernet

37

Gigabit Ethernet - Summary

IEEE 802.3z
1000 Mbps
802.3 Ethernet frame format

Support star-wired topologies

Support fiber & copper
At least 2 km over SMF
At least 500 m over MMF
At least 25 m over copper

Preserves minimum and

maximum frame size of 802.3

Full & half-duplex operation

Meets all 802 requirements
except Hamming distance
Bytes

Collision domain diameter of

200m
Accommodate 802.3x flow
control

Preamble

Destination
Address

Source
Address

Length of
Data Field

0 - 1500
Protocol Header, Data, and Pad

IEEE 802.3 Frame Format

10 Gigabit Ethernet

38

Customer Challenges
Enterprise
Multiple locations in one metro area
Need to support high-bandwidth applications: imaging,
CAD/CAM, storage

Service Providers
Need high-speed connections between POPs
Need flexible bandwidth, just-in-time provisioning

Metro/MANs
Very low cost
Emergence of metro Ethernet services
10 Gigabit Ethernet

39

1/10 GbE Vision

End-to-End Ethernet
Backbone - Coast-to-Coast, Continent-to-Continent
Fiber, 10Gbps and up
Metro - City-to-City, Town-to-Town
1Gbps migrating to 10Gbps
Access - Last/First Mile - Ethernet to the home
56Kbps migrating to 1Gbps
LAN - Desktop-to-Desktop, Floor-to-Floor
10/100 Mbps migrating to 1Gbps

Integrated Services (Voice/Video/Data)

10 Gigabit Ethernet

40

1 GbE Applications
Ideal backbone interconnect technology for use between
10/100 Base-T LAN switches
High-performance servers & high-end desktop PCs
Data centers

10 Gigabit Ethernet

41

10 GbE Applications
Local Area Networks

High-speed campus backbone

Server farms (& back-up)
Data centers
Remove LAN bottlenecks
Eliminate 1 Gbps link aggregation
issues
ERP applications
Enterprise switches
Edge routers
Test Equipment

Wide Area Networks

Inter/Intra PoP connections
Distance learning

10 Gigabit Ethernet

42

Storage Area Networks

Database servers
Technical/scientific/medical
imaging/supercomputing
High-resolution streaming media
Local & remote data mirroring
Centralized back-up
Storage service providers

Metro Area Networks

Private/shared access networks
Inter-campus connectivity
Video-on-demand, broadcast
video, video conferencing
Telephony, Telemedicine

10 GbE Applications

10 Gigabit Ethernet

43

The Vision: End-to-End

Ethernet

Courtesy: Octavio Morales, World Wide Packets

10 Gigabit Ethernet

44

10-GbE in the WAN

Courtesy: Paul Botorff, Nortel networks

10 Gigabit Ethernet

45

10GbE in the WAN

http://www.cisco.com/warp/public/cc/techno/lnty/etty/ggetty/tech/10gig_wp.htm

10 Gigabit Ethernet

46

10GbE in the MAN

http://www.cisco.com/warp/public/cc/techno/lnty/etty/ggetty/tech/10gig_wp.htm

10 Gigabit Ethernet

47

DataCenter Network
Gigabit and 10-Gigabit Ethernet

Courtesy: B. Tolley/3Com; Nan Chen/Nortel

10 Gigabit Ethernet

48

ISP/NSP Network
Gigabit and 10-Gigabit Ethernet

Courtesy: B. Tolley/3Com; Nan Chen/Nortel

10 Gigabit Ethernet

49

10-GbE in SANs

Courtesy: Arnie Thompson, Network Appliance

10 Gigabit Ethernet

50

Ethernet-based SANs

Courtesy: Arnie Thompson, Network Appliance

10 Gigabit Ethernet

51

Significant Market Impact

10 GbE market will reach $3.6 billion in 2004
10 GbE revenue in WAN/MAN will grow to 2500% to $1.8 billion in 2003
10 GbE LAN will start significant penetration in 2003

10-Gb Ethernet Applications

Communications equipment

Edge switches and terabit routers packet-based line

cards
Bridge/ Layer2 switch
Router/ Layer3 switch

Storage equipment - iSCSI line cards

Test equipment
PL4 to XGMII bridge
10 Gigabit Ethernet

52

Capacity Convergence

Courtesy: Paul Botorff, Nortel networks

10 Gigabit Ethernet

53

Gigabit Ethernet
Technology

Gigabit Ethernet OSI model

10 Gigabit Ethernet

55

Open Systems Interconnect

(OSI) Reference Model

Software Layers

7. Application

Example Protocols

6. Presentation

TELNET, HTTP, SMTP

File transfer, mail, API's

5. Session

IETF

Hardware Layers
IEEE802

10 Gigabit Ethernet

56

4. Transport

UDP/TCP, SNMP
Error Control, Endto End transmission,
retransmission.

3. Network

IP
ARP, routing

2. LLC

Multiplexing/Demultiplexing

2. Data Link

Gig Ethernet MAC

1. Physical

Gig Ethernet PCS/PMA

Framing, error detection, Link flow control

Line Drivers/Receivers, encoder/decoders, timing
1000BASE-LX

Building a 1000Base-X
Ethernet System
UDP,IP
TCP/IP
v4
PPC

User
Logic

Bus Management
FIFO,Flow Control
OPB

Bus

Management

FIFO

Frame Generation, stats

gathering, flow control

Generic

MAC

GMII

Line Coding,
Auto-Neg,
Sync,
8B/10B
PCS

TBI

10

Serdes,
Clk-rec,
cml/pecl

P
M
A

Gen

16
OSI Layer 3 & 4

OSI Layer 2

OSI Layer 1

( Network/Transport Layer)

(Data Link Layer)

(Physical Layer)

Software

Hardware

Hardware

10 Gigabit Ethernet

57

Transceiver

P
M
D

MDI

Fiber/Copper
LX/SX/CX

Building a 1000Base-X
Ethernet system
UDP,IP
TCP/IP
PPC

User
Logic

Bus Management
FIFO,Flow Control

OPB

Bus

Management

FIFO

Gen

16

10 Gigabit Ethernet

58

Frame Generation, Stats gathering, Flow Control,

Line Coding, Auto-Neg, Syncronization, 8B/10B,
Disparity checks, Serdes Gen and Clock Recovery.

Generic

MAC/PCS/PMA

Transceiver

P
M
D

MDI

Fiber/Copper
LX/SX/CX

Applications/Target Market
Xilinx
Xilinx
Xilinx

Xilinx
Xilinx

10 Gigabit Ethernet

59

Applications/Target Market
Xilinx

Connecting 100 Mbps workgroup to Gigabit Ethernet

10 Gigabit Ethernet

60

I0 Gigabit Ethernet
Technology

What is 10 GbE?
Next step in Ethernet data rate

Preserves Ethernet frame format

Compatible with previous generations
Increases performance range to 1000:1
10x the performance at 3 to 4x the cost of 1 GbE

The technology to continue deployment of Ethernet into

MAN/WAN environments
Low cost MAN/WAN technology

Uses only full-duplex transmission for MAC

10 Gigabit Ethernet

62

GbE vs. 10 GbE

Gigabit Ethernet (802.3z)

Copper & Optical Fiber media only

Half (CSMA/CD) & Full Duplex only
Carrier extension & frame burst
8b/10b coding scheme
Leverage Fibre Channel PMDs
Up to 5 km distance

10 Gigabit Ethernet

63

10 Gigabit Ethernet (802.3ae)

Optical Fiber media only

Full Duplex only
Throttle MAC speed
New coding scheme (64b/66b)
New optical PMDs
Up to 40 km distance
Direct attachment to
SONET/SDH gear

Whats Different at 10 Gbps?

Full-duplex only (no CSMA/CD)
Previous speeds also defined half-duplex

Fiber optic media only (no copper cable options)

All previous speeds included copper media
Multi mode fiber bandwidth limits distance
Multiple PMD choices for single mode fiber

WAN PHY (SONET-friendly)

WAN interface sub-layer defined for compatibility with SONET OC-192 maps to OC-192 frames
Rate adaptation to SONET payload capacity

New line code (64b/66b)

New Ethernet MAN/WAN capability

10 Gigabit Ethernet

64

10 GbE Layer Diagram

Source: 10 Gigabit Ethernet Alliance

10 Gigabit Ethernet

65

10 GbE Components
PHY standards
A LAN PHY operating at a data rate of 10.3125 Gbps
A WAN PHY operating at a data rate of 9.95328 Gbps
Compatible with OC-192c/SDH VC-4-64c payload rates

Optical transceivers - PMD interfaces

MAC

10 Gigabit Ethernet

66

10 GbE LAN PHY

LAN operates at 10.3125 Gbps data rates
Uses simple encoding mechanisms to transmit data on
dark fiber and dark wavelengths

10 Gigabit Ethernet

67

10 GbE WAN PHY

Operates at 9.95328 Gbps
data rates
Seamless compatibility with
SONET OC-192c/SDH STM-64
DWDM/TDM

Asynchronous service
preserved
Enables low cost access to
SONET optical infrastructure

10 Gigabit Ethernet

68

Accomplished by addition of
SONET/SDH sublayer
Implemented as an optional sub-layer
that maps encoded data stream of
the LAN PHY into the payload
envelope of a SONET frame

Supports SONET/SDH overhead

fields & fault processing

Why WAN PHY?

It is SONET friendly
Enables using SONET infrastructure for layer-1 transport
SONET ADMs, DWDM transponders, optical regenerators
Require some SONET features
OC-192 link speed, SONET framing, minimal path/section/line overhead
processing

But it isnt SONET compliant

Connects to SONET access devices, but not directly into SONET
infrastructure
Avoids more costly aspects of SONET
No TDM support (concatenated OC-192c only)
Does not require meeting SONET grid laser specifications, jitter
requirements, stratum clocking
Minimal OAM&P
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69

10 GbE WAN PHY

Encapsulation
Ethernet packets in SONET frames
A WAN PHY operating at a data rate compatible with the payload rate of OC192c/SDH VC-4-64c
Define a mechanism to adapt the MAC/PLS data rate to the data rate of the
WAN PHY

10 Gigabit Ethernet

70

10 GbE WAN-PHY Seamless

Attachment

Courtesy: Paul Botorff, Nortel Networks

10 Gigabit Ethernet

71

10 GbE Components - PMD

PMD objectives are PHY independent
The 3 serial (850nm, 1310nm, 1550nm) PMDs support both the
LAN & WAN PHY
There is no relationship between the link distance and the LAN
or WAN PHY

Optical transceivers - PMD interfaces

850nm Serial, MMF, 65M

1310nm WWDM, MMF (300M), SMF (10km)
1310nm Serial, SMF 10km
1550nm Serial, SMF 40km

10 Gigabit Ethernet

72

PMD Options

Courtesy: Bob Grow, Intel

10 Gigabit Ethernet

73

Ethernet LAN Architecture

Courtesy: Bob Grow, Intel

10 Gigabit Ethernet

74

Understanding the
Terminology

Courtesy: Jonathan Thatcher, World Wide Packets

10 Gigabit Ethernet

75

10 GbE PHY Architectures

XAUI
Serial LAN

Serial WAN

WWDM LAN

MAC

MAC

MAC

XGXS

PCS
64b/66b

PMA
Serial

WIS

XGXS

XGXS

PCS
64b/66b

XGXS

PCS
8b/10b

PMA
WWDM

PMD
WWDM

XGXS

MAC - Media Access Control

PCS - Physical Coding Sub-layer
PHY - Physical Layer Device
PMA - Physical Media Attachment
PMD - Physical Media Dependent
WWDM - Wide Wave Division Multiplexing
WIS - WAN Interface Sub-layer
XAUI - 10 Gigabit Ethernet Attachment Unit Interface
XGMII - 10 Gigabit Media Independent Interface
XGXS - XGMII Extender Sub-layer
XSBI - 10 Gigabit Sixteen-Bit Interface

10 Gigabit Ethernet

76

PMD
Serial

PMA
Serial

PMD
Serial

10GbE Sub-layers (1)

XGXS: XGMII Extender Sub-layer

Extend physical chip-to-chip interconnect to 20

4 x 3.125 Gb/s XAUI
8b/10b encode, 10b/8b decode
Lane-by-lane synchronization (Compensates for clock disparity
between lanes)
Loop back mode for system test

PCS: Physical Coding Sub-layer

Improve transition density and framing
64b/66b encode, 66b/64b decode
Scrambler & de-scrambler
10 Gigabit Ethernet

77

10GbE Sub-layers (2)

PMA: Physical Media Attachment

Serialize and deserialize to 10 Gbps

16:1 SERDES
Clock synthesis
Low output jitter
CDR - clock and data recovery

PMD - Optics: Physical Media Dependent

O/E and E/O conversion
Optical transmitter and receiver

10 Gigabit Ethernet

78

10 GbE Interfaces (1)

XGMII
MAC

XAUI
XGXS

XSBI
XGXS

PCS

PMA

PMD

XGMII (10G Media Independent I/F)

156.25 Mbps, DDR (3 maximum distance)
74 pins: Tx/Rx (32 data, 4 control, 1 clock)
4 Byte-wide lanes with 1 control bit per lane

XSBI (10G Sixteen-Bit I/F)

Based on OIF SFI-4 interface
644.53 Mbps, LVDS
34 pins: Tx/Rx (16 data (differential signals), 1 clock)
10 Gigabit Ethernet

79

Fiber
Optics

10 GbE Interfaces (2)

XAUI (10G Attachment Unit I/F)
AUI - Borrowed from the Ethernet Attachment Unit Interface, X - represents
the Roman Numeral tem for 10 Gbps
Interface extender - Extends XGMII reach (3 vs. 20 maximum distance)
4 differential lanes @ 3.125 Gbps
Employs 8b/10b EMI-reduced transmission encoding
XAUI reduces the 74 pin XGMII to 16 pins Tx / Rx (4 lanes, differential/serial)
A path for cost reduction of system products
Enables pluggable optical transceivers
Enables lower IC costs (i.e., pins = cost)
Longer trace lengths enable higher density ICs (e.g., multiple MACs) and greater
flexibility in board layout

XAUI is identical to Infiniband & 10 Gigabit Fibre Channel

10 Gigabit Ethernet

80

10 GbE MAC
MAC - Unchanged from GbE
MAC data rate of 10.000 Gb/s
Serial PHY: 10.3 GBaud (64b/66b code)
Parallel PHY: 4 X 3.125 GBaud (8b/10b code)
Performs rate control for WAN PHY
Not used for LAN PHY types
Full duplex standard only

Maintains 802.3 frame format and size

New rate adaptation capability
Extend inter-frame gap

10 Gigabit Ethernet

81

MAC
MAC pacing matches the MAC/PLS data rate to the WAN
PHY data rate
The MAC transmits a longer Inter-Packet Gap between packets
when the WAN PHY is used
The number of the bytes added to each IPG is proportional to
the length of the previous packet
These extra bytes of IPG are removed during 64B/66B encoding
to effectively reduce the data rate

10 Gigabit Ethernet

82

10 GbE Benefits
Brings Ethernet high
volume/low cost cost model to
10 Gbps networks
Scales network backbones in
enterprise core and in SP
Internet data centers
Leverages 250 million
Ethernet ports installed base
Supports all IP services
Data, packetized voice & video

Provides advanced
management capabilities
10 Gigabit Ethernet

83

Logical path forward to aid in

the design of future proofed
networks
Aggregates 1 GbE (1000BaseX, 1000Base-T)
Enable end-to-end networking
Integration of LAN, MAN & WAN
into one seamless network

Compatibility with SONET/

SDH OC-192 installed base
Leverages existing OC192c/SDH-64 core Internet rates
for faster time-to-market

Metro Ethernet
10 GbE in the Metropolitan Area
Networks

MAN Dynamics
Extremely heavy traffic between campuses
Large campuses have several thousand users per site
Inter-LAN traffic often reaches multi-gigabit range today
This traffic will continue to grow

Interconnecting campus LANs on a single, shared, highcapacity MAN ring can seamlessly link all sites on a VPN
under a common Ethernet protocol
No translations required between sites
Very high traffic concentration between ring nodes

10 Gigabit Ethernet

85

What is Metro Ethernet?

A Metro Ethernet Network (MEN) offers Ethernet access
and Ethernet based services across a MAN
Some service providers have introduced a MEN-like
technology for the Wide Area Network (WAN)

10 Gigabit Ethernet

86

Ethernet in the Metro

Packet traffic is becoming the dominant traffic type in networks worldwide

Rapid growth in sites demanding high speed access and flexible services
Ethernet is a mature, predictable, & well understood data networking technology
Significantly lowers total cost of ownership, which benefits carriers & their
customers

10 Gigabit Ethernet

87

Advantages of 10 GbE
in the Metro
LAN and WAN-compatibility
Provides opportunity to implement dependable IP VPN services

Secure, reliable, scalable applications

Implementation of a single management infrastructure that can be
scaled to meet the anticipated customer base size
Facilitating customer control of effective security policies and
applications
Reduced latency with guaranteed SLAs (service-level agreements)
Reliable & less expensive alternative to private/leased line
communication networks

10 Gigabit Ethernet

88

Metro Ethernet Transport

10 Gigabit Ethernet

89

Lowering the Cost

of the Network
Reducing unnecessary layers
of equipment significantly
Lowers equipment cost
Lowers operational cost
Lowers complexity
Simplifies architecture

10 Gigabit Ethernet

90

Consortium
10 Gigabit Ethernet Alliance
Metro Ethernet Forum

10GEA - 10 Gigabit
Ethernet Alliance
100+ Members - Xilinx is a Participating Member
Mission
Promote industry awareness, acceptance, and advancement of
technology and products based on the emerging 10 Gigabit
Ethernet standard
Accelerate industry adoption by driving technical consensus and
providing technical contributions to the IEEE 802.3ae Task
Force
Provide resources to establish and demonstrate multi-vendor
interoperability of 10 Gigabit Ethernet products

10 Gigabit Ethernet

92

MEF - Metro Ethernet Forum

Non-profit organization dedicated to accelerating the
adoption of optical Ethernet as the technology of choice in
metro networks worldwide
Comprised of 67 members as of January 2002
Leading service providers, major incumbent local exchange
carriers, top network equipment vendors

Mission - Accelerate adoption of optical Ethernet as the

technology of choice in metro networks worldwide

10 Gigabit Ethernet

93

MEF - Key Objectives

Build consensus and unite service providers, equipment
vendors, end customers on optical Ethernet
Facilitate implementation of optical Ethernet standards to
allow delivery of Ethernet services and make Ethernetbased metro transport networks carrier class
Enhance worldwide awareness of the benefits of optical
Ethernet services and Ethernet-based metro transport
networks
Enable Ethernet applications and services, building on the
physical transport specified by e.g. 10GEA
10 Gigabit Ethernet

94

Competition

High-Speed Network for

Data, Voice and Multimedia

10 Gigabit Ethernet

96

Equipment

Interconnection Devices
Repeater: PHY device that restores data and collision
signals: a digital amplifier
Hub: Multi-port repeater + fault detection
Bridge: Data link layer device connecting two or more
collision domains. MAC multicasts are propagated
throughout extended LAN
Router: Network layer device. IP, IPX, AppleTalk. Does
not propagate MAC multicasts
Switch: Multi-port bridge with parallel paths
10 Gigabit Ethernet

98

What is a Repeater?
Repeaters are low-level devices that amplify or regenerate
weak signals
Repeaters are needed to provide current to drive long
cables
Repeaters are used to join network segments together to
increase the total length of the network
Act at the physical layer and allow all traffic to cross LAN
segments

10 Gigabit Ethernet

99

What is a Hub?
A place of convergence where data arrives from one or
more directions and is forwarded out in one or more other
directions
Hub is a repeater with fault detection functionality
Connects high-performance stations/devices to Ethernet
LAN and provides high-performance inter-LAN
connectivity using switching technology
A hub usually includes a switch of some kind

10 Gigabit Ethernet

100

What is a Bridge?
Connect a LAN to another LAN that uses the same
protocol (e.g., Ethernet or Token Ring)
Works at the data-link level of a network, copying a data
frame from one network to the next network along the
communications path
Bridges can make minor changes to the frame before
forwarding it (such as adding and deleting some fields
from the frame header)

10 Gigabit Ethernet

101

What is a Switch?
Network device that selects a path or circuit for sending a
unit of data to its next destination
Switch is a simpler & is faster than a router
Simultaneous switching of packets between its ports increases the
aggregate LAN bandwidth dramatically

Network device processing packets at layer 2 & 3

Layer 2 Switch:
Filters & forwards at the data link layer of the OSI model
Uses MAC address to determine where frames are sent
Layer 3 Switch:
Routes packets at wire speed using Layer 3 information
10 Gigabit Ethernet

102

What is a Router?
Determines next network point to which a packet should
be forwarded on the way to its final destination
Routers use the network layer information within each packet to
route it from one destination/LAN to another
Must recognize all the different layer 3 protocols that are used on
the networks it is linking together
Routers communicate with one another to determine the best
route through the complex connections of many LANs to
increase speed and cut down on network traffic

10 Gigabit Ethernet

103

What is a NIC?
NIC - Network Interface Card
NIC is an expansion card used to connect a PC, server, or
workstation to a LAN
NIC provides an interface between the network and the
PCs bus
Most NICs are designed for a particular type of network,
protocol, and media
The NIC segments outgoing messages into packet
formats specified by the LAN protocol for transmission
10 Gigabit Ethernet

104

Ethernet Block
Diagrams

Core Router
1/10GbE Line Card
Control Plane
Processor

Optics

PHY

Backplane / Switch Fabric Card

Memory

10GbE
MAC

Network
Co-Processor (s)
NPU /
ASIC

Switch
Fabric

Backplane
I/F

Backplane
I/F

Memory
xN
Central Management Board

OC-48 / OC-192 POS/ATM Line Card

Control Plane
Processor

Optics

PHY

Memory

Framer /
Mapper

Network
Co-Processor (s)
NPU /
ASIC

10GbE
Mgr.

Backplane
I/F

10 Gigabit Ethernet

106

ATM
Mgr.

SDRAM / SRAM / FLASH

CPU
xN

SONET
Mgr.

System Bus

Buffer
Mgr.

I/O
Mgr.

Edge Router
OC-12 / OC-3 POS or ATM
Optics

Backplane / Switch Fabric Card

Framer
Mapper

PHY

Backplane
I/F

Switch
Fabric

Backplane
I/F
10 / 100 / 1000 Ethernet Linecard
PHY

10/100/Gig
MAC

Memory

Backplane
I/F

Central Management Board

T/E Linecard
TE

T/E
Framer

TX / RX

Backplane
I/F

I/O Mgr.

SONET
Mgr.

ATM
Mgr.

SDRAM / SRAM / FLASH

DSL Linecard
xDSL
TX / RX

HDLC
Controller

Backplane
I/F

CPU
System Bus

10 Gigabit Ethernet

107

Buffer
Mgr.

I/O
Mgr.

Enterprise Router
RJ-45

10/100
PHY

Memory
I/F

10/100
MAC

DMA
Controller

CPU

RJ-45

LAN
Side

802.11a/b
Radio

10/100
PHY

UART

10/100
MAC

802.11a/b
Baseband
Controller

T/E Framer

T/E
TX/RX

HDLC

xDSL
TX / RX

ATM SAR

ATM OC-3
PHY

UTOPIA
PCI Bus (32/33 or 64/66) or
Proprietary Bus

10 Gigabit Ethernet

108

SDRAM
Flash /
SRAM
I/F Driver

WAN
Side
(to CO)

RS232

SOHO Router
802.11a/b
Baseband
Controller

802.11a/b
Radio

RJ-45

LAN
Side

10/100
PHY

10/100
MAC

MII

Memory
I/F
CPU

DMA
Controller
UART

AFE

UTP

Flash /
SRAM
I/F Driver

RS232

Home
PNA

USB
Transceiver

IEEE 1394 /Firewire

USB
Device
Controller

T/E Framer

T/E
TX/RX

HDLC

xDSL
TX / RX

QAM Decoder
& FEC

RS-232

PCI Bus (32/33 or 64/66) or

Proprietary Bus

10 Gigabit Ethernet

SDRAM

109

Cable

T1/E1
DSL

Clock Generator
& DLLs

WAN
Side
(to CO)

GbE Switch
Magnetics

GbE
PHY

GbE
MAC

Magnetics

GbE
PHY

GbE
MAC

Packet
Memory
Address
Cache
Switch
Fabric
ASSP

Network
Management
CPU
Memory
I/F

Magnetics

10 Gigabit Ethernet

110

GbE
PHY

GbE
MAC

Memory

10 GbE Router Line Card

Control
Plane
Processor

System Bus

Memory
Memory
Memory
Controller
Controller

10 GbE

Integ.
Optics

P
M
A

P
C
S

10GbE
MAC

XAUI XGMII

Classification
Engine

NPU
or
ASIC

Security
Proc.

Traffic
Queue
Mgr.

Scheduler

BP
SER /
DES

BP
Optics

Parallel
Parallel
I/F
I/F

System
Clock
Other Line Card,
Switch Fabric, or
Network Mgmt. Card

10 Gigabit Ethernet

111

GigE Router Line Card

Control
Plane
Processor

System Bus

Memory
Memory
Memory
Controller
Controller

GbE
MAC

PHY

Magnetics

GMII

NPU or
ASIC

Backplane
SERDES
SERDES

Serial I/F
Driver
Receiver

Parallel
Parallel
I/F
I/F

System
Clock
Other Line Card,
Switch Fabric, or
Network Mgmt. Card

10 Gigabit Ethernet

112

10/100 Ethernet Router

Line Card
Control
Plane
Processor

System Bus

Memory
Memory
Memory
Controller
Controller

10/100
MAC

PHY

Magnetics

MII

NPU or
ASIC

Backplane
SERDES
SERDES

Serial I/F
Driver
Receiver

Parallel
Parallel
I/F
I/F

System
Clock
Other Line Card,
Switch Fabric, or
Network Mgmt. Card

10 Gigabit Ethernet

113

Xilinx Solutions for

1/10 Gigabit Ethernet
Virtex-II Pro SystemIO + 1/10
GbE MAC

Virtex-II Series Expanded to

Include Virtex-II Pro

Virtex-II Logic, Routing, Features

Upward compatible, same design tools
Embedded Multipliers, SelectIO-Ultra (with
840Mbps LVDS), DCI/XCITE, DCM

Up to 16, 3.125 Gbps serial transceivers

Channel bonding, 8b/10b encoding
Supports high-speed interfaces GbE,
10GbE (XAUI), PCI/PCI-X, Infiniband,
RapidIO, HyperTransport, FlexBus 3/4,
POS-PHY 3/4

Up to four IBM 405 PowerPC

32-bit RISC CPU: 420 DMIPS @ 300 MHz
The leading embedded CPU architecture in
telecom & networking infrastructure
IBM CoreConnect on-chip bus

Virtex-II Pro and IP Solutions will Further Enable Next

Generation Networking and Telecom Products
10 Gigabit Ethernet

115

Virtex-II Pro Features

50 :
50 :

BRAM
18 Bit
36 Bit
Impedance
Controller

18 Bit

Embedded DSP
functionality - up to
500 Billion MAC/s
CLK0
CLK90
CLK180
CLK2X
RST
CLK270
CLK2X180
DSSEN
CLKDV
PSINCDEC
CLKFX180
PSEN
CLKFX
STATUS[7:0]
PSCLK
LOCKED
PSDONE

Embedded Dual-Port RAM for Data Buffering

4000

CLKIN
CLKFB

clock signal
control signal

10 Gigabit Ethernet

Virtex

4000XL

3500

Delay (ps)

3000
2500
2000

Virtex-II

1500
1000

500
0
0

Digital Clock
Management (DCM) Precise Clock
Generation
116

XCITE Digitally-Controlled
Impedance (DCI) for
simpler PCB layout

200

400

600

800

1000

LUTs Reached

Active Interconnect
Technology with a 300 MHz
System Clock

SelectIO
25 IO types including
840 Mbps LVDS

Virtex-II Pro Family

10 Gigabit Ethernet

117

Virtex-II Pro RocketIO

Technology
Transceiver Module
8B/10B
TXDATA

Encode

FIFO

Serializer

TX
+
TX-

Transmit
Buffer

Transmitter

31.1 MHz
156.3 MHz

REFCLK
Comma Detect
and Word
Alignment

RXDATA

20X Multiplier

Receiver
RX Clock Generator

Elastic

8B / 10B

Buffer

Decode

Deserializer

Up to sixteen multi-gigabit serial transceivers

Support 622 Mbps to 3.125 Gbps
Most complete feature set
10 Gigabit Ethernet

118

Loopback

TX Clock Generator

Receive
Buffer

RX+
RX-

Physical Media Attachment

(PMA)
Programmable features
Transceiver Module
8B/10B
TXDATA

Encode

FIFO

Serializer

TX+
TX-

Transmit
Buffer

42 MHz
156.3 MHz

RXDATA

Transmitter
20X Multiplier

REFCLK

Receiver

Comma Detect
and Word
Alignment

RX Clock Generator

Elastic

8B / 10B

Buffer

Decode

10 Gigabit Ethernet

Loopback

TX Clock Generator

119

Deserializer

Receive
Buffer

RX+
RX-

300 mV to 800 mV output

50 ohm or 75 ohm on-chip
termination
4 levels of pre-emphasis to
support up to 20 of FR-4
pc-board trace
Comma detect

Supports AC or DC coupling
Local loop-back capability

Physical Coding Sublayer

(PCS)
Transceiver Module
8B/10B
TXDATA

Encode

FIFO

Serializer

TX+
TX-

Transmit
Buffer

42 MHz
156.3 MHz

RXDATA

Transmitter
20X Multiplier

REFCLK

Receiver

Comma Detect
and Word
Alignment

Loopback

TX Clock Generator

RX Clock Generator

Elastic

8B / 10B

Buffer

Decode

Deserializer

Receive
Buffer

RX+
RX-

8B/10B line coding logic

Transmit FIFO for clock
synchronization
Receive Elastic Buffer
for channel bonding
Flexible FPGA interface
1, 2, and 4 byte

All of the above can be optionally bypassed

10 Gigabit Ethernet

120

Virtex-II Pro Helps You Manage the

Transition from Parallel to Serial I/Fs
IOB

SelectI/O-Ultra
technology for parallel
interfaces

Input
Reg DDR mux

OCK1

Reg

ICK1

Reg
OCK2

3-State

Reg

ICK2

Reg DDR mux

OCK1

Reg
OCK2

32b @
78 MHz

Rocket I/O Multi-Gigabit Serial

Transceivers
Up to Sixteen 3.125 Gbps transceivers

10 Gigabit Ethernet

121

Output

DDR
FF

Gb Serial
Gb Serial
Transceiver Transceiver
32b @
78 MHz

PAD

25 I/O Standards
XCITE Technology
840 Mbps LVDS
Dedicated DDR
Registers

P
N
IOB

Helps preserve investment in legacy designs

Eases transition from parallel to serial technology
Parallel interface designs will not go away

Complete GE MAC Offerings

First in programmable industry to provide complete
Gigabit Ethernet (GE) MAC solutions
1-GE MAC with GMII interface
10-GE MAC with XGMII interface

Part of the comprehensive Platform FPGA SystemIO

solution for emerging system connectivity standards

10 Gigabit Ethernet

122

1-Gb Ethernet
MAC Core

1-GE MAC Technical Details

- Facts & Features
1 GIG ETHERNET FACTS.
Core Specifics
Supported Family
Virtex,Virtex-II,
Spartan2e, Virtex2Pro
Performance
125MHz
Global Clock Buffers

Virtex II Slice Count

Runs on Software Ver.

~471min
~1777max
MGT, SRL16, DCM
Dist & Block RAM
4.1I (E.35)

I/O connections

200

Special Features

10 Gigabit Ethernet

124

1 GIG ETHERNET FEATURES

Static optional modes
PCS/PMA: Full Duplex/1000Base-X only.
GMII: Full/Half Duplex/1000Base-X or T.
Statistics: 41counters based on the IETF
EtherStats -- RFC2819.
Host
Dist_mem vs Block mem
Family
Dynamic Configuration register:
VLAN
Flow Control: Pause (asymmetrically or
symetrically enabled)
Jumbo frames: 9K
Half duplex or Full Duplex
CRC: In-band or MAC generated
Host CLK: programmable.
IFG: Sets IFG stretch capability (test equipment)

FPGA LOGIC
MAC

GT_Ethernet_1 (MGT)
PCS
Physical Coding Sublayer

Tx

TX

PAUSE

RX

Frame

Tx

Gen

k-codes
&
Disp.

Client

Flow

I/F

Control

Txdata[7:0]

FIFO

Txcharisk
8B / 10B
Txchardispmode
Encode
Txchardispval

Frame
checks

HOST

Config

10 Gigabit Ethernet

Stats MDIO

125

Rx
Sync

MDIO

Transmit
Buffer

Transmitter
20X Multiplier

62.5 MHz (REF CLK)

Neg.
Rx

Serializer

TX+
TX-

TX Clock Generator

Txbuferr

Auto

Physical Media attachment

Conexant IP

Loop-back

gtx_clk
(125MHz)

Technical Details- MAC with PCS/PMA Block

Diagram (V-II Pro Only)

Receiver
RX Clock Recovery

Rxdata[7:0]
Rxcharisk
Rxnotintable
Rxdisperr
Rxbufstatus(1)
Rxchariscomma

8B / 10B

Deserializer

Decode

Comma Det.

Receive
Buffer

RX+
RX-

Elastic
Buffer
SIGNAL_DETECT

1-Gb Ethernet MAC w/ GMII

Single-speed half- and/or full-duplex 1-Gigabit Ethernet Media
Access Controller (GMAC)
Fully compliant with IEEE 802.3-2000 standard

Supports Virtex-II (-4), Virtex-E (-7) and Spartan-IIE (-7) FPGAs

8b Gigabit Media Independent Interface (GMII) running 125MHz for 1Gbps
bandwidth
Can interface to industry standard ASSP PHY chips
8b internal data path and back-end interface, 125MHz operation

10 Gigabit Ethernet

126

Additional GMAC Features

Optional support for VLAN frames
Virtual LAN allows network administrators to reduce the time it
takes to implement moves, adds, and changes

Optional support for JUMBO frames (9k max)

Powerful statistics gathering
Allows remote network administration

Configured and monitored through an independent microneutral interface

Optional flow control through MAC Control pause frames
Integrated MDIO port for management of PHY layers
10 Gigabit Ethernet

127

1-Gb Ethernet MAC IP Core

Back-End
Interface

GMAC CORE
GMII

GMAC Internal CORE

8

TX Data
TX Valid

Transmit
Engine

8
TX
I/O

Pause Req
Pause Value 16
RX Data
RX Valid

Flow
Control

Deference
COL
CRS

and Backoff
Receive
Engine

8
RX
I/O

Management I/F

Statistics
and Configuration

Compliant IEEE 802.3-2000

10 Gigabit Ethernet

128

TXD[7:0]
TX_ER
TX_EN
TX_CLK

RXD[7:0]
RX_DV
RX_ER
RX_CLK

Gigabit Ethernet
Applications
Communications Equipment
GbE Network Interface Cards (NICs)
PCI-, PCI-X- and Cardbus-based
Edge switches and terabit routers packet-based line cards

Storage Equipment
iSCSI line cards

Numerous bridge opportunities

PL3 to Gb Ethernet

10 Gigabit Ethernet

129

10-Gb Ethernet
MAC Core

10-Gb Ethernet MAC IP Core

Back-End
Interface

XGMAC CORE
XGMII

XGMAC Internal CORE

TX Data
TX Ctrl

64
Transmit
Engine

Pause Req
Pause Value 16
RX Data
RX Ctrl

64

Management I/F

64
TX
I/O

TXD[31:0]
TXC[3:0]
TX_CLK

Flow
Control
Receive
Engine
Statistics
& Configuration

64
RX
I/O

RXD[31:0]
RXC[3:0]
RX_CLK

Designed to IEEE 802.3ae Draft D3.2

10 Gigabit Ethernet

131

10GE MAC
Technical Details
10 GIGABIT ETHERNET MAC FACTS
Core Specifics
Supported Family
Virtex-II (-5)

XC2V1000-XC2V8000
Performance

10 Gigabit Ethernet

Global Clock Buffers

Virtex-II Slice Count

32b XGMII interface 312.5Mbps per

HSTL Class 1 drivers
64b internal data path and back-end
interface, 156.25MHz SDR operation
3
3629 slices

Special Features
Runs on Software Ver.

Integrate digital clock management

4.1i

I/O connections

77 external, 249 internal

132

10-GE MAC with XGMII

Single-speed full-duplex 10-Gbps MAC controller
Accelerates low-risk migration to next-generation networks
Compliant with IEEE P802.3ae draft D3.2 (to be ratified 3/02)
Xilinx is active member in IEEE 802.3ae committee
Supports LAN (10.3Gbps) & WAN (OC192 9.953Gbps) rates

Interoperates with industry-standard PHY ASSPs

Available now as a LogiCORE product from Xilinx
Downloadable over the Internet
Occupies 33% (3269 slices) of Virtex-II 2V2000

10 Gigabit Ethernet

133

Additional 10-GE
MAC Features
Optional support for VLAN frames
Virtual LAN allows network administrators to reduces the time it
takes to implement moves, adds and changes

Optional support for JUMBO frames (9k max)

Powerful statistics gathering
Allows network administrators to manage the network

Configured and monitored through a uP-independent

interface
Optional flow control through MAC Control pause frames
Integrated MDIO port for management of PHY layers
10 Gigabit Ethernet

134

10Gb Ethernet MAC w/ XGMII

Client
Interface
(FIFO)

MAC

PCS

WIS

P
M
A

OSI Layer 1 (PHY)

XGMII
XGMII

P
M
D

Glossary
MAC : Medium Access Control
PCS : Physical Coding Sublayer
WIS : WAN Interface Sublayer
XGMII : 10 Gig Medium Independent Interface
PMA : Physical Media Attachment Sublayer
PMD : Physical Medium Dependent Sublayer

Compliant with IEEE802.3ae, ver. D3.2 (to be ratified 03/02)

Single speed full-duplex 10 Gbps MAC controller

32b XGMII interface 312.5Mbps, per HSTL Class 1 drivers

64b internal data path and back-end interface, 156.25MHz SDR operation
Can interface to industry standard ASSP PHY chips
Supports LAN (10.3Gbps) & WAN (OC192 9.953Gbps) Line rates

10 Gigabit Ethernet

135

10GE MAC with XGMII

Interface
Back-End
Interface

10 GE MAC + XGMII CORE

XGMAC

TX Data
TX Ctrl

XGMII

64
Transmit
Engine

8
16

RX Data
RX Ctrl

RS/XGMII
RS/XGMII

TX
I/O

Flow
Control

64

Receive
Engine

RX
I/O

XGMII

Management

MDIO I/F

10 Gigabit Ethernet

136

MDIO I/F

Virtex-II, Virtex-II Pro

10 GE MAC with XAUI

Interface
Back-End
Interface

10 GE MAC + XAUI CORE

XGMAC

TX Data
TX Ctrl

PCS/PMA
PCS/PMA

XAUI

64
Transmit
Engine

Pause Req
Pause Value 16
RX Data
RX Ctrl

XAUI Floorplan
2VP7

Rocket I/O
Transceivers

Flow
Control

64

Receive
Engine

XGMII

Management

MDIO I/F

10 Gigabit Ethernet

137

Virtex-II Pro only

The 10 Gigabit Ethernet

Family

In FPGA

Media Access Control (MAC)

Full Duplex
10 Gigabit Media Independent Interface (XGMII) or
10 Gigabit Attachment Unit Interface (XAUI)
WWDM
LAN PHY
(8B/10B)

Can interface
to

WWDM Serial Serial Serial

PMD
PMD
PMD
PMD
1310 nm 850 nm 1310 nm 1550 nm

10GBASE-LX4

10GBASE-X
10 Gigabit Ethernet

Serial
LAN PHY
(64B/66B)

138

10GBASE-LR
10GBASE-SR 10GBASE-ER

10GBASE-R

Serial
WAN PHY
(64B/66B + WIS)
Serial Serial Serial
PMD
PMD
PMD
850 nm 1310 nm 1550 nm

10GBASE-SW 10GBASE-EW
10GBASE-LW

10GBASE-W

40 Gbps Switch Fabric

PM8355 = 4-Channel 2.0
to 3.125 Gbps
Transceiver

MGTs
MGTs
MGTs
MGTs

10 Gigabit Ethernet

139

MGTs

GMAC
GMAC/PCS/PMA
Virtex-II Pro
Virtex-II Pro

MGTs

XGMAC
XGMAC/XAUI

Simple 10GbE Line Card

To Backplane

XAUIlike

Buffer

XGMAC

XAUI

10GBASE-R Serial LAN PHY

XenPak

Memory
XAUI

10 Gigabit Ethernet

140

64B/66B
PCS

SERDES

E/O

Fiber

10GbE Optical Modules

XenPak MSA current market favourite to succeed

1.5 x 4.5 footprint
XAUI interface to MAC
http://www.xenpak.org/

10 Gigabit Ethernet

141

10GBASE-X (WWDM)
10GBASE-X PCS is functionally identical to XAUI
Some management registers move around in the address space
Signal detect pins used
from optics
E/O

XenPak

E/O
Optical
E/O

XGMAC

XAUI
E/O

10 Gigabit Ethernet

142

MUX

A 10 Gigabit Ethernet LAN/WAN

Line Card Design Example

Integrated
Optics

OC-192 POS

ASSP

10GE
PHY
LAN/WAN

FPGA
10GE MAC

Implementation review

10 Gigabit Ethernet MAC (10GE)

CSIX
RapidIO
POS-PHY Level 4 (PL4)

10 Gigabit Ethernet

143

ASSP
NPU

CSIX
FPGA
CSIX Bridge

RapidIO
ASSP
Terabit
Switch
Fabric

Backplane

ASSP

POS-PHY L4

XAUI

XenPak

10 Gigabit Ethernet
Interfaces
Name

Number of Data Rate

Lines
Per Line

Number of
Useful
Comments
Clock and
Transmission
Control Lines Distance

XGMII
10Gb/s
Media
Independent
Interface
XSBI
10Gbps
Serial Bus
Interface
XAUI
10Gbps
Attachment
Unit Interface

32 TX
32 RX

312.5 Mbps

4 Tx Ctrl
1 Tx Clk
4 Rx Ctrl
1 Rx Clk

< 7cm (3)

74 Signal
Lines

16 TX
16 RX
LVDS

622 Mbps

1 Tx Clk
1 Rx Clk

<20 cm (8) +
1 connector

64 Signal
lines

None

>50 cm (20) 16 signal

+ 2 connectors lines

10 Gigabit Ethernet

144

4 TX
3.125Gbps
4 RX
Differential

10 Gigabit Ethernet
Interfaces
Name

Number of Data Rate

Lines
Per Line

Comments
Useful
Number of
Transmission
Clock and
Control Lines Distance

XGMII
10Gb/s
Media
Independent
Interface
XSBI
10Gbps
Serial Bus
Interface
XAUI
10Gbps
Attachment
Unit Interface

32 TX
32 RX

312.5 Mbps

4 Tx Ctrl
1 Tx Clk
4 Rx Ctrl
1 Rx Clk

< 7cm (3)

74 Signal
Lines

16 TX
16 RX
LVDS

622 Mbps

1 Tx Clk
1 Rx Clk

<20 cm (8) +
1 connector

64 Signal
lines

None

>50 cm (20) 16 signal

+ 2 connectors lines

10 Gigabit Ethernet

145

4 TX
3.125Gbps
4 RX
Differential

XGMII
Logical Interface between
MAC and PHY
Convenient partition for
specification

Support multiple PHY types

Support existing management
interface and register set

Xilinx XGMAC

XGMII
PCS
PMA
PMD

Fiber

10 Gigabit Ethernet

146

XGMII
4 lane parallel interface
32 bits Data and 4 Control bits TX
32 bits Data and 4 Control bits RX

Control bit allows embedded delimiters

DDR signalling, source centred
156.25MHz clock (one TX, one RX)
312.5 Mbps on each data/control line.

10 Gigabit Ethernet

147

XGMII Control Codes

TXC
0
1
1
1
1
1

10 Gigabit Ethernet

148

TXD
0x00 through 0xFF
0x07
0x9C
0xFB
0xFD
0xFE

Description
Normal data transmission
Idle
Sequence (only valid in lane 0)
Start (only valid in lane 0)
Terminate
Error

XGMII Example Waveform

TX_C LK

TXC<3:0>

0xF

0x1 0x0

TXD<7:0>

TXD<15:8>

Dp

0xC

0xF

fram e dat a

Dp

frame da ta

TXD<23:16> I

Dp

frame da ta

TXD<31:24> I

Dp SF D

frame da ta

I: Idle c ontrol c hara cte r, S: St art control c harac ter, Dp: pream ble Da ta oc tet, T: Te rminat e c ontrol c harac te r

10 Gigabit Ethernet

149

Fault Reporting (1)

Local Fault and Remote Fault codes are defined
Both start with Sequence (D=0x9C, C=1) in lane 0

Allow coarse-grained fault finding prior to further

investigation
Local fault can be generated anywhere in the PHY
Remote fault only generated in the MAC in response to a
Local Fault message

10 Gigabit Ethernet

150

Fault Reporting (2)

Normal Operation
Device A

Device B
TX Idle Sequence

Idle Sequence RX

MAC/XAUI

MAC/XAUI

RX Idle Sequence

Idle Sequence TX

Simultaneous A and B power up and reset

Link Status OK in both A & B
MAC Transmission Enabled in both A & B
No negotiation or handshakes

10 Gigabit Ethernet

151

Fault Reporting (3)

Link Fault

Device A

Device B

TX Idle Sequence

No signal RX

MAC/XAUI

MAC/XAUI

RX Remote Fault

Remote Fault TX

PHY in Device B detects fault, passes LF message to MAC

Link Status FAIL in Device B
Device B signals Remote Fault to Device A
Link Status FAIL in Device A
MAC Transmission halted in both A & B

10 Gigabit Ethernet

152

XGMII Clock Management

GTX_CLK
IBUFG

XGMAC Core
DCM

CLKIN
FB

BUFG

CLK0

FDDRRSE

CLK90

XGMII_TX_CLK
BUFG

TX_CLK
BUFG
RX_CLK

DCM
CLK0

IBUFG

CLKIN
FB

10 Gigabit Ethernet

153

XGMII_RX_CLK

XGMII Weaknesses
Single ended I/O standard
HSTL Class I limited to 3 track length (unterminated)

Lots of pins
78 pins for entire interface

Physical layout is therefore difficult at best

10 Gigabit Ethernet

154

10 Gigabit Ethernet
Interfaces
Name

Number of
Lines

Data Rate
Per Line

Number of
Useful
Comments
Clock and
Transmission
Control Lines Distance

XGMII
10Gb/s
Media
Independent
Interface
XSBI
10Gbps
Serial Bus
Interface
XAUI
10Gbps
Attachment
Unit
Interface

32 TX
32 RX

312.5 Mbps

4 Tx Ctrl
1 Tx Clk
4 Rx Ctrl
1 Rx Clk

< 7cm (3)

74 Signal
Lines

16 TX
16 RX
LVDS

622 Mbps

1 Tx Clk
1 Rx Clk

<20 cm (8) +
1 connector

64 Signal
lines

None

>50 cm (20)
+2
connectors

16 signal
lines

10 Gigabit Ethernet

155

4 TX
3.125Gbps
4 RX
Differential

XAUI
10 Gigabit eXtended Attachment Unit Interface
Used to extend the 10G Media Independent Interface
4 lane serial, embedded clock
battle-tested 8B10B encoding on each lane
Allows interconnects of over 500mm (20) on standard FR-4
material
Even longer on specialized materials e.g. GETek, RT-Duroid
Protocol and PHY Independent

Hot Swappable

10 Gigabit Ethernet

156

Why XAUI is Important

Example: Current 10GE solution with XGMII extender
Virtex-II
MAC

TXC
TXD

Media Access
Control RXC
RXD

36

36

PCS/PMA
Physical Coding
Sublayer/ Physical
Media Attachment

Parallel
XGMII

Issue: 2 max

157

Dependent
Interface

Serial
XAUI

Up to 20

Allows up to 20 trace plus 2 connectors

10 Gigabit Ethernet

PMD
Four Serial Channels
Physical Medium
Bonded Together

Greater layout flexibility

Allows back plane implementations

Virtex-II Pro Integrates XAUI

V-II PRO
MAC

XAUI

TX

PMD

PCS/PMA
RX

Benefits
Lowers pin count and device count
Solves jitter and skew issues

10 Gigabit Ethernet

158

XAUI Electrical Interface

At 3.125Gbps, /4 = 1
Starting to look like Microwave Engineering again

100 ohm differential impedance

Intel suggest stripline configuration
Cohn, Seymour B., "Characteristic Impedance of the Shielded-Strip Transmission Line,"
IRE Transactions on Microwave Theory and Techniques, Vol MTT-2, No. 3, July 1954, pp.
52-57.

10 Gigabit Ethernet

159

Mapping from XGMII to XAUI

31

Data
TXD[31:0]
24 23 16 15
8 7 6 5 4 3 2 1 0

Control
TXC[3:0]
3 2 1 0

Byte
Byte Byte Byte Lane 0= TXD[7:0]+TXC[0]
Lane 3 Lane 2 Lane 1

7 6 5 4 3 2 1 0
8+control
HGFEDCBA,K
8B10B Encoder
10
abcdefghij

0 1 2 3 4 5 6 7 8 9

10 Gigabit Ethernet

160

XAUI Control Codes

Codegroup Description
Dxx.y
Normal data
transmission
K28.5
/K/ (Sync)
K28.0
/R/ (Skip)
K28.3
/A/ (Align)
K28.4
/Q/ (Sequence)
K27.7
/S/ (Start)
K29.7
/T/ (Terminate)
K30.7
/E/ (Error)

10 Gigabit Ethernet

161

MGTs Advantage

10 Gigabit Ethernet

162

Transceiver Module

8B/10B
TXDATA

Encode

FIFO

Serializer

Transmit
Transmit
Buffer
Buffer

TX Clock
Clock Generator
TX
Generator

40 MHz -156 MHz

Transmitter
20X Multiplier

REFCLK

Receiver

Comma Detect
and Word
Alignment

RXDATA

TX+
TX-

Loopback

8B10B encode/decode with

error detection
Comma detection
RX elastic buffer/channel
bonding
A state-of-the-art PMA
(Ser/Des)

RX
Generator
RXClock
Clock
Generator

Elastic

8B / 10B

Buffer

Decode

Deserializer
Deserializer

Receive
Buffer

RX+
RX-

Idle Generation
Idle XGMII is translated to ||A||, ||K|| and ||R||
Simple rules for mapping into these codes
First idle after data alternates between ||A|| and ||K||, unless an
||A|| is not due, then ||K|| is sent
||R|| is the second idle after data
||A|| codes are separated by no less than 16 columns and no
more than 31 columns
If not sending an ||A||, either ||R|| or ||K|| is sent, randomly
distributed

10 Gigabit Ethernet

163

Idle Generation (2)

XGMII
T/RXD<7:0 >

S Dp D

D --- D

T/RXD<15: 8>

Dp Dp D

D --- D

T/ RX D<23 :1 6>

Dp Dp D

D --- D

T/ RX D<31 :2 4>

Dp Ds D

D --- D

PCS
LANE 0

S Dp D

D --- D

LANE 1

R Dp Dp D

D --- D

LANE 2

R Dp Dp D

D --- D

LANE 3

R Dp Ds D

D --- D

Le gend :
Dp re pres ents a da ta ch arac ter co ntaining the prea mble pattern
Ds re pres ents a da ta ch arac ter co ntaining the SFD pa ttern

10 Gigabit Ethernet

164

Channel Synchronization
Each line has to find the byte boundary
Uses Comma characters in 10B stream (0011111xxx or
1100000xxx)
This doesnt appear anywhere else

Follow state machine in 10GbE specification

Not the same as the state machine within the MGTs
Must be implemented in CLB logic

10 Gigabit Ethernet

165

Channel Bonding
Aligns the lanes to each other
Can deal with up to 84UI of lane-to-lane skew (26.9 ns)
Lane 0
Lane 1
Lane 2
Lane 3

K
K
R
R

K
R
K
K

R
K
K
K

A
K
R
K

K
R
A
R

R
A
K
A

R
K
R
K

K
R
R
R

Lane 0
Lane 1
Lane 2
Lane 3

10 Gigabit Ethernet

166

K
R
K
R

K
K
K
K

R
K
K
K

K
K
K
K

K
K
R
K

R
R
R
R

R
R
K
R

A
A
A
A

R
K
R
K

K
K
K
K

R
R
R
R

R
R
R
R

K
K
K
K

K
K
K
K

R
R
R
R

K
K
K
K

R
R
R
R

R
R
R
R

Channel Bonding (2)

Alignment achieved according to state machine in
specification
Must be implemented in CLB Logic

Aligns on ||A|| code groups

Causes read pointers in MGT elastic buffers to (hopefully)
centre on the same point
LF sent up to MAC until lanes are deskewed

10 Gigabit Ethernet

167

Link Initialization (1)

Device A

Device B
TX Idle Sequence+RF

Idle Sequence+RF RX

MAC/XAUI

MAC/XAUI

RX No Signal

Device A powered up and reset

Device B powered down
Device A detects fault
Device A signals RF to Device B
Link Status = FAIL in Device A
MAC Transmission halted in Device A

10 Gigabit Ethernet

168

No Signal TX

Link Initialization (2)

Device A

Device B
TX Idle Sequence+RF

Idle Sequence+RF RX

MAC/XAUI

MAC/XAUI

RX No Signal

Idle Sequence TX

Device B powers up and resets

Device B signals Idle to Device A
Device A hasnt synchronised and deskewed yet
Link Status = FAIL in both A and B
MAC Transmission halted in both A and B

10 Gigabit Ethernet

169

Link Initialization (3)

Device A

Device B
TX Idle Sequence

Idle Sequence+RF RX

MAC/XAUI

MAC/XAUI

RX Idle Sequence

Idle Sequence TX

Device A RX detects idle sequence, synchronises and deskews

Device A stops sending RF to Device B
Device A Link Status = OK
MAC transmission enabled in Device A
When Device A idle reaches Device B, normal operation

10 Gigabit Ethernet

170

XAUI Clock Management

REFCLK
IBUFG
XGMAC Core
BUFG

GT_XAUI_2

DCM
CLKIN CLK0
FB
TX_CLK

RX_CLK

10 Gigabit Ethernet

171

BUFG

GT_XAUI_2
REFCLK
GT_XAUI_2
REFCLK
GT_XAUI_2
REFCLK
REFCLK
TXUSRCLK
TXUSRCLK2
TXUSRCLK
RXUSRCLK
TXUSRCLK2
TXUSRCLK
RXUSRCLK2
RXUSRCLK
TXUSRCLK2
TXUSRCLK
RXUSRCLK2
RXUSRCLK
TXUSRCLK2
RXUSRCLK2
RXUSRCLK
RXUSRCLK2

10 Gigabit Ethernet
Interfaces
Name

Number of Data Rate

Lines
Per Line

Number of
Useful
Comments
Clock and
Transmission
Control Lines Distance

XGMII
10Gb/s
Media
Independent
Interface
XSBI
10Gbps
Sixteen Bit
Interface
XAUI
10Gbps
Attachment
Unit Interface

32 TX
32 RX

312.5 Mbps

4 Tx Ctrl
1 Tx Clk
4 Rx Ctrl
1 Rx Clk

< 7cm (3)

74 Signal
Lines

16 TX
16 RX
LVDS

622 Mbps

1 Tx Clk
1 Rx Clk

<20 cm (8) +
1 connector

64 Signal
lines

None

>50 cm (20)
16 signal
+ 2 connectors lines

10 Gigabit Ethernet

172

4 TX
3.125Gbps
4 RX
Differential

XSBI

10 Gigabit Sixteen Bit Interface

Interface to the serial PHY serdes
16 bits LVDS in each direction
640 MHz SDR is a challenge...
but APD have a reference design in the pipe

10 Gigabit Ethernet

173

Summary

Summary
10GbE is much more cost effective than SONET
In the end economics always influence key decisions
Native Ethernet at 10Xs the performance/cost will displace SONET
infrastructure over the long run especially when the traffic is IP

Simple, scalable, manageable, reliable, interoperable, multiprotocol support, high performance, application-enabler, cost
effective
Ethernet leveraged into other technologies
Ethernet over SONET, Wireless Ethernet - IEEE 802.11b/a,
Resilient Packet Ring (RPR)

10 Gigabit Ethernet

175

Summary
Service providers are delivering optical IP/Ethernet-based
solutions
Ethernet provides just-in-time bandwidth, usage based billing,
application aware networks, w/ customer control
Requirements exist today
Storage application providers, streaming video, medical imaging

Ethernet challenge for SPs

Key missing element in Ethernet is OAM support
Pricing 10/100/1000 Mbps Ethernet services vs. T1/T3/OC3

Xilinx solutions provide layer 1 and 2 solutions for Gigabit

Ethernet and 10 Gigabit Ethernet (XGMII, XAUI, XSBI)
10 Gigabit Ethernet

176

Extra

IEEE 802.3 PHY

Specifications
Standard
1Base5
10Base5
10Base2
10Broad36
FOIRL
10Base-T
10Base-FL
10Base-FB
10Base-FP
100Base-TX
100Base-FX
100Base-T4
100Base-T2
1000Base-LX
1000Base-LX
1000Base-LX
1000Base-SX
1000Base-SX
1000Base-CX
1000Base-T

10 Gigabit Ethernet

IEEE Data Rate

802.3e
802.3
802.3a
802.3b
802.3d
802.3i
802.3j
802.3j
802.3j
802.3u
802.3u
802.3u
802.3y
802.3z
802.3z
802.3z
802.3z
802.3z
802.3z
802.3ab

178

1 Mb/s
10Mb/s
10Mb/s
10Mb/s
10Mb/s
10Mb/s
10Mb/s
10Mb/s
10Mb/s
100Mb/s
100Mb/s
100Mb/s
100Mb/s
1Gb/s
1Gb/s
1Gb/s
1Gb/s
1Gb/s
1Gb/s
1Gb/s

Medium

Topology

Two pairs of twisted telephone cable

Single 50-ohm coaxial cable (thick Ethernet)
Single 50-ohm RG 58 coaxial cable (thin Ethernet)
Single 75-ohm CATV broadband cable
Two Optical Fibers
Two pairs of 100-ohm Category 3 or better UTP cable
Two optical fibers
Two Optical Fibers
Two Optical Fibers
Two pairs of 100-ohm Category 5 UTP cable
Two Optical Fibers
Four pairs of 100-ohm Category 3 or better UTP cable
Two pairs of 100-ohm Category 3 or better UTP cable
Long wavelength laser (1300nm) over 62.5um multi-mode fiber
Long wavelength laser (1300nm) over 50um multi-mode fiber
Long wavelength laser (1300nm) over 10um Single mode fiber
Short wavelength laser (850nm) over 62.5um multi mode fiber
Short wavelength laser (850nm) over 50um multi mode fiber
Specialty shielded balanced copper jumper cable assemblies
Four pairs of 100-ohm Category 5 or better cable

Star
Bus
Bus
Bus
Star
Star
Star
Star
Star
Star
Star
Star
Star
Star
Star
Star
Star
Star
Star
Star

Max. Cable Length

Half Duplex Full Duplex
250M
N/A
500 M
N/A
185M
N/A
1800M
N/A
1000M
>1000
100M
100M
2000M
>2000M
2000M
N/A
1000M
N/A
100M
100M
412M
2000M
100M
N/A
100M
100M
316M
550M
316M
550M
316M
5000M
275M
275M
316M
550M
25M
25M
100M
100M

10 Gigabit Ethernet

179

XAUI - Interface Extender

Between MAC & PCS

10 Gigabit Ethernet

180

10 Gigabit Ethernet

181