8255

Programmable Peripheral Interface

Intel 8255 PPI

Very commonly used peripheral chip used for
interfacing I/O devices with microprocessor.
It can be programmed to transfer data under
various conditions: simple and interrupt I/O.

Features of the 8255

It consists of three 8-bit bidirectional I/O ports
: A, B, and C , that can be configured to meet
different system I/O needs.
The individual ports can be programmed to be
input or output.

Pin Diagram
PA3

40

PB4

PA2

39

PB5

PA1

38

PB6

PA0

37

PB7

RD

36

WR

CS

35

RESET

GND

34

D0

A1

33

D1

A0

32
31

D2
3
D3

30

D4

PC7

10

PC6

11

PC5

12

29

D5

PC4

13

28

D6

PC0

14

27

D7

PC1

15

26

VCC

PC2

16

25

PB7

PC3

17

24

PB6

PB0

18

23

PB5

PB1

19

22

PB4

PB2

20

21

PB3

8255A

Architecture of the 8255A

Data Bus buffer

It is a 8-bit bidirectional Data bus.
Used to interface between 8255 data bus with
system bus.
The internal data bus and Outer pins D0-D7 pins
are connected in internally.
The direction of data buffer is decided by
Read/Control Logic.

Read/Write Control Logic

Manage all of the internal and external
transfers of both Data and Control or Status
words.
CS (Chip Select). A "low" on this input pin
enables the communication between the 8255
and the CPU.
RD (Read). A "low" on this input pin enables
8255 to send the data or status information to
the CPU on the data bus.

 WR (Write). A "low" on this input pin enables

the CPU to write data or control words into
the 8255.
A0 and A1 (Port Select 0 and Port Select 1).
These input signals, in conjunction with the
RD and WR inputs, control the selection of
one of the three ports or the control word
register.

 (RESET) Reset. A "high" on this input initializes

the control register to 9Bh and all ports (A, B,
C) are set to the input mode

Group Control Logic

CPU outputs a control word to the 8255 which
contains information such as mode, bit set/bit
reset.
Each of the Control blocks (Group A and
Group B) accepts "commands" from the
Read/Write Control logic, receives control
words from the internal data bus and issues
the proper commands to its associated ports.

 The group control logic is split into two similar

sub sytems
Group A control which configures Port A and the
upper 4-bits of Port C.
Group B control which configures Port B and the
lower 4-bits of Port C.

Group A and Group B control

Group A and B get the Control Signal from

CPU and send the command to the
individual control blocks.
Group A send the control signal to port A
and Port C (Upper) PC7-PC4.
Group B send the control signal to port B
and Port C (Lower) PC3-PC0.

Ports
There are four ports which can be configured
as either input or output.
Port A is an indivisible 8-bit port. Port B is an
indivisible 8-bit port. Port C (upper) is an
indivisible 4-bit port. Port C (lower) is an
indivisible 4-bit port.

PORT A
This is a 8-bit buffered I/O latch, can be
programmed as input or output port.
It can also be an 8-bit bidirectional port.
It can be programmed by mode 0 , mode 1,
mode 2 .

PORT B
This is a 8-bit buffer I/O latch, can be
programmed as in input or output port.
It can be programmed by mode 0 and mode 1
It cannot be used as an 8-bit bi-directional
port.

PORT C
It is splitted into two parts. Port C can also be
either an input or an output port.
Each 4 bit port can be either an input or an
output port.
It can be programmed by bit set/reset
operation.

Operation modes
BSR mode
I/O mode
I/O mode is of 3 types
Mode 0: Simple I/O
Mode 1: Handshaking I/O
Mode 2: Bidirectional I/O

I/O Mode of the 8255

 If D7 = 0, then it is BSR (bit set/reset) mode,

the bits of port C are programmed
individually.

MODE 0(Simple input / Output):

In this mode , port A, port B and port C is used
as individually (Simply) input or output ports.
Outputs are latched , Inputs are buffered not
latched.
Ports do not have Handshake or interrupt
capability.
Data are simply written to or read from a port
by initiating Read command with proper port
address

Example
Write a program to initialize 8255 in following
configuration.
Port A: Simple input
Port B: Simple input
Port C(Lower): Output
Port C(Upper): input
Assume address of control word register o 8255 is
83H

MVI A,98H ;Load control word

OUT 83H ;Send control word

MODE 1 :(Input/output with Hand

shake)
In this mode, input or output is transferred by
hand shaking Signals.
Handshaking signals is used to transfer data
between whose data transfer is not same.
Each port uses three lines from port C as
handshake signals

 In this mode handshake signals are exchanged

between the port and the peripheral device prior
to transfer of the data.
Ports A and B are the data ports. Port C assumes
the role of supplying the handshaking signals.
Each data port uses 3-bits of port C for
handshaking signals. The remaining 2-bits of port
C are available for simple I/O functions.
Mode 1 supports interrupt logic

Mode 1 - Input Port with Handshaking

Mode 1 - Input Port with Handshaking

STB/ (Strobe Input)
Active low
Indicate that it has transmitted a byte of data
IBF (Input Buffer Full)

Indicate that the input latch has received the byte

data
It is reset when MPU reads the data

 INTR (Interrupt Request)

Used to interrupt the MPU
Generated if STB/, IBF and INTE (internal flip-flop) are
all at logic 1
Reset by the falling edge of the RD/ signal

INTE (Interrupt Enable)

Internal flip-flop used to enable or disable the
generation of the INTR signal

 The peripheral checks the IBF signal to ensure

the 8255A is ready for data ( i.e. the processor
has read the previous data ).
The peripheral places the data it wishes to
send to the processor onto the data port.
The peripheral asserts the strobe signal ( STB =
0)

 The 8255A latches the data on the port using the STB/
signal to enable its input latches.
After latching the data the 8255A asserts the IBF signal
to tell the peripheral it has read the data and that the
input latches are full.
The IBF signal remains asserted until the processor
reads the data stored in the port latches.
On receiving the IBF signal from the 8255A, the
peripheral de-asserts the STB/ signal.

 Alternative -- Interrupt Driven System

If the INTE bit of the port is set (accomplished by bit set facility on
port C) then when both IBF and STB/ are logic 1 an interrupt is
generated on the ports INTR line.
With this line connected to one of the 8085As interrupt input pins
and with processor interrupts enabled then when INTR goes high an
interrupt service routine will be executed.
The ISR is required to read the data from the 8255A input port.
When the data has been read from the port, the 8255A de-asserts
its IBF control signal telling the peripheral device that the data has
been read by the processor and that it is free to send new data.

Mode 1 - Output Port with

Handshaking

Mode 1 - Output Port with

Handshaking
ACK/ (Acknowledge)
MPU must set this input signal low
Indicate that MPU receives the data from the 8255A
port
OBF/ (Output Buffer Full)
Goes low when MPU writes data into the output latch
Indicate that new data is ready to be read

 INTR (Interrupt Request)

Used to interrupt the MPU
Generated if ACK, OBF and INTE (internal flip-flop) are
all at logic 1
Reset by the falling edge of the RDsignal

INTE (Interrupt Enable)

Internal flip-flop used to enable or disable the
generation of the INTR signal

 An initial state is assumed with the output data

latches of the 8255A empty and the peripheral
device is ready to accept data.
The processor writes data, destined for the
peripheral, to the 8255As data latches.
Loading data into the data latches of the 8255A
clears the interrupt request output of the 8255A
(INTR = 0) and asserts the output buffer full flag
(OBF = 0).

 The peripheral device reads the output data of

the 8255A when it sees OBF asserted.
Once the peripheral has read the data, it
generates an ACK = 0 pulse to tell the 8255A
that its output data has been read.

Example
Write a program to initialize 8255 in following
configuration.
Port A: Output with handshake
Port B: input with handshake
Port C(Lower): Output
Port C(Upper): input
Assume address of control word register o 8255 is
23H

D7

D6

D5

D4

D3

D2

D1

D0

MVI A, AEH
OUT 23H

;Load control word

;Send control word

MODE 2:bi-directional I/O data

transfer
This mode allows bidirectional data transfer over a
single 8-bit data bus using handshake signals.
When operated in Mode 2, port A becomes bidirectional.
The bi-directional operational mode for port A is
supported by five handshaking signals using bits of port
C.
Port B can be operated in either mode 0 or mode 1.
When used in mode 1 the remaining three bits of port
C assume the role of handshaking signals for port B.

 If port B is used in mode 0 the remaining bits

of port C can be programmed in mode 0 to be
either an output port or an input port.

Mode 2 control word

Mode 2 - Sequencing

 Read data from peripheral followed by writing data to

peripheral
Data is placed on PA0 - PA7 by the peripheral
Peripheral asserts its STB/ output telling 8255 data to be
read. The 8255A latches the data in its input buffers.
The 8255 asserts its IBF output to tell the peripheral the
data has been latched but not read by the processor.
The peripheral de-asserts its STB/ output with IBF still set.
The 8255A requests an interrupt ( assuming interrupts are
used)

 Processor write sequencing

Data is output from the processor and latched by
the 8255A using the WR signal.

The rising edge of WR causes the OBF to be

asserted, telling the peripheral device there is data
for it to read.
The peripheral enables its input buffers and tells
the 8255A it is ready to receive data by asserting
the ACK flag.

 On the falling edge of ACK, the 8255A releases its

latched data onto the lines PA0 - PA7. The data is
read by the peripheral device.
The 8255A de-asserts its OBF flag telling the
peripheral there is no further data to read.
The rising edge of ACK causes the 8255A to
generate an interrupt request. ( if this feature is
used ). The interrupt tells the processor that the
peripheral has read the data and that further data
can be written to the 8255A.

BIT SET/RESET MODE

 A very useful feature of port C of the 8255A,

when it is not being used for handshake
operations, is its bit-set / bit-reset capability.
PC0-PC7 is set or reset as per the status of D0.
A BSR word is written for each bit