Abstract

This project consists of two parts1. In the first part we will design digital circuits on a FPGA based platform (SPARTAN 3E)
using verilog and simulate the same in Orcad Pspice.
2. In the second part we will inject stuck at 0 and stuck at 1 fault in the above mentioned
circuit and generate a test pattern based on fault injection in the FPGA.
This method is able to perform fault diagnosis for stuck-at-0 and stuck-at-1 faults, which can
locate resource faults in the logic elements of FPGA We use SPARTAN 3Eas the object to
generate the test pattern, work out the test circuit and synthesis them Finally, the test circuit is
injected with stuck-at-0 and stuck-at-1 faults and the test patterns are generated by using
PSPICE.
On many occasions, the working environment (such as electrical stress, field effect, temperature
and so on) always leads to the logic resource failure which happens in LE (Logic Element). We
approach a test pattern generation method based on fault injection for logic elements of FPGA.
We design the circuit using verilog and synthesize the same using Xilinx Project Navigator on
the FPGA. Building the corresponding simulation model in SPICE, we inject fault (s-a-0 or s-a1 fault) to every required node and make simulation. In each simulation we can get a
corresponding test pattern. When the s-a-0 or s-a-1 fault occurs in FPGA, using the test pattern
can locate the fault logic resource. Because the FPGA can be reconfigured, we can repair the
system function by changing of the layout.