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Chapter 8: Memory Management!
Chapter 8: Memory Management!

Background"
Swapping "
Contiguous Allocation"
Paging"
Segmentation"
Segmentation with Paging"
Operating System Concepts!
8.2!
Silberschatz, Galvin and Gagne 2005!
Background!
Program must be brought into memory and placed within a process
for it to be run"
"
Input queue or job queue collection of processes on the disk
that are waiting to be brought into memory to run the program"

"
User programs go through several steps before being run"
8.3!
Binding of Instructions and Data to Memory!

Address binding of instructions and data to memory addresses can
happen at three different stages"
Compile time: If memory location known a priori, absolute
code can be generated; must recompile code if starting location

changes"
Load time: Must generate relocatable code if memory location
is not known at compile time"

Execution time: Binding delayed until run time if the process
can be moved during its execution from one memory segment

to another. Need hardware support for address maps (e.g.,
base and limit registers). "
8.4!
Multistep Processing of a User Program!
8.5!
Logical vs. Physical Address Space!

The concept of a logical address space that is bound to a separate
physical address space is central to proper memory management"
Logical address generated by the CPU; also referred to as

virtual address"
Physical address address seen by the memory unit"
Logical and physical addresses are the same in compile-time and
load-time address-binding schemes; logical (virtual) and physical

addresses differ in execution-time address-binding scheme"
8.6!
Memory-Management Unit (MMU)!

Hardware device that maps virtual to physical address
"
In MMU scheme, the value in the relocation register is added to
every address generated by a user process at the time it is sent to

memory
"
The user program deals with logical addresses; it never sees the
real physical addresses"
8.7!
Dynamic relocation using a relocation register!
8.8!
Swapping!
A process can be swapped temporarily out of memory to a backing
store, and then brought back into memory for continued execution
"
Backing store fast disk large enough to accommodate copies of
all memory images for all users; must provide direct access to
these memory images
"
Roll out, roll in swapping variant used for priority-based
scheduling algorithms; lower-priority process is swapped out so
higher-priority process can be loaded and executed
"
Major part of swap time is transfer time; total transfer time is
directly proportional to the amount of memory swapped
"
Modified versions of swapping are found on many systems (i.e.,
UNIX, Linux, and Windows)"
8.9!
Schematic View of Swapping!
8.10!
Demand Paging!
Bring a page into memory only when it is needed"
Less I/O needed"
Less memory needed "
Faster response"
More users
"
Page is needed reference to it"
invalid reference abort"
not-in-memory bring to memory"
"
8.11!
Transfer of a Paged Memory to Contiguous Disk Space!
8.12!
Valid-Invalid Bit!
With each page table entry a validinvalid bit is associated
(1 in-memory, 0 not-in-memory)"
Initially validinvalid but is set to 0 on all entries"
Example of a page table snapshot:
Frame #"
valid-invalid bit"
1"
1"
1"
1"
0"
!"
0"
0"
page table"
"
During address translation, if validinvalid bit in page table entry is 0
page fault"
8.13!
Page Table When Some Pages Are Not in Main Memory!
8.14!
Steps in Handling a Page Fault!
8.15!
What happens if there is no free frame?!

Page replacement find some page in memory, but not
really in use, swap it out"
algorithm"
performance want an algorithm which will result in

minimum number of page faults"
Same page may be brought into memory several times"
8.16!
Memory Allocations!
8.17!
Contiguous Allocation!
Main memory usually into two partitions:"
Resident operating system, usually held in low memory with

interrupt vector"
User processes then held in high memory

"
Each (Single-partition) allocation"
Relocation-register scheme used to protect user processes

from each other, and from changing operating-system code
and data"
Relocation register contains value of smallest physical address;

limit register contains range of logical addresses each logical
address must be less than the limit register "
8.18!
A base and a limit register define a logical address space!
8.19!
HW address protection with base and limit registers!
8.20!
Contiguous Allocation (Cont.)!

Multiple-partition allocation"
Hole block of available memory; holes of various size are

scattered throughout memory"
When a process arrives, it is allocated memory from a hole

large enough to accommodate it"
Operating system maintains information about:

a) allocated partitions b) free partitions (hole)"
OS"
OS"
OS"
OS"
process 5"
process 5"
process 5"
process 5"
process 9"
process 9"
process 8"
process 2"
process 10"
process 2"
process 2"
8.21!
process 2"
Dynamic Storage-Allocation Problem!

How to satisfy a request of size n from a list of free holes"
First-fit: Allocate the first hole that is big enough"
Best-fit: Allocate the smallest hole that is big enough;
must search entire list, unless ordered by size. Produces

the smallest leftover hole."
Worst-fit: Allocate the largest hole; must also search
entire list. Produces the largest leftover hole."
First-fit and best-fit better than worst-fit in terms of

speed and storage utilization"
8.22!
Example!
Given free memory partitions of
100K, 500K, 200K, 300K, and 600K

(in order), how would each of the
First-fit, Best-fit, and Worst-fit
algorithms place processes of 212K,
417K, 112K, and 426K (in order)? "
Which algorithm makes the most
efficient use of memory? "
8.23!
Fragmentation!
External Fragmentation Gaps between allocated contiguous
memory - total memory space exists to satisfy a request, but it is

not contiguous"
Internal Fragmentation allocated memory may be slightly larger
than requested memory; this size difference is memory internal to a

partition, but not being used"
Reduce external fragmentation by compaction!
Shuffle memory contents to place all free memory together in

one large block"
Compaction is possible only if relocation is dynamic, and is

done at execution time"
I/O problem"
! Latch
! Do
job in memory while it is involved in I/O"
I/O only into OS buffers"
8.24!
Paging!
Logical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is

available"
Divide physical memory into fixed-sized blocks called frames
(size is power of 2, between 512 bytes and 8192 bytes)"

Divide logical memory into blocks of same size called pages."
Keep track of all free frames"
To run a program of size n pages, need to find n free frames and
load program"
Set up a page table to translate logical to physical addresses"
Internal fragmentation"
8.25!
Address Translation Scheme!

Address generated by CPU is divided into:
"
Page number (p) used as an index into a page table

which contains base address of each page in physical
memory
"
Page offset (d) combined with base address to define

the physical memory address that is sent to the memory
unit"
8.26!
Address Translation Architecture!
V"
V"
I"
8.27!
Paging Example !
8.28!
Paging Example!
8.29!
Free Frames!
Before allocation"
After allocation"
8.30!
Implementation of Page Table!

Page table is kept in main memory"
Page-table base register (PTBR) points to the page table"
Page-table length register (PRLR) indicates size of the page
table"
In this scheme every data/instruction access requires two
memory accesses. One for the page table and one for the
data/instruction."
The two memory access problem can be solved by the use
of a special fast-lookup hardware cache called associative

memory or translation look-aside buffers (TLBs)!
8.31!
Associative Memory!
Associative memory parallel search "
Page #"
Frame #"
"Address translation (A, A)"
If A is in associative register, get frame # out"
Otherwise get frame # from page table in memory"
8.32!
Paging Hardware With TLB!
Associate Memory"
8.33!
Effective Access Time!

Associative Lookup = time unit"
Assume memory cycle time is 1 microsecond"
Hit ratio percentage of times that a page number is found
in the associative registers; ration related to number of

associative registers"
Hit ratio = "
Effective Access Time (EAT)"
"
"EAT = (1 + ) + (2 + )(1 )"
"
"
"= 2 + "
"
8.34!
Memory Protection!
Memory protection implemented by associating protection bit
with each frame

"
Valid-invalid bit attached to each entry in the page table:"
valid indicates that the associated page is in the

process logical address space, and is thus a legal page"
invalid indicates that the page is not in the process

logical address space"
8.35!
Valid (v) or Invalid (i) Bit In A Page Table!
8.36!
Swapping!
8.37!
Virtual Memory!
Elusion to expand memory view onto
the secondary storage."

Moving pages frames between
memory and HD"

Demand paging"
8.38!
Demand Paging!
Bring a page into memory only when it is needed"
Less I/O needed"
Less memory needed "
Faster response"
More users
"
Page is needed reference to it"
invalid reference abort"
not-in-memory bring to memory"
"
8.39!
Transfer of a Paged Memory to Contiguous Disk Space!
8.40!
Valid-Invalid Bit!
With each page table entry a validinvalid bit is associated
(1 in-memory, 0 not-in-memory)"
Initially validinvalid but is set to 0 on all entries"
Example of a page table snapshot:
Frame #"
valid-invalid bit"
1"
1"
1"
1"
0"
!"
0"
0"
page table"
"
During address translation, if validinvalid bit in page table entry is 0
page fault"
8.41!
Page Table When Some Pages Are Not in Main Memory!
8.42!
Steps in Handling a Page Fault!
8.43!
What happens if there is no free frame?!

Page replacement find some page in memory, but not
really in use, swap it out"
algorithm"
performance want an algorithm which will result in

minimum number of page faults"
Same page may be brought into memory several times"
8.44!
Page Table Structure!

Hierarchical Paging"
Hashed Page Tables"
Inverted Page Tables"
8.45!
Hierarchical Page Tables!

Break up the logical address space into multiple page tables"
A simple technique is a two-level page table"
8.46!
Two-Level Paging Example!

A logical address (on 32-bit machine with 4K page size) is divided into:"
a page number consisting of 20 bits"

a page offset consisting of 12 bits"
Since the page table is paged, the page number is further divided into:"
a 10-bit page number "
a 10-bit page offset"
Thus, a logical address is as follows:
page number"
page offset"
p 2"
p i"
d"
10"
12"
10"
where pi is an index into the outer page table, and p2 is the displacement
within the page of the outer page table"
8.47!
Two-Level Page-Table Scheme!
8.48!
Address-Translation Scheme!
Address-translation scheme for a two-level 32-bit paging
architecture"
8.49!
Stop here!
8.50!
Hashed Page Tables!

Common in address spaces > 32 bits"
The virtual page number is hashed into a page table. This page
table contains a chain of elements hashing to the same location."

Virtual page numbers are compared in this chain searching for a
match. If a match is found, the corresponding physical frame is

extracted."
8.51!
Hashed Page Table!
8.52!
Inverted Page Table!

One entry for each real page of memory"
Entry consists of the virtual address of the page stored in
that real memory location, with information about the

process that owns that page"
Decreases memory needed to store each page table, but
increases time needed to search the table when a page

reference occurs"
Use hash table to limit the search to one or at most a
few page-table entries"
8.53!
Inverted Page Table Architecture!
8.54!
Shared Pages!
Shared code!
One copy of read-only (reentrant) code shared among

processes (i.e., text editors, compilers, window systems)."
Shared code must appear in same location in the logical

address space of all processes
"
Private code and data "
Each process keeps a separate copy of the code and data"
The pages for the private code and data can appear
anywhere in the logical address space"
8.55!
Shared Pages Example!
8.56!
Segmentation!
Memory-management scheme that supports user view of memory "
A program is a collection of segments. A segment is a logical unit
such as:"
"
"
"
"
"
"
"
"
"
"main program,"
"procedure, "
"function,"
"method,"
"object,"
"local variables, global variables,"
"common block,"
"stack,"
"symbol table, arrays"
8.57!
Users View of a Program!
8.58!
Logical View of Segmentation!

1"
4"
1"
2"
3"
2"
4"
3"
user space "
physical memory space"
8.59!
Stop here!
8.60!
Segmentation Architecture!
Logical address consists of a two tuple:"
"
"<segment-number, offset>,"
Segment table maps two-dimensional physical addresses;
each table entry has:"
base contains the starting physical address where the

segments reside in memory"
limit specifies the length of the segment"
Segment-table base register (STBR) points to the segment
tables location in memory"

Segment-table length register (STLR) indicates number of
segments used by a program;"

"
segment number s is legal if s < STLR"
8.61!
Segmentation Architecture (Cont.)!

Relocation."
dynamic"
by segment table
"
Sharing."
shared segments"
same segment number

"
Allocation."
first fit/best fit"
external fragmentation"
8.62!
Segmentation Architecture (Cont.)!

Protection. With each entry in segment table associate:"
validation bit = 0 illegal segment"
read/write/execute privileges"
Protection bits associated with segments; code sharing
occurs at segment level"

Since segments vary in length, memory allocation is a
dynamic storage-allocation problem"

A segmentation example is shown in the following diagram"
8.63!
Address Translation Architecture !
8.64!
Example of Segmentation!
8.65!
Sharing of Segments!
8.66!
Segmentation with Paging MULTICS!

The MULTICS system solved problems of external
fragmentation and lengthy search times by paging the

segments
"
Solution differs from pure segmentation in that the
segment-table entry contains not the base address of

the segment, but rather the base address of a page
table for this segment"
8.67!
MULTICS Address Translation Scheme!
8.68!
Segmentation with Paging Intel 386!

As shown in the following diagram, the Intel 386 uses
segmentation with paging for memory management with a

two-level paging scheme"
8.69!
Intel 30386 Address Translation!
8.70!
Linux on Intel 80x86!

Uses minimal segmentation to keep memory management
implementation more portable"

Uses 6 segments:"
Kernel code"
Kernel data"
User code (shared by all user processes, using logical
addresses)"
User data (likewise shared)"
Task-state (per-process hardware context)"
LDT"
Uses 2 protection levels:"
Kernel mode"
User mode"
8.71!
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Chapter 8: Memory Management!

Chapter 8: Memory Management!

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

that are waiting to be brought into memory to run the program"

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

Binding of Instructions and Data to Memory!

code can be generated; must recompile code if starting location

is not known at compile time"

can be moved during its execution from one memory segment

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

Multistep Processing of a User Program!

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

Logical vs. Physical Address Space!

physical address space is central to proper memory management"

Logical address generated by the CPU; also referred to as

Physical address address seen by the memory unit"

Logical and physical addresses are the same in compile-time and

load-time address-binding schemes; logical (virtual) and physical

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

Memory-Management Unit (MMU)!

every address generated by a user process at the time it is sent to

real physical addresses"

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

Dynamic relocation using a relocation register!

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

Schematic View of Swapping!

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

Less I/O needed"

Less memory needed "

Page is needed reference to it"

invalid reference abort"

not-in-memory bring to memory"

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

Transfer of a Paged Memory to Contiguous Disk Space!

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

Silberschatz, Galvin and Gagne 2005!

Page Table When Some Pages Are Not in Main Memory!

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

Steps in Handling a Page Fault!

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

What happens if there is no free frame?!

really in use, swap it out"

performance want an algorithm which will result in

Same page may be brought into memory several times"

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!

Operating System Concepts!

Silberschatz, Galvin and Gagne 2005!