Survey On Fault

This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TPEL.2014.2304561, IEEE Transactions on Power Electronics
Survey on Fault-Tolerant Techniques for Power

Electronic Converters
Wenping Zhang, Student Member, IEEE, Dehong Xu, Fellow, IEEE, Prasad N. Enjeti, Fellow, IEEE, Haijin Li,
Student Member, IEEE, Joshua T. Hawke, Student Member, IEEE, and Harish S. Krishnamoorthy, Student Member
AbstractWith wide-spread application of power electronic

converters in high power systems, there has been a growing
interest in system reliability analysis and fault-tolerant
capabilities. This paper presents a comprehensive review of
conventional fault-tolerant techniques regarding power
electronic converters in case of power semiconductor device
failures. These techniques can be classified into four categories
based on the type of hardware redundancy unit: switch-level, leglevel, module-level and system-level. Also, various fault-tolerant
methods are assessed according to cost, complexity, performance,
etc. The intent of this review is to provide a detailed picture
regarding the current landscape of research in power electronic
fault-handling mechanisms.
Index TermsFault-tolerance, power electronic converters,
system reliability, post-fault operation.
I. INTRODUCTION
ower electronic convertersfeaturing higher efficiency
and higher power densityplay an increasingly important
role in adjustable-speed drives, utility interface of renewable
energy resources, flexible high-voltage direct current (HVDC)
transmission systems, and electric or hybrid electric vehicles
(HEVs) [1]-[3]. However, field experiences have
demonstrated that electrolytic capacitors and power switching
devices in power electronics converters, such as insulated gate
bipolar transistors (IGBTs) and metal-oxide field-effect
transistors (MOSFETs), are the most vulnerable components,
which challenge the reliability of the system [4]-[5]. Since
most of the power electronic converters do not exhibit
redundancy, any fault that occurs to components or
subsystems will result in interruption of the operation. In
certain applications related to personal safety, such as electric
drives for vehicles, this unexpected system shutdown will
place passengers into areas of potential risks [6].
This work is supported by the National High Technology Research and

Development Program of China 863 Program (2012AA053601,
2012AA053602, and 2012AA053603), the National Natural Science
Foundation of China (51277163), the Specialized Research Fund for the
Doctoral Program of Higher Education of China (20120101130010), and
Zhejiang Key Science and Technology Innovation Group Program
(2010R50021).
W. Zhang, D. Xu and H. Li are with the Institute of Power Electronics,
College of Electrical Engineering, Zhejiang University, Hangzhou 310027,
China. (e-mail: xdh@cee.zju.edu.cn)
P. Enjeti, J. Hawke and H. Krishnamoorthy are with Department of
Electrical & Computer Engineering, Texas A&M University, Hangzhou
College Station, Texas, 77840, USA. (e-mail: enjeti@tamu.edu)
Digital Object Identifier
In critical applications, such as military, financial markets and

hospitals, system interruptions could lead to immeasurable
economic losses [5], [7]. Therefore, discussion of faulttolerant power systems and enhanced system reliability
attracts much attention among researchers.
References [8]-[9] define some metrics to evaluate power
electronic system reliability, such as failure rate, mean time
between failures (MTBF), mean time to repair (MTTR), and
availability. Since a precise mathematical model is helpful
when verifying whether a fault-tolerant design meets expected
requirements, empirical-based model and physics-of-failure
model are employed while designing components of power
electronics systems [10]. With regard to system-level
configurations, the markov model is widely adopted [11].
For a fault-tolerant system, the fault diagnosis is the first
step once a fault occurs [12]. An accurate and timely detection
and protection can prevent fault propagations and catastrophic
consequences. The fault-tolerant operation, consisting of faultisolation and fault-reconfiguration is the next counter-measure,
which is always based on hardware redundancy design and
corresponding fault-tolerant control. As for fault-tolerant
operations, numerous solutions are reported by past literatures.
Based on the type of the hardware redundancy, these methods
are classified into four categories: 1) switch-level, 2) leg-level,
3) module-level and 4) system-level. For the first solution,
various fault-tolerant methods, such as inherently redundant
switching states [18]-[32], DC-bus midpoint connection [33][57] and redundant parallel or series switches installation [58][63], are investigated extensively. In leg-level solutions, the
main approach is to add redundant legs in parallel or series
connection to main legs [64]-[74]. Among them, the redundant
parallel leg solution achieves a better compromise between the
system cost and performance, thus becoming a hot area of
fault-tolerant research. Cascade multilevel converters (CMCs)
and modular multilevel converters (MMCs) are typical
topologies with module-level redundancy. Three scenarios
including neutral-shift, DC-bus voltage reconfiguration and
redundant modules installation are employed [75]-[88]. In
industry fields, the parallel redundancy converter approach is
widely employed due to higher reliability. Among the above
approaches, some system performances during post-fault are
degraded. Therefore, these methods can only be applied in
fields where a limp-home function is allowable after faults.
Additionally, it is necessary to explore more practical
modified topologies endowed with a full redundant capability,
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and therefore can potentially be applied within the industry in

the future.
Due to the growing importance and extensive research
surrounding the fault tolerance of power converters, the
authors feel that this is the right time to put forth a systematic
perspective on the status of the fault-tolerant research.
Altogether, this paper presents a comprehensive overview of
the fault-tolerant techniques in the case of power
semiconductor failures. Section II introduces general
classification of conventional fault-tolerant techniques and the
relevant assessment criteria. Several existing methods for the
hardware fault-isolation are presented and compared in
Section III. Section IV summarizes switch-level hardware

reconfigurations. Leg-level and module-level for hardware
reconfigurations are presented in Section V and Section VI,
respectively. Section VII introduces system-level solutions.
The concluding remarks and discussion are summarized in
Section VIII.
II. GENERAL CLASSIFICATION
The prevailing fault-tolerant methods for power electronics
converters are presented in Fig.1, which are categorized into
switch-level, leg-level, module-level and system-level.
Fault-Tolerant Methods for Power Electronics Converters
Switch-Level
Leg-Level
Redundant
DC-Bus Midpoint Redundant Series Redundant Series
Switching States
Connection
or Parallel Switch or Parallel Leg
Module-Level
Neutral-Shift
System-Level
Dc-Bus Voltage Redundant Series Redundant Series or

Regulation
or Parallel Module Parallel Converter
Fig. 1. State-of-the-art fault-tolerant methodology chart
Most of multilevel converters are considered switch-level

redundant circuits, since some switches are added compared to
basic 2-level converters. Consequently, an inherent
redundancy that multiple switching combinations of threephase correspond to the same three-phase outputs is formed.
Therefore, the fault-tolerance can be realized by exploring
these inherently redundant switching states [18]-[32]. The
second solution for the switch-level reconfiguration is to
connect the faulty converter to the midpoint of the DC-bus via
additional auxiliary switches [33]-[57]. The two-phase control
are normally applied in the remaining two phases to maintain
balanced outputs during post-fault operations. Another
scenario comes from the use of redundant switches in parallel
or series connection to main switches [58]-[63]. Based on
whether or not the redundant switch is operated in normal
conditions, two schemes are developed: online strategy and
offline strategy.
As for leg-level scenarios, a powerful solution currently in
use is to apply extra legs in parallel with main legs. Since the
redundant leg can substitute the damaged leg, the normal
behavior of the converter can be guaranteed after faults [64][70]. Alternately, the redundant legs can be in series
connection to the main legs for fault reconfigurations [71][74]. Similar to switch-level solutions, the redundant leg can
be designed for online mode or offline mode based on
different applications.
Module-level solutions are primarily for CMCs or MMCs.
The first strategy is neutral-shift method. After faults, the
number of the operative modules in each phase is unequal; the
phase shifts among three phase-voltage references is adjusted
to maintain balanced line-to-line voltages [75]-[82]. Another
technique is the DC-bus voltage configuration method, which
attempts to sustain an unchanged output voltage by raising the
input voltage. The increased voltage can be normally shared
by three phases via combining the neutral-shift scenario [83][86]. A more powerful solution currently in use is to apply
extra modules in series with other modules. The redundant

module substitutes the damaged one, maintaining the original
outputs [87]-[88]. Similarly, the redundant module can be
designed for online- or offline-mode based on applications.
More costly techniques, such as using an extra converter
reserved for system fault-reconfigurations have been
employed in industrial applications. Two common topologies
are the cascaded redundant converter and the parallel
redundant converter [89]-[95]. The additional converter can be
operated in either cold or hot backup mode.
In order to assess the above techniques, the comparison
criteria used in this paper are presented as follows.
1) Cost. The cost will increase if extra fuses or devices are
added for system fault-tolerance. Furthermore, semiconductor
devices in some basic topologies may need to be overdesigned
for fault-tolerant operation, which increases costs as well.
2) Output performance. The output capability should be
evaluated first. Also, other factors, such as the total harmonic
distortion (THD) of output voltages or currents, system
efficiency, and dynamic response should be taken into
consideration as well. A topology with full fault-tolerance
should behave after faults identically to normal operations.
3) Reliability. How many types of faults are covered and
how much reliability is enhanced are also important metrics
used to evaluate overall performance of fault-tolerant topology.
III. FAULT ISOLATION TECHNIQUES
For most of fault-tolerant solutions, the physical faultisolation is the first step, especially in the case of short-circuit
fault. The fault-isolation unit forces damaged switches or
poles to be electrically isolated from the system first which
can eliminate its influence over the system behavior. Then the
post-fault reconfiguration can be activated. The following
requirements should be taken into consideration for the design:
1) Rapidity. 2) Fault coverage. 3) Precision. The excellent
isolation scheme should only isolate damaged components,
while leaving all the healthy switches operational. 4) Impact

on the normal operation of the system. 5) Complexity and cost.
Fig. 2 shows five typical isolation schemes. Although these
schemes are based on two-level circuits, the concept can be
generally applied to other topologies as well.
Strategy 1 is shown in Fig. 2(a) [13]. This method can
disconnect either a single switch or entire phase-leg from the
system. For instance, S2 isolation is implemented by triggering
the semiconductor-controlled rectifier (SCR) T1 which creates
a shoot-through loop across the DC-bus and blows the fuse F2.
Note that the size of auxiliary capacitors is critical to the
duration of the fault-isolation process. The main disadvantages
of this strategy are as follows. 1) The presence of the fuses in
the DC-bus side will increase the parasitic inductance. 2) The
component count is relatively high, increasing the system cost.
C1
F1
F1
F1
S1
T1
S1
S1
T1
S2
T2
TN
S1
R1
S2
(a)
S2
S2
S2
C2
S1
F1
F2
F2
F2
(b)
(c)
(d)
(e)
Fig. 2. Five typical fault-isolation schemes (a) Strategy1 (b) Strategy 2 (c)
Strategy 3 (d) Strategy 4 (e) Strategy 5
Strategy 2a simplified version of Strategy 1has only

two fuses and one triode for alternating current (TRIAC)
incorporated and is shown in Fig. 2(b) [14]. Here, in the case
of S1 short-circuit, S2 is blocked and TN is triggered to clear the
fuse F1. However, this strategy still has the drawback of
increased parasitic inductances.
Strategy 3 is presented in Fig. 2(c). In order to eliminate the
parasitic inductance due to the added fuses, the fuses are
removed to the output of each phase [15]. Since the fuses are
in series with output filter inductors, the effect of parasitic
inductances is not important. When a short-circuit fault occurs
in one of the switches, the complementary switch is blocked
and the TRIAC is triggered on. Consequently, the fuse can be
cleared. Still, the main drawbacks are as follows. 1) It cannot
handle the fault where two switches in one pole fail
simultaneously. 2) This approach isolates the whole leg, even
if just one switch fails. That means, as long as one switch fails,
the healthy switch in the same leg cannot continue operating.
Strategy 4 is shown in Fig. 2(d). Here, the fuse in strategy 3
is replaced by a controllable switch [16]-[17]. The switch can
be relays, TRIACs or bi-IGBTs. Compared to fuses, these
switches increase costs and losses. Also, different switches
have special characteristics to accommodate. For instance, the
time response of relays is slow. The turn-off process of
TRIACs is uncontrollable and the overload capability of
IGBTs is low [17]. Additionally, this approach still cannot
handle the fault of simultaneous two-switch failure.
Strategy 5 is presented in Fig. 2(e). Recently, new power
switches with high short-circuit capabilities and fast fuses
have been developed. With the help of such power devices, it
is possible to implement a simple isolation [14]. When a short
circuit occurs in either one of the switches, the complementary
switch is turned on to cause a shoot-though loop, blowing out
the fuses. Still, the parasitic inductances of fuses exist.
IV. FAULT-RECONFIGURATIONS: SWITCH-LEVEL

After the fault-isolation, fault reconfiguration is activated.
This process relies on hardware redundancy design and
corresponding fault-tolerant control. This section introduces
three types of switch-level hardware redundancies and
associated control strategies.
A.
Redundant Switching States
Multilevel converters are in essence one type of switchlevel redundant circuits, where some switches are added into
basic 2-level converters. Due to these additional switches, the
redundancy of output switching states is created. Therefore,
the fault-tolerance can be realized by exploring these
redundant switching states. Note that the method is normally
implemented based on the space-vector modulation (SVM)
algorithm [18]-[19].
Li et al. proposed a control scheme of utilizing the voltage
vector redundancy for neutral-point clamped (NPC) inverters
[20]. Assuming that Sa1 fails in short-circuit, phase-A cannot
output zero-level due to the shoot-though path as shown in Fig.
3(a). As a result, the voltage vectors involving zero-level of
phase-A are invalid as shown in Fig. 3(b). The converter is
still able to output a full voltage with the help of redundant
vectors. However, the other issues are introduced [21].
Specifically, Sa2 has to withstand the total dc-bus voltage,
which leads to the oversized design of the semiconductors. A
similar approach is applied in other 3-level topologies, like Ttype [22], active NPC [23], etc. It is worth mentioning that,
when the middle switches fail in open-circuit in T-type threelevel converters, it can be degraded into two-level without any
loss of output voltage.
opn
npn
Sa1
Sb1
Da5
Sa2
Sa3
Sa4
Db5
Sb2
Da6
Sb3
Sb4
(a)
ppn
Sc1
Db6
npo
Dc5
Sc2
Sc3
Sc4
A
B
C
Dc6
npp
opo
non
ppo
oon
opp
noo
nop
ppp
ooo
nnn
oop
nno
pon
pop
ono
onp
nnp
pnn
poo
onn
pno
pnp
(b)
Fig. 3. 3-level neutral-point clamped topology (a) Sa1 short-circuit failure (b)
Voltage vectors diagram after the failure
The fault-tolerant operation based on the vector redundancy

is also employed in CMCs [24]-[25]. When some switches in
the circuit fail, the corresponding space vectors become
invalid and the output voltage is decreased. In [26], the faulty
cells also participate in the operation and contribute output
levels depending on specific faulty switches. In addition, in
order to solve the computational complexity with the increase
of number of modules, the space vectors are defined in a 60
g-h coordinate system [27]. Based on the 60g-h coordinate
system, a pulse width modulation (PWM) pattern called largesmall alternation (LSA) is proposed [28]-[30]. Compared to
other methods, the LSA modulation results in output line-toline voltages with the lowest THD in the post-fault [28].
Note that this inherent redundancy exists in not only 3phase switching combinations, but also switching states of a
single phase in some converters. For instance, in multilevel
active clamped (MAC) converters, when the output is 1Vdc,
two conduction paths can be selected as shown in Fig. 4(a),
which can be utilized for redundancy [31]. However, it
implies an increase of the blocking voltage of some devices in
some fault conditions. For instance, Sn31 has to withstand 2Vdc
when the output level is 3Vdc in the case of Sn21 short-circuit
(see Fig. 4(b)). Alternatively, a scheme is proposed [31] to
maintain the original device blocking voltage but at the
expense of some output levels.
3Vdc
3Vdc
Sp31
2Vdc
Sp21
Sp22
Sn32
Sn22
1Vdc
Sp13
Sp12
2Vdc
Sp11
Sn31
1Vdc
Sn21
Sn33
Sp21
Sp22
Sn32
Sp11
Sn22
Sp12
Sn31
Sp13
2Vdc
Sn21
#5
Sa1
Sp21
Sn43
Sp32
Sp11
Sn42
Sp22
Sn33
Sn41
Sp12
Sn32
Sp23
Sn31
Sp13
Sn22
Sn21
Sn14
Sn11
(a)
#5
Sp41
Sn44
Sp21
Sn43
Sp32
Sp11
Sn42
Sp22
Sn33
Sn41
Sp12
Sn32
Sp23
Sn31
Sp13
Sn22
Sn21
Sn14
+
V
#3
+
V
#2
Sa2
+
V
#1
Sa1
Sp31
#4
+
V
#4
+
V
-
Sb1
Sc1
Sa2
Sb2
Sc2
Sa1
Sb1
Sc1
Sa2
Sb2
Sc2
TN
O
C
C
Sb2
Sc2
TN
(b)
(c)
#3
The first fault-tolerant topology shown in Fig. 6(a) forces

the faulty phase to connect to the midpoint of the DC-link via
the additional TRIACs [15], [34]. After faults, the
reconfigured system is similar to the structure where only four
switches are used to drive a three-phase machine [35]. Note
that since the inverter is still capable of providing the full
rated current, the torque production will be preserved.
Nevertheless, the main disadvantages are as follows.
1) The maximum balanced line-to-line output voltage in
post-fault operations is reduced to half of its nominal value.
2) This approach is only applied in situations where the
midpoint of DC-link capacitors can be accessed.
3) Since the phase-current flows into the midpoint of the
DC-bus, oversized DC-bus capacitors are mandatory.
The second method connects the neutral-point of the motor
to the DC-bus midpoint via the incorporated TRIAC TN as
shown in Fig. 6 (b) [36]-[37]. Note that only one TRIAC is
added for the fault-tolerance. In case of loss of one phase (e.g.
phase-A) as shown in Fig. 7(a), the magnitude of phase-B and
phase-C currents is increased by and the phase shift
between these two is regulated to 60in post-fault operations
as shown in Fig. 7(b) [6]. Note that the modified control
strategy leads to a zero-sequence current. Therefore, TN needs
to be turned on after faults to flow the neutral current.
+
V
-
Sa1
#2
Sa2
Sa1
(a)
In order to further improve the fault-tolerance, some

auxiliary switches are added, which increase the number of
redundant switching states. Fig. 5(a) presents a modified 5level MAC topology [31], where two auxiliary devices are
added at terminals #2 and #4. A similar approach is applied in
general multilevel converters proposed by Chen et al [32].
This method can tolerate any single device failure without loss
of any output-voltage levels. Nevertheless, the main
disadvantages lie in these aspects. 1) An increased number of
conduction devices lead to higher conduction losses. 2) The
blocking voltage of some devices is unavoidably doubled. For
instance, when Sp13 fails in short-circuit, Sp22 has to withstand
2V shown in Fig. 5(b). 3) The modified architecture loses the
features of good symmetry compared to the original circuit.
Sn44
Sc1
Fig. 6. Switch-level fault-tolerant motor drives (a) Topology 1 (b) Topology 2

(c) Topology 3
(b)
+
V
-
Sb1
Ta
Tb
Tc
Sa2
Fig. 4.Multilevel active clamped topology (a) Output is 1Vdc (b) Sn31
overvoltage when Sn21 is short-circuit
Sp31
Sa1
Sn11
0Vdc
(a)
Sp41
DC-Bus Midpoint Connection
As for three-phase converters, if one phase fails, the

remaining two phases can maintain continuous operations.
Three typical fault-tolerant topologies with additional switches
employed in motor applications are presented in Fig. 6 [33].
O
Sn11
0Vdc
B.
Sp31
Sn33
1) The performance in post-fault operations is degraded.

Either the output voltage is reduced, or the blocking voltage of
devices is increased, or suboptimal output THD occurs.
2) The fault coverage of this approach is limited.
3) The approach utilizing 3-phase redundant vectors can
only be employed in a three-phase three-wire system.
+
V
-
Sn11
(b)
Sb1
Sc1
Ic
ia
ib
ic
3 pu
A
B vN
Ic
30
In summary, the main disadvantages of redundant switching

states approach are as follows.
Ia
1pu
C Post-Fault
30
#1
Fig. 5. Fault-tolerant multilevel active clamped topology (a) Normal

Operation (b) Output is 0V in the case of Sp13 short-circuit failure
Pre-Fault
Sa2
Sb2
Sc2
3 pu
Ib
Ib
TN
(a)
(b)
Fig. 7. (a) Phase-A failure (b) Phasor diagram in the pre- and post-fault
Nevertheless, the drawbacks of this approach can be

identified as follows.
1) The oversized semiconductors are necessitated.
2) The maximum speed of the machine in post-fault is

reduced to 0.5 of its nominal value because the equivalent
line-to-line voltages are decreased to 0.5pu.
3) This approach can only be applied when the DC-bus
midpoint and the motor neutral-point can both be accessed.
4) The neutral-current is significantly increased, which
necessitates oversized DC-bus capacitors.
The third method connects the neutral-point of a motor to
an additional fourth leg [38]-[39]. As shown in Fig. 6 (c), an
extra leg and a TRIAC are incorporated. It is worth
mentioning that the fourth pole can be permanently connected
to the converter even in normal operations without TRIACs
[38]-[39]. Compared to the previous two solutions, this
topology yields the following good features.
1) The system is free of the DC-bus midpoint balancing
problems and minimum capacitance sizing.
2) The line-to-line voltage can be increased to 1pu
compared to previous methods.
A similar principle can be applied in five-phase motors as
shown in Fig. 8. However the solution for generating the
unchanged rotating magneto motive force (MMF) is not
unique. Normally, two strategies are employed [40]-[42], (see
Fig. 8(b)-(c)). In the first scheme, there is an attempt to
generate the unchanged rotating MMF with the minimum
possible current magnitude of the remaining healthy phases.
All the current references are increased by 1.314 times and
shifted by 18 degrees as shown in Fig. 8(b). However this
solution exhibits a zero-sequence current component. In the
second strategy, the current references of the healthy phase are
modified to achieve undisturbed MMF and eliminate zerosequence current components. In this case only two current
reference vectors are rotated by 36 degree (see Fig. 8(c)).
However, the magnitude of the remaining phase has to
increase by 1.38 times to achieve the unchanged MMF. A
similar approach can be applied in other multi-phase motors,
like six-phase [43], four-phase [44], etc.
Sa1
Sb1
Sc1
Sd1
Se1
ib
ic
id
ia
ie
Sa2
Sb2
Sc2
Sd2
TN
(a)
Id
Ic
18
18
Ie
18
(b)
I d
36
18
Se2
I b
Ia
Ic
36
Ie
Ia
I b
(c)
Fig. 8. Five-phase machine (a) Phase-A failure (b) Strategy 1 in case of phaseA failure (c) Strategy 2 in case of phase-A failure
The disadvantages of this approach in motor applications

are as follows.
1) The method only can handle open-circuit failures
happening in the signal-phase or multiple phases.
2) Since the healthy phases have to withstand over-current

after faults, oversized devices are necessary. Also, the overcurrent is decreased with an increase of the phase number.
3) For a three-phase machine, a neutral connection is
necessary. If the neutral current flows into the DC-bus, it
necessitates oversized capacitors.
A similar idea can be applied in 3-phase voltage source
inverters (VSIs). As shown in Fig. 9(a), the basic idea is to
constantly force the output voltage of the faulty phase to zero
and regulate the phase-angle of the other two phase voltages,
maintaining balanced line-to-line voltages in post-fault. As
shown in Fig. 9(b), the phase angles of phase-B and -C will be
shifted by 30away from the faulty phase (phase-A) [19]. Note
that the equivalent balanced phase-voltages in post fault
conditions (vAE', vBE', vCE') are only of those in normal
conditions as shown in Fig. 9 (b).
Sa1
Sb1
VC
Sc1
VC
vA
vB
vC
30
VCE
VAE
VBE 30
Post-Fault
Sa2
Sb2
(a)
Sc2
VA
Pre-Fault
VB
VB
(b)
Fig. 9. Two-phase control in voltage source inverters (a) Phase-A failure (b)
Phasor diagram in the pre- and post-fault
Following a similar approach, TRIACs are added to 6-leg

AC-DC-AC converters [45], 5-leg converters [46], nineswitch converters [47], and matrix converters [48]-[50] for
fault-tolerance. Note that the matrix converter is treated as a
two-stage rectifier/inverter [51]-[52]. The existing modulation
techniques for the inverter stage can be used. As for multilevel
converters, an additional TRIAC TN is employed in NPC
converters to connect the output to the mid-point as shown in
Fig. 10(a) [20], [53]. An alternative scheme is the active-NPC
topology as shown in Fig. 10(b) [23], [54], which utilizes
IGBTs to replace clamped diodes, such that the output
terminal of the faulty phase can be connected to the mid-point
via S2/S5 or S3/S6. However, the output voltages in these two
approaches both are reduced after faults. In an attempt to
overcome this problem, some fast fuses and thyristors are
added as shown in Fig. 10(c) [55]-[56]. In case of a shortcircuit fault, the corresponding thyristor is triggered to clear
the associated fuse. Consequently, the faulty leg is
reconfigured into a two-level structure. However, some
semiconductors have to withstand overvoltages. A similar
approach is applied in active-NPC [55]-[56] shown in Fig.
10(d). Due to the additional switching states provided by the
extra switches S5/S6, the faulty leg is still able to achieve three
voltage levels in some fault conditions. However, the main
drawback remains the oversized semiconductors.
In additional, Ma et al. applied the two-phase control in
general multilevel converters, which combined dc-component
injection as well [57]. However, the reduced output voltage is
still the primary issue during post-fault conditions.
S5
S1
TN
S1
S2
S2
S3
S3
S4
S4
S6
T1
S1
T1
F1
S2
F1
F2
T2
S3
S4
S5
S1
S2
S6
S3
F2
S4
T2
(a)
(b)
(c)
(d)
Fig. 10.Switch-level fault-tolerant multilevel converters (a) Topology 1 (b)
Topology 2 (c) Topology 3 (d) Topology 4
C.
Redundant Parallel or Series Switches Installation
1) Redundant Parallel Switch

This approach places extra switches in parallel with the
main switches. Based on whether or not the redundant switch
is operated in normal conditions, this method is implemented
in two ways: offline scheme and online scheme.
In the offline scheme, the redundant switch is not operated
in normal conditions. When a fault occurs, the redundant
switches are activated to replace faulty switches. As shown in
Fig. 11 (a), the traditional MC is accompanied by a
bidirectional switch and a series of relays [58]. The redundant
switch can replace any of the switches via selecting relays. In
order to increase the system availability, more redundant
switches can be added [58]. A similar approach is introduced
into two-level inverters [59]. Thyristors can replace relays to
reduce the transition time due to their short turn-on time.
SR11
SR
R1 R2 R3
R4
SaU
R5
SaV
SR12
R6
2) In the offline scheme, one redundant unit is shared by

multiple main switches, which can reduce the system cost.
However, more linking switches are introduced.
3) In the offline scheme, the linking switches increase the
conduction loss in post-fault. In the online scheme, the parallel
switches can reduce conduction losses in normal conditions.
2) Redundant Series Switch
The two-level voltage source converter with IGBTs directly
in series is widely used in flexible HVDC transmissions [60].
The redundant devices are connected in series with main
switches for short-circuit failures as shown in Fig. 12(a) [61].
The overall conduction losses are doubled in normal
operations. Also, the voltage sharing issue among the series
devices has to be addressed. In addition, some switches have
to withstand overvoltages after short-circuit failures. In order
to further handle open-circuit failures, this topology is
modified by adding parallel thyristors as shown in Fig. 12(b)
[62]. However, this scenario is at the expense of higher costs.
Another topology providing the series redundancy is flying
capacitor multilevel converters (FCMCs). As shown in Fig. 12
(c), an fault-tolerant design for three-cell 4-level FCMC is
proposed in [62]-[63]. When a single-switch fault occurs, the
faulty switch and its counterpart are bypassed. The
corresponding capacitor is isolated from the system or
constantly connected in parallel with another capacitor.
However, the primary disadvantages are the following.
1) Some switches need to withstand the full DC-link
voltage after failures.
2) The series switches (K1, K2) experience on-state losses
during normal operations.
SR13
SaW
SR14
SbU
SbV
SbW
ScV
SR1
S1
S1
K2
ScW
SR22
Relay
S2
SR21
(a)
S1
K1
SR24
SR23
ScU
SR1
+
+
3V - 2V-
+
V
-
S2
S3
S4
S2
S5
(b)
SR2
Fig. 11. Redundant parallel switch (a) Offline-switch scheme (b) Onlineswitch scheme
Unlike the offline scheme, the redundant switch in the

online scheme participates in normal operations. Reference
[31] connects two devices in parallel for MAC converters
shown in Fig. 11(b). Note that the redundant switches are only
placed in the highest-level and lowest-level paths because the
redundancy of the middle levels is achieved by the redundant
switching states discussed above. The parallel devices can
reduce the overall conduction losses in normal operations.
However, the current sharing issue has to be addressed.
To sum up, the main features of the redundant parallel
switch approach are as follow.
1) Relays and SCRs are normally selected as linking
switches. Compared to relays, SCRs have faster transient time,
potentially shortening the system reconfiguration process.
(a)
SR2
(b)
S6
(c)
Fig. 12. Redundant series switch (a) Topology I (b) Topology II (c) Topology
III
V. FAULT-RECONFIGURATIONS: LEG-LEVEL
In this section, two types of leg-level hardware
redundancies and associated control strategies are introduced,
which are redundant parallel leg and redundant series leg.
A.
Redundant Parallel Leg
This approach is implemented via adding a parallel

redundant leg. Depending on whether or not the redundant
parallel leg functions in pre-fault, there are two schemes:
offline leg scheme and online leg scheme.
Fig. 13(a) presents a solution based on an offline parallel
leg [64]. Since the number of the redundant leg is only one,
three main legs share it together which reduces the entire cost.
Meanwhile, three TRIACs, e.g. TA~TC, are added as linking

switches. Before faults, the additional leg is inactive. When a
fault occurs, the spare leg replaces the faulty leg. Note that the
topology can only cover the fault happening in a single phase.
A similar approach is applied in doubly fed induction
generator (DFIG) systems [65] and HEVs [16], [66]. It is
observed that multiple converters share one redundant leg to
reduce system costs. In order to increase the system
availability, the number of the redundant legs is increased up
to three [61] as shown in Fig. 13(b). Since relays have a
considerable amount of delay, they can be replaced with bidirectional switches to shorten the dynamic process [67].
Sa1
Sb1
Sc1
SR1
Sa2
Sb2
Sc2
SR2
Sa1
SRa1
Sb1
SRb1
Sc1
SRc1
Sa2
SRa2
Sb2
SRb2
Sc2
SRc2
TA
TB
TC
TA
TB
TC
4) The backup leg can operate in online or offline mode.

The loss is higher in the online mode due to the fact that the
additional leg is operating. However, the online backup leg
can help improve the output quality in normal conditions.
B.
Redundant Series Leg
The series redundancy leg is widely applied in 3-phase

motor drives [71] as shown in Fig. 15(a). Note that the voltage
space vectors are the same as 3-level inverters [72]. In case of
short- or open-circuit failures, the faulty leg stops working,
while the two remaining phases continue operating to maintain
the original flux. However, the output voltage is reduced
during post-fault operations. Therefore, an alternative
configuration using the same number of switches with two
isolated and unequal dc-link voltages (Vdc1,Vdc2) is reported as
shown in Fig. 15(b) [73]-[74]. The output capability of the
system can be increased to some extended. However, the
oversized semiconductors are still necessitated.
Sa1
Sa2
Sb2
Sb1
Ta
C2
SR3
SR4
(a)
Sa3
S2
C2
Sa1
SR2
Sa2
Fa
Ta
SR3
Sa3
SR4
Sa4
Phase C
Sa2
Fa
SR1
Phase B
Phase C
SR2
SR5 SR6
Phase B
C1
C1
Sa4
A
(b)
Fig. 14. Online parallel redundancy leg topologies (a) Flying capacitor
redundant leg (b) Inductor redundant leg
To sum up, the principle features of the parallel leg

approach are identified as follow.
1) The number of the redundant legs can be from 1 to 3.
The number is a balance of offsetting the improved reliability
with the increased costs.
2) In the offline scheme, the linking switches are required.
The added linking switches increase the conduction loss in
post-faults. Therefore, it is significant to apply semiconductors
with a lower on-state resistance as the linking switches.
3) The topology of the redundant legs could be the same, or
different, as that of legs in the original circuit. Hence, it can
select its own topology based on the specific requirements.
Sb1
Sa3
Sc1
Sb3
Sc3
Vdc
Vdc2
Vdc1
Sa3
Sa4
Sb4
Sb3
B
In the online leg scheme, the redundant leg operates even in

normal conditions to improve the system behavior. Two
modified topologies based on the 3-level NPC topology are
presented in Fig. 14 [68]-[70]. Taking the circuit in Fig. 14(a)
as an example, the fourth leg adopts a flying capacitor
topology different from the main legs. In normal conditions,
this additional leg provides a stiff neutral-point voltage. When
a fault occurs (e.g. phase-A), the fuses Fa and F are blown out
first. Then, SR5, SR6 and Ta are activated. Consequently, the
faulty leg is substituted by the fourth leg and the system is
reconfigured as a standard NPC converter. A similar principle
can be applied in the circuit in Fig. 14(b).
Sa1
Sc2
Sa1
(a)
(b)
Fig. 13. Offline parallel redundancy leg solutions (a) One redundant leg (b)
Three redundant legs
SR1
Sc1
Sc3
Sc4
Sa2
Sb2
Sa4
Sc2
Sb4
Sc4
(a)
(b)
Fig. 15. Series redundancy leg solutions (a) Topology 1 (b) Topology 2
VI. FAULT-RECONFIGURATION: MODULE-LEVEL

CMCs and MMCs are typical circuits with module-level
redundancy. If some modules fail, the other modules
implement the fault-tolerant reconfiguration to maintain
continuous operations. The main approaches are neutral-shift,
dc-bus regulation and redundant module installation.
A.
Neutral-Shift
After faults, an unequal number of modules are applied in

three phases. Therefore, this method is attempted to modify
phase shifts among phase-voltage references to maintain
balanced line-to-line voltages in post-fault. It functions as
though the equivalent neutral-point is shifted after faults, so it
is called neutral-shift (NS) method.
Taking the 5-module 11-level CMC as an example, when a
fault occurs with two faulty modules in phase-b and one faulty
module in phase-c, the unbalanced line-to-line voltages are
applied. To keep balanced line-to-line voltages, the simplest
solution is to bypass an equal number of modules per phase as
shown in Fig. 16(a) [75]. However, this approach results in
very low output voltages. Therefore, [76] introduces the NS
method to maximize the line-to-line voltages, where the
angles of the phase voltages are recalculated after faults. The
phase-shift angles for different faults [77] are
2
2
2
2
2
2
Va Vb 2VaVb cos Vb Vc 2VbVc cos Va Vc 2VaVc cos
(1)
360
where Va, Vb, Vc are the magnitudes of three phase voltages,

and , , are the angles between every two phase-voltages.
Va
Va
a5
a4
a3
a3
6.67
c2
=
113
c3
6.67
a1
a1
c1 b1
c1 b1 b2 b3
b4 b5 Vb
c2 =150
b
=120 2 b3
c3
c4
b4
6.67
5.2
b5 Vb Vc c5
Vc c5
5.2
a2
97
=
5.2
120
=
=
120
a2
In summary, the NS method is easy to be implemented.

Nevertheless, the primary disadvantages are as follows.
1) This approach cannot be employed in the application of
three-phase 4-wire systems.
2) The full voltage in normal situations still cannot be
achieved during post-fault conditions.
3) In post-fault conditions, the load power factor not only
depends on the load characteristic, but also on how much the
neutral-point is shifted.
(a)
(b)
Fig. 16. (a) Bypass equal number of modules (b) Neutral-shift approach
Based on (1), the output voltages based on the NS method

are shown in Fig. 16(b). Compared to the method in Fig. 16(a),
the output line-to-line voltages are increased by 28%.
However,
1) Since (1) is nonlinear and the number of possible faults is
limited, the use of a pre-calculated table is recommended to
avoid complex online calculations [19];
2) According to [77], (1) may have multiple solutions for
some fault conditions. Also it does not always result in the
maximum possible value of the output line-to-line voltages.
To overcome these problems, an extension of NS method is
proposed [77], where the angle between the two voltages with
the lowest amplitude values is forced to be 180, and both the
magnitude and the phase of the other phase are adjusted to
achieve maximum output voltages as shown in Fig. 17(a). Fig.
17(b) and (c) present an example with 3 faulty modules in
phase-b and 2 faulty modules in phase-c with two methods.
Compared to the traditional NS method, the extension of the
NS method can increase the output voltage by 15%.
Va
a5
a5
Va
a4
a4
4.36
4.36
a3
Vc
Vc
Vb
c2
4.36
a1
60
c1 60
a3
a2
Va
b1
b2
b3
Vc
a2
Vb
a1
c2
c196
84
b1
b2
b3
Vb
(a)
(b)
(c)
Fig. 17. (a) Extension of neutral-shift method (b) Result of traditional neutralshift method (c) Result of extension of neutral-shift method
The additional limitations of the traditional NS method are

detailed in [78], which affects the output power factor (PF) of
the converter. Therefore, in some types of faults, PF angles
could be greater than 90even if the load is not an active load.
In this case, the inverter will absorb the power instead of
supplying the load, which may lead to its destruction.
Reference [79] proposed a variant method combining the
merit of the neutral-shift and the 3rd zero-sequence injection.
After the occurrence of a fault, the converter can be analyzed
as two separate systems. The first one can operate as a threephase balanced system with 3rd harmonics injection to increase
the modulation index by 1.15 times, and the second one can
operate with the NS approach to obtain balanced three-phase
voltages. Fig. 19 illustrates an example with a phase-b module
failure. The resultant modulation index can reach 0.83pu.
Zero-Sequence Injection
Va(1)
Neutral-Shift
Va
a3
a2
120
c3
c2
Vc
2.3
a1
c1
b1
b2
120
120 120
120
2.3
2.3
120
b3
Vc(1)
Va(1)
Va(2) 1
60 =
Vc(2) 1
120 120
Vb(1)
120
Vc(1)
Vb(1)
Vb
(a)
Va(2)
(b)
Vc(2)
Fig. 18. (a) One module in phase-b failure (b) Vector diagram for post-fault
Since the injected zero-sequence component is all

fundamental frequency, the NS method limits the range of
load power factor [82]. Therefore, some alternative zerosequence component injection methods with non-fundamental
frequency based on the carrier-PWM are proposed to
eliminate the adverse effect of the NS method [80]-[81].
Furthermore, Carnielutti et al. analyzed a formal
mathematical derivation to establish a theoretical background
[82]. For a given fault condition, the optimum zero-sequence
components for the output line-to-line voltages are obtained.
However, the process of obtaining the zero-sequence
component in this method is relatively complex.
B.
DC-Bus Voltage Reconfiguration
It is noted that a common drawback of the previous method

is the reduced output voltage during post-fault operations.
Therefore, in an attempt to sustain an unchanged output
voltage, an alternative approach is to increase the input DCbus voltage. The DC-bus voltage reconfiguration is generally
categorized by whether the overvoltage is withstood only by
the faulty phase or shared among three phases.
In applications of static compensators [83]-[84], H-bridge
modules in a CMC are used as active rectifiers. When the
faults occur, the DC-link voltages of the remaining modules in
the faulty phases are increased to keep the total voltage
unchanged. For example, in the case of the fault as in Fig. 19
(a), the voltage stress on remaining semiconductor devices is
increased by 200% (shown in Fig. 19 (b)).
Va
a3
Va
a3
a2
3.61
a2
5.19
a1
5.19
120
120 120
c3
Vc
c2
c1
b1
120
3.61
(a)
a1
b2
b3 Vb Vc c2
a1
5.19
120
5.19
Va
a1
a1
14080
5 b1
b1
3 120 b2 b V Vc c2 .3
b
1
3
5.19
(b)
5.19
(c)
5.19
b2
b3 Vb
Fig. 19. Dc-bus voltage reconfiguration (a) Fault occurrence (b) Strategy 1 (c)
Strategy 2
Unlike the previous method, the approach in [84]-[85]

introduces a neutral shift, sharing the increased voltage burden
equally among all healthy modules of three phases. As shown
in Fig. 19 (c), the DC-link voltage of the remaining modules is

only increased by 35% with this method.
Although the output voltage can be sustained at same level
as that in the pre-fault condition, the principle drawbacks of
the DC-bus voltage reconfiguration still exist as follows.
1) The increased DC-bus voltage can expose a higher
voltage stress on the devices, necessitating oversized design.
2) The combination of the DC-bus reconfiguration and
neutral-shift can only be applied in three-phase 3-wire systems.
Moreover, another post-fault reconfiguration to maintain
output voltage is realized by regulating the output transformer
turn ratio [86]. This reconfiguration method is based on a
multi-coil transformer and a set of bidirectional valves for the
system fault-tolerance. However, the added hardware
increases the system costs greatly.
C.
Redundant Modules Installation
For CMCs, redundant modules are added in series with the

basic topology as shown in Fig. 20(a). Normally, the
redundant modules are inactive. When any module has a fault,
it will be isolated by setting the bypass switch T in the 3-4
position. Subsequently, the redundant module starts to replace
the faulty module and reestablish the normal operation. The
bypass switches can be simplified by applying the failure
characteristics of semiconductors. In contrast, in [83], the
redundant modules are active in normal operations. Therefore,
the output quality is improved compared to the previous
method. However, the conduction losses are relatively higher.
The fault-tolerant control is shown in Fig. 20(b). It can be seen
that the output voltage amplitude of the each cell in faulty
phase is increased after faults. A similar approach can be
applied in MMC [87]-[88], shown in Fig. 20(c). The
redundant modules adopt the online mode, which can reduce
the transition time and the charge time of redundant modules.
Redundant Module
A1
A2
AN
AR
B1
B2
BN
BR
C1
C2
CN
S1
3 4
S2
1 2
S3
Redundant
Modules
M_Bp 1
M_Cp 1
M_Ap 2
M_Bp 2
M_Cp 2
M_Ap N
M_Bp N
A
(N+1)vosin(t+120)
Voltage
Controller
(N+1)vosin(t-120)
1/NC
1/NB
M_An N
M_Bn N
M_Cn N
(N+1)vosin(t)
Recalculate
NA, NB, NC
NA, NB and NC are the numbers

of operative cells in each phase
PWM A1
PWM B1
PWM C1
PWM AN
PWM BN
PWM CN
PWM AR
PWM BR
PWM CR
(b)
-Vdc
Bypass
Faulty Cells
1/NA
FaultTolerant
Controller
M_Cp N
S4
(a)
M_An 2
M_Bn 2
M_Cn 2
M_An 1
M_Bn 1
M_Cn 1
Redundant
Modules
Redundant
Modules
Redundant
Modules
Sa11
Sb11
Sc11
Sa11
Sb11
#1 Group
Sc11
i1a
v1a
C
Sa12
Sb12
Sc12
Sa21
Sb21
Sc21
Sa22
Sb22
Sc22
Sa12
AC
Motor
Sa21
Sb12
Sc12
Sb21
Sc21
#2 Group
i2a
Ta
Tb
Tc
v2a
Sa22
Sb22
Ta1
Tb1
Tc1
Sc22
Ta2
Tb2
Tc2
(a)
Normal
#1 group failure
* =P2a
* =50%Poa
* =100%Poa
P1a
P2a
* =50%Qoa Q2a
* =100%Qoa
* =Q2a
Q1a
(b)
#2 group failure
* =100%Poa
P1a
* =100%Qoa
Q1a
i1a V1a*
v1a
V1a Sine Generator
P,Q
v1a_ref
1a
Controller
V1asin(t+1a)
a*
PLL
v1a
P1a*
Q1a*
i2a V2a*
v2a
V2a Sine Generator
P,Q
v2a_ref
2a
Controller
V2asin(t+2a)
*
a
i1a
Voltage i1a_ref
Controller
v2a
P2a*
Q2a*
PWM
Current
Controller
PWM
ga12
Phase A in #1 Group
i2a
Voltage i2a_ref
Controller
PLL
CAN Synchronization
Bus
Bus
ga11
Current
Controller
ga21
ga22
Phase A in #2 Group
(c)
Fig. 21. (a) Series converters for motor drive (b) Parallel converters for UPS
system (b) Control strategy for parallel UPS system
VIII.CONCLUSIONS
S2
Redundant
Modules
M_Ap 1
S1
Redundant
Modules
Each Module
CR
+Vdc
and phase-leg open-circuit. However, the power rating after

faults is degraded. Parallel converters have been used to
improve the reliability in active power filters [89],
uninterruptible power supplies (UPSs) [90], and DFIGs [91].
As shown in Fig. 21 (b), one of inverters is operated in normal
condition. When faults occur, the other inverter can replace
the faulty one for continuous operation. However, when the
dual converters are operated at same time during normal
situations, the reduction of circulating currents among
converters is an important objective to address. Several
control techniques have been developed to ensure equal load
sharing [92]-[93]. As shown in Fig. 21(c), the current sharing
is controlled via regulating the magnitude and the phase angle
of the output references. In addition, this concept is applied in
DC/DC converters, AC/DC converters, etc. Two common
connection structures are common DC-bus and high frequency
AC-bus.
(c)
Fig. 20. Series redundant module (a) Cascaded converters topology (b)
Cascaded converters control (c) modular multilevel converters topology
VII. HARDWARE RECONFIGURATIONS: SYSTEM-LEVEL

In this section, two types of system-level hardware
solutions for fault reconfiguration are introduced, which are
cascaded converters and parallel converters. As shown in Fig.
21(a), three switches are added in series with each output
phase [6]. Therefore, the modified configuration is able to
handle single switch short-circuit, single switch open-circuit,
This paper presented a comprehensive review of faulttolerant techniques in power electronic converters that have
been introduced in past literatures. The fault-tolerant solutions
are always based on hardware redundancy plus associated
control strategies. Therefore, the conventional fault-tolerant
techniques are classified into switch-level, leg-level, modulelevel and system-level solutions based on the type of hardware
redundancy. Various approaches are presented and their
advantages and disadvantages are analyzed in detail. It is
shown that some fault-tolerant methods, such as redundant
switching states and neutral-shift, are easily implemented and
cost-effective, but cannot maintain the full rated power after
faults. Therefore, in mission critical applications, the full
fault-tolerant design serves as a more suitable option.
Therefore, multiple modified topologies with full faulttolerant capability are summarized. Among them, the
redundant parallel leg topology is recognized as the optimal
compromise between system cost, performance and reliability.
Additionally, the implementation of redundant parallel
converters is a relatively mature technique, widely employed

in industrial applications. In conclusion, the past research
identifies the following key results and limitations.
1) As for fault-isolation circuits, the elimination of
increased parasitic inductance due to the presence of fuses
needs to be studied further. Development of power switches
with better short-circuit capabilities and faster fuses would
greatly simplify the fault-isolation circuit.
2) The combination of connecting the faulty leg to the DCbus mid-point and two-phase control are widely applied in
motor drives, which can optimize the redundancy design.
Therefore, it is beneficial to further investigate the hardware
and software combination technique for system fault-tolerance.
3) The parallel and series redundant switch, leg or module
is a big branch of the hardware fault-tolerant solutions. The
redundant unit can be designed in online or offline mode.
Present attention is directed to the offline leg structure due to
remarkably better performance and relatively lower cost.
Additionally, the redundant module applied in MMC for
system redundancy is an hot area of present research.
4) The solutions utilizing the inherent redundancy such as
redundant switching state and neutral-shift are similar in
nature, but differ in the implementation and the form of the
zero-sequence component. Therefore, these approaches cannot
be employed in a three-phase four-wire system due to the
injected zero-sequence component. Also, the reduced output
voltage in post-fault condition is the common drawback for
these strategies.
5) The DC-bus voltage reconfiguration method necessitates
oversized semiconductors, limiting its application range. It is
significant to note that the future direction should look to
explore the combination of multiple methods to optimize
fault-tolerant performance.
6) Very few literatures quantitatively analyze the transition
from the faulty state to the post-fault state. How to achieve the
seamless and rapid transient processes from fault occurrence
to post-fault operation should be addressed further.
7) Since most of the fault-tolerant strategies are only
feasible for single open- or short-circuit fault, the faulttolerant topologies designed to handle multiple faults is quite
few. Further investigation into methods capable of handling
multiple simultaneous faults is needed.
8) Very few quantitative reliability estimations on
topologies after redundant design are reported. It is important
to form systematic approaches to assess the reliability of faulttolerant design.
[4]
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Wenping Zhang (S12) received the B.S degree in
electrical engineering, from Nanjing University of
Science and Technology, Nanjing, China, in 2008.
He is currently pursuing the PhD. degree in the
Department of Electrical Engineering, Zhejiang
University, Hangzhou, China.
From Sep. 2012 to Sep. 2013, he was a visiting
student in electrical engineering at Texas A&M
University. His research interests include fuel cell
power systems, the reliability of the power electronics systems, etc.
Dehong Xu (SM10F13) received the B.S., M.S.,
and Ph.D. degrees from the Department of
Electrical Engineering, Zhejiang University,
Hangzhou, China, in 1983, 1986, and 1989,
respectively. Since 1996, He becomes a full
professor in College of Electrical Engineering of
Zhejiang University. He was a visiting scholar in
University of Tokyo, Japan from Jun. 1995 to May
1996. From Jun. to Dec. of 2000, he was a visiting
professor in CPES of Virginia Tech, United State. From Feb. 2006 to Apr.
2006, he was a visiting professor in ETH, Switzerland. He is interested in
power electronics topology and control, power conversion for energy saving
and renewable energy. He has authored five books and more than 350 papers.
He owns 3 US patent and 20 Chinese patents. He has received three IEEE
paper awards.
Presently he is a board member of Electrical Engineering Discipline of
China State Department Education Degree Committee. He is president of
China Power Supply Society. He was an at-large AdCom member of IEEE
power electronics society from 2006-2008. He is an associate editor of both
IEEE Transaction on Power Electronics and IEEE Transaction on Sustainable
Energy. He was technical program chair of IEEE International Symposium on
Power Electronics for Distributed Generation Systems (PEDG2010), general
chair of PEDG2013, and general chair of IEEE International Symposium on
Industrial Electronics (ISIE2012).
Prasad N. Enjeti (M85SM88F00) received the
B.E. degree from Osmania University, Hyderabad,
India, in 1980, the M. Tech degree from the Indian
Institute of Technology, Kanpur, in 1982, and the
Ph.D. degree from Concordia University, Montreal,
QC, Canada, in 1988, all in electrical engineering. In
1988, he joined, as an Assistant Professor, the
Department of Electrical Engineering Department,
Texas A&M University, College Station. In 1994,
he was promoted to Associate Professor and in 1998
he became a Full Professor. He holds four U.S. patents and has licensed two
new technologies to the industry so far. He is the lead developer of the Power
Electronics/Power Quality and Fuel Cell Power Conditioning Laboratories,
Texas A&M University and is actively involved in many projects with
industries while engaged in teaching, research and consulting in the area of
power electronics, motor drives, power quality, and clean power utility
interface issues.
Dr. Enjeti received the inaugural R. David Middlebrook Technical
Achievement Award from the IEEE Power Electronics Society in 2012. He
received the IEEE-IAS Second and Third Best Paper Awards in 1993, 1998,
1999, 2001, and 1996, respectively; the Second Best IEEE-IA
TRANSACTIONS paper published in mid-year 1994 to mid-year 1995, the
IEEE-IAS Magazine Prize Article Award in 1996, the Class of 2001 Texas
A&M University Faculty Fellow Award for demonstrated achievement of
excellence in research, scholarship and leadership in the field, and he directed
a team of students to design and build a low cost fuel cell inverter for
residential applications, which won the 2001 future energy challenge award,
grand prize, from the Department of Energy (DOE).
Haijin Li (S13) received the B.S. degree in electrical
engineering, from the Department of Electrical
Engineering, Zhejiang University, Hangzhou, China, in
2010. He is currently pursuing the Ph.D. degree in the
Department of Electrical Engineering, Zhejiang
University, Hangzhou, China.
His current research interests include fuel cell power
system, efficiency optimization for inverter.
renewable energy conversion, etc.
Joshua T. Hawke (S11) received the B.S. degree in

electrical engineering from Texas A&M University,
College Station, TX, USA in 2007. He is currently
working towards his Ph.D. degree in electrical
engineering at Texas A&M University.
From 2010-2011, he was an Application Engineer
for Maxwell Technologies in San Diego, CA, USA.
His current research interests include multiport
converters clean and renewable energy technologies, as
well as multiport power conversion.
Harish S. Krishnamoorthy (S12) received his B.
Tech degree in Electrical & Electronics Engineering
from National Institute of Technology, Tiruchirappalli
in 2008. He is currently working towards his Ph.D.
degree in electrical engineering at Texas A&M
University.
From 2008 to 2010, he was an Engineer in General
Electric (GE) Energy, India. His current research
interests are in high power density converter design,

Survey On Fault

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This article has been accepted for publication in a future issue of this journal, but has not been

Survey on Fault-Tolerant Techniques for Power

AbstractWith wide-spread application of power electronic

This work is supported by the National High Technology Research and

In critical applications, such as military, financial markets and

and therefore can potentially be applied within the industry in

Section III. Section IV summarizes switch-level hardware

Fault-Tolerant Methods for Power Electronics Converters

Dc-Bus Voltage Redundant Series Redundant Series or

Fig. 1. State-of-the-art fault-tolerant methodology chart

Most of multilevel converters are considered switch-level

extra modules in series with other modules. The redundant

while leaving all the healthy switches operational. 4) Impact

Strategy 2a simplified version of Strategy 1has only

IV. FAULT-RECONFIGURATIONS: SWITCH-LEVEL

Redundant Switching States

The fault-tolerant operation based on the vector redundancy

The first fault-tolerant topology shown in Fig. 6(a) forces

In order to further improve the fault-tolerance, some

Fig. 6. Switch-level fault-tolerant motor drives (a) Topology 1 (b) Topology 2

DC-Bus Midpoint Connection

As for three-phase converters, if one phase fails, the

1) The performance in post-fault operations is degraded.

In summary, the main disadvantages of redundant switching

Fig. 5. Fault-tolerant multilevel active clamped topology (a) Normal

Nevertheless, the drawbacks of this approach can be

2) The maximum speed of the machine in post-fault is

The disadvantages of this approach in motor applications

2) Since the healthy phases have to withstand over-current

Following a similar approach, TRIACs are added to 6-leg

Redundant Parallel or Series Switches Installation

1) Redundant Parallel Switch

2) In the offline scheme, one redundant unit is shared by

Unlike the offline scheme, the redundant switch in the

Redundant Parallel Leg

This approach is implemented via adding a parallel

Meanwhile, three TRIACs, e.g. TA~TC, are added as linking

4) The backup leg can operate in online or offline mode.

Redundant Series Leg

The series redundancy leg is widely applied in 3-phase

To sum up, the principle features of the parallel leg

In the online leg scheme, the redundant leg operates even in

VI. FAULT-RECONFIGURATION: MODULE-LEVEL

After faults, an unequal number of modules are applied in

Va Vb 2VaVb cos Vb Vc 2VbVc cos Va Vc 2VaVc cos

where Va, Vb, Vc are the magnitudes of three phase voltages,

In summary, the NS method is easy to be implemented.

Based on (1), the output voltages based on the NS method

The additional limitations of the traditional NS method are

Since the injected zero-sequence component is all

DC-Bus Voltage Reconfiguration

It is noted that a common drawback of the previous method

Unlike the previous method, the approach in [84]-[85]

in Fig. 19 (c), the DC-link voltage of the remaining modules is

Redundant Modules Installation

For CMCs, redundant modules are added in series with the

NA, NB and NC are the numbers

and phase-leg open-circuit. However, the power rating after

VII. HARDWARE RECONFIGURATIONS: SYSTEM-LEVEL

converters is a relatively mature technique, widely employed

Lee, F.C., "The state-of-the-art power electronics technologies and

Yantao Song; Bingsen Wang, "Survey on Reliability of Power

[24] B. McGrath, D. Holmes, and T. Lipo, Optimized space vector