Xilinx 7 Series FPGA

Power Benchmark
Design Summary
January 2015
Copyright 2015 Xilinx
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Application-centric Benchmarking Process

100G Packet
Processor

OTN
Muxponder

ASIC
Emulation

Wireless Radio &

Satellite Modem

Edge
QAM

AVB
Switcher

Military
Radio

Mobil
Backhaul

FPGA resource counts, toggle rates, clock speeds

Xilinx Power Estimator

(XPE) version 2014.4
MAX condition used to
estimate worst-case
static power

Page 2

Competitors
Estimator

XPE

Copyright 2015 Xilinx

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Early Power Estimator

(EPE) versions 14.1
MAX condition used to
estimate worst-case static
power

Power Benchmark: Traffic Manager in 100G Line Card

Virtex-7 X690T FPGA
Xilinx Altera
Transceiver
I/O
Dynamic
Static
1.30X

Interlaken
16 at 10.3125G

Interlaken
16 at 10.3125G

Transceivers

20

Interlaken

NPU

Interlaken

25

Traffic
Management

30

Transceivers

Total Power (Watts)

35

DDR3
DDR3
DDR3
SDRAM

Backplane
Interface

15
10
5

Resources

0
Virtex-7 Stratix V
X690T 5SGXA7
-2LE
I-Grade

Interface

622K

I/Os

GTs

Environment

Process

Tj = 100C

Max

Rate

LC/LEs

232K
167K

8 x 32-bit DDR3

544

1600 Mb/s

Flip-Flops

Interlaken

32

10.3 Gb/s

Block RAM
DSP Blocks

PLLs

Core Freq.
*Design results sourced from Xilinx Power Estimator (XPE) version 2014.4 and Altera Early Power Estimator (EPE) version 14.1
Page 3

Copyright 2015 Xilinx

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15,516 Kb

250 MHz

Power Benchmark: 100GE over OTU4 Transponder

Virtex-7 X690T FPGA

Total Power (Watts)

30

Transceivers

35

100GE
Mapper

Transceivers

100G
OUT-4
OTL4.10
Optical 10X11.18G
Module

100G
EFEC

Transceiver
I/O
Dynamic
Static

OTU-4
Framer

Xilinx Altera

Overhead Processing

1.27X

CAUI

100G
OUT-4
Optical
Module

100GE
Clients

25

Overhead bus

20
15

10

Resources

622K

0
Virtex-7 Stratix V
X690T 5SGXA7
-2LE
I-Grade

Interface

I/Os

GTs

Rate

Process

Tj = 100C

Max

LC / LEs

392K
245K

LVCMOS

50

250 Mb/s

Flip-Flops

GT

10

11.1 Gb/s

Block RAM

9,360 Kb

GT

10

10.3 Gb/s

Core Freq.

350, 175 MHz

*Design results sourced from Xilinx Power Estimator (XPE) version 2014.4 and Altera Early Power Estimator (EPE) version 14.1
Page 4

Environment

Copyright 2015 Xilinx

.

Power Benchmark: ASIC Prototyping

Virtex-7 FPGA 2000T
Xilinx Altera
Transceiver
I/O
Dynamic
Static

2.04X
60

Total Power (Watts)

50

40

30

20

10

0
Virtex-7 Stratix V
2000T EEB (x2)
-2LE
I-Grade

2 x 952K

Resources
Interface

I/Os

GTs

3 64-bit DDR3

366

LVDS

408

Copyright 2015 Xilinx

.

Process

Tj = 100C

Max

Rate

LC / LEs

1066 Mb/s

Flip-Flops

1000 Mb/s

Block RAM

21,600 Kb

Core Freq.

200 MHz

*Design results sourced from Xilinx Power Estimator (XPE) version 2014.4 and Altera Early Power Estimator (EPE) version 14.1
Page 5

Environment

1,224K
765 K

Power Benchmark: Wireless WCDMA / LTE Picocell

Kintex-7 325T FPGA
64 MB
DDR3

DAC
DUC / DDC

OFDM
Modulator

10

OFDM
Demod

PCIe

12

MIMO
Modulator

14

MIMO
Decoder

Total Power (Watts)

16

QAM
DeMod

Layer 1/2 API

1.69X

QAM
DeMod

GbE

18

Channel
Encoder

Transceiver
I/O
Dynamic
Static

64 MB
DDR3

Channel
Encoder

Xilinx Altera

ADC

MicroBlaze
Processor

6
4
2

64 MB
DDR3

Resources

0
Kintex-7
325T
-2LI(0.95V)

Stratix V
5SGXA4
-4I

Interface

420K

I/Os

GTs

Environment

Process

Tj = 100C

Max

Rate

LC / LEs

240K

Flip-Flops

150K

3 x 16-bit DDR3

129

1066 Mb/s

GT

4.0 Gb/s

GT

1.25 Gb/s

GT

2.5 Gb/s

Block RAM
DSP Blocks
PCIe Blocks
Core Freq.

*Design results sourced from Xilinx Power Estimator (XPE) version 2014.4 and Altera Early Power Estimator (EPE) version 14.1
Page 6

Copyright 2015 Xilinx

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14,562 Kb
342

1
307.2 MHz

12
10

Digital Up
Converter

RRC
Filter

FIFO

J.83 Annex
A/B/C
Modulator

14

FIFO

16

EMAC

Total Power (Watts)

18

10 Gig

2.06X

20

Transceivers

10G Network Interface

Dense Edge QAM Modulator

Kintex-7 325T FPGA

RF
4.6 Gigasample
14-Bit DAC

DAC IF

128 Channels RF Port #1

External
External
DDR3
DDR3
Memory
Memory

6
4
2
0
Kintex-7 Stratix V
325T
5SGXEA4
-2LI(0.95V)
-3I

362K

Resources
Interface

Xilinx Altera
Transceiver
I/O
Dynamic
Static

I/Os

GTs

LVDS

124

1152 Mb/s

LVCMOS

12

15 MHz

2x 8-bit DDR3

55

800 Mb/s

10.3 Gb/s

GT

Rate

Environment

Process

Tj = 100C

Max

LC / LEs

182K

Flip-Flops

157K

Block RAM
DSP Blocks
Core Freq.

*Design results sourced from Xilinx Power Estimator (XPE) version 2014.4 and Altera Early Power Estimator (EPE) version 14.1
Page 7

Copyright 2015 Xilinx

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12,402 Kb
641
384, 576,156, 192, 200 MHz

Power Benchmark: AVB Switcher

Kintex-7 325T FPGA
Xilinx Altera

1.38X

Transceiver
I/O
Dynamic
Static

DDR3
DDR3
DDR3
SDRAM

10
8

SD / HD / 3G
Transmit Interface

16SD/HD/3G
Inputs1

Frame Buffer
Control /
Frame Sync

12

Chroma Keyer
Mixes, Wipes,
Effects

14
SD / HD / 3G
Receive Interface

Total Power (Watts)

16

8 SD/HD/3G
Outputs1

6
4
2

Resources
0
Kintex-7
325T
-2LI (0.95V)

Arria V
5AGXB3
I-Grade

362K

Interface

I/Os

GTs

3 x 72-bit DDR3

450

GT

16

Environment

Process

Tj = 100C

Max

Rate

LC / LEs

300K

800 Mb/s

Flip-Flops

188K

2.97 Gb/s

Block RAM
DSP Blocks
Core Freq.

*Design results sourced from Xilinx Power Estimator (XPE) version 2014.4 and Altera Early Power Estimator (EPE) version 14.1
Page 8

Copyright 2015 Xilinx

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10,800 Kb
500
148.5 MHz

AVB Switcher (4-channel)

Artix-7 100T FPGA

SD / HD / 3G
Transmit Interface

Chroma Keyer
Mixes, Wipes,
Effects

4SD/HD/3G
Inputs*

Frame Buffer
Control /
Frame Sync

SD / HD / 3G
Receive Interface

1.43X

Total Power (Watts)

DDR 2/3
SDRAM

4 SD/HD/3G
Outputs*

3
2
Control Interface

*Note: SD/HD/3G inputs and outputs share GTs

1
1
0
Artix-7
100T
-1LI
(0.95V)

Cyclone V
5CGXC7
C-Grade

149K

Xilinx Altera
Transceiver
I/O
Dynamic
Static

Process

Tj = 85C

Max

LC / LEs

75K

Flip-Flops

47K

Block RAM

Resources

DSP Blocks
Interface
1 x 64-bit DDR3

I/Os

GTs

112

GT

125

PLL

800 Mb/s

Phaser Block

2.97 Gb/s

Core Freq.

Copyright 2015 Xilinx

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2,250 Kb

Rate

*Design results sourced from Xilinx Power Estimator (XPE) version 2014.4 and Altera Early Power Estimator (EPE) version 14.1
Page 9

Environment

148.5, 400 MHz

Power Benchmark: Single Channel Mobile Backhaul

Artix-7 200T FPGA
Xilinx Altera

Control Plane
Processor

Transceiver
I/O
Dynamic
Static

1.43X

Traffic Management,
Packet Processing

Modem

Timing
Synchronization

Transceivers

Total Power (Watts)

SRAM

Ethernet Switch
Transceivers

DDR3

5
4
3
2
1

Resources

Interfaces
Artix-7
200T
-1LI(0.95V)

Arria V
5AGXA5
I-Grade

190K

Tj = 100C

Max

LC / LEs
Flip-Flops

GTs

1 x 32-bit DDR3

72

800 Mb/s

LVDS pairs

128

800 Mb/s

DSP Blocks

SEIO

150

100 Mb/s

PLL

1.0 Gb/s

Core Freq.

*Design results sourced from Xilinx Power Estimator (XPE) version 2014.4 and Altera Early Power Estimator (EPE) version 14.1
Page 10

Process

I/Os

Switch ports

Rate

Environment

Copyright 2015 Xilinx

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Block RAM

130K
81K
5,076 Kb

345
2
250, 400 MHz

Power Benchmark: Satellite Modem

Artix-7 100T FPGA
Xilinx Altera
1.58x

Total Power (Watts)

1.4

Transceiver
I/O
Dynamic
Static

1.2
1.0
0.8
0.6
0.4
0.2

150K

0.0
Artix-7 Cyclone V
100T
5CGEA7
-1LI(0.95V) I-grade

Process

Tj = 85C

Max

LC/LEs

85 K

Flip-Flops

52 K

Block RAM

Resources
Interface

DSP Blocks
I/Os

1x 32-bit DDR2

69

GTs
-

Rate
250 Mb/s

*Design results sourced from Xilinx Power Estimator (XPE) version 2014.4 and Altera Early Power Estimator (EPE) version 14.1
Page 11

Environment

Copyright 2015 Xilinx

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PLLs
Core Freq.

3,420 Kb
126
2
30, 62.5, 125 MHz

Military Network Protocol Platform Data Aggregator

Artix-7 200T FPGA

Total Power (Watts)

1.44X

6
5
4
3
2
1
0
Artix-7
200T
-1LI(0.95V)

Arria V
5AGXA5
C-Grade

190K

Resources
Interface

Xilinx Altera
Transceiver
I/O
Dynamic
Static

I/Os

2x 36-bit RLDRAMs

GTs

Rate

Process

Tj = 85C

Max

LC / LEs

63K

Flip-Flops

58K

122

520 Mb/s

Block RAM

GT

5 Gb/s

DSP Blocks

GT

2.5 Gb/s

PCIe Blocks

GT

2.5 Gb/s

Core Freq.

*Design results sourced from Xilinx Power Estimator (XPE) version 2014.4 and Altera Early Power Estimator (EPE) version 14.1
Page 12

Environment

Copyright 2015 Xilinx

.

3,600 Kb
400
1
125 MHz