2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

A New Sensitivity-Driven Process Variation Aware

Low Power Self-Restoring SRAM Design
Nandakishor Yadav, Sunil Dutt and G.K. Sharma
ABV-Indian Institute of Information Technology and Management Gwalior
Gwalior (Madhya Pradesh), INDIA - 474015.
Email: {nkyadav.vlsi, hadbodutt3}@gmail.com, gksharma@iiitm.ac.in
AbstractVariation in process parameters results in an appalling number of SRAM failures which jeopardize design yield.
These variations are expected to get further aggravate with
technology scaling. Adaptive Body Bias (ABB) and Dynamic
Voltage Scaling (DVS) are the useful techniques to alleviate the
impact of process variation. However, with continued technology
scaling, the achievable performance by ABB or DVS alone is becoming limited. In this paper, we propose a process corner based
sensitivity-driven approach for self-restoring SRAM design by
amalgamating ABB with DVS. More importantly, we leverage the
contradiction between read-write stabilities and uneven conduct
of inter-die process variation to Noise Margins (NMs) as a blessing
of low-power SRAM design. Simulation results based on PTM
32nm CMOS technology quantify the viability and effectiveness
of the scheme. Proposed approach meliorate Static Noise Margin
(SNM), Read Noise Margin (RNM) and Write Margin (WM) by
12.6%, 59.2% and 6.1%, respectively. In addition, leakage current
is reduced by 57.1% and a power redeem of 67.9%, 13.1% and
5.2% is achieved in hold, read and write mode, respectively.

I.

rates would be very benevolent for yield enhancement. Selfrestoring is a circuit level technique that detects Process Corner
(PC) of the die, and accordingly Adaptive Body-Bias (ABB)
or Dynamic Voltage Scaling (DVS) is employed to ameliorate
failure probability. ABB concedes the tuning of device threshold voltage (Vth ) by controlling Body-to-Source voltage (VBS ),
while DVS concedes the tuning of circuit performance, such as
delay or power by controlling supply voltage (VDD ). Intended
to self-restoring SRAM design, [6] exploit array leakage or
inverter-chain delay monitoring approach to descry the process
corners. However, the approach proposed in [6] impose three
major limitations: 1) Monitoring array leakage or inverterchain delay cannot distinguish between systematic inter-die
variation in pMOS and nMOS devices separately, 2) Leakage
monitoring circuit suffer from temperature variation and 3) For
the high Vth process corner dies, ABB results in a larger
leakage deviation. A zonal based restoring scheme to abate
failure probability and restrain leakage deviation by partitioning zones build on leakage versus threshold voltage is reported
in [7]. As [6] [7] impose a large area overhead, Direct Adaptive
Body-Bias (D-ABB) [8] is a low area overhead approach in
which the effects of process variation are compensated by
estimating device threshold voltage and accordingly ABB is
applied by implementing relationship between Vth and VBS .
D-ABB possess two major short-comings: 1) Design of analog
circuits is a complex task because of the second order effects
on design specifications and 2) Since most high-performance
analog circuits depend on matched devices, the performance
variation caused by this mismatch will be crucial in scaled
CMOS technologies. Unlike [6] [8], a self-restoring closedloop compensation technique by monitoring the read stability
and writability is discussed in [9].

I NTRODUCTION

CMOS technologies are moving continuously toward finer

geometries; exhibiting higher package density, higher functional capability and lower dynamic power consumption [1].
As device dimensions pierce into sub-nanometer regime, designers endure the major blockade of process parameter variation. In nano-scaled era, process variation formulate SRAM
design more complex, longing to excogitate over processinduced stability issues to abate failure probability. Moreover,
increased variability in modern VLSI technology has a severe
cost implication: Semiconductor industries must discard under
performance SRAM dies which increases cost and decreases
total revenue [2].

However, all the aforementioned techniques deemed to

be good, with further technology scaling to deca-nanometer
regime, process variation cannot be serenity just by ABB or
DVS alone. Further, embedded SRAM memory in Systemon-Chips (SoCs) covers more than 80% of the total chip
area which covet for low-power SRAM design. Sub-threshold
SRAM design helps in reducing power consumption to some
extent, but it raises the stability issues. Moreover, SRAM
failures due to process variation depends on the operating conditions, such as supply voltage and temperature. The operating
conditions changes dynamically, which posses the challenges
to previous mitigation techniques [6] [7] [8] [9]. Also, [10]
shows that ABB increases intra-die variation due to increase
in Short Channel Effects (SCE) which gets worsen with further
technology scaling. In [11], it is investigated that using DVS
together with ABB is much more effective than using any

For last 2-3 decades, researchers scrutinize to seize SRAM

failures at miscellaneous level of abstractions, e.g., devicelevel, circuit-level and architecture-level. At architecture level,
in SRAM memories to improve yield, redundant row/column
based techniques [3] [4] are counseled. These techniques
detects and replaces faulty cells by adaptively remapping.
The architecture assumes that the SRAM is equipped with
a Built-In-Self-Test (BIST) [5] to detect faulty cells due to
process variation. However, these redundancy techniques have
limitations on the number of faulty rows/columns, it can
handle. Also, failures due to intra-die variation are randomly
distributed across SRAM dies and recovery from such failures
is arduous to wield by row/column redundancy.
With the limitations of existing fault tolerant schemes,
SRAM, that can mend itself and, hence, reduce failure
1063-9667/14 $31.00 2014 IEEE
DOI 10.1109/VLSID.2014.27

116

of them individually. [11] utilize ABB and DVS to address

leakage and dynamic power, respectively. In this paper, we
show that even under a large inter-die variation, uniting ABB
and DVS is an effective and reliable technique to mitigate the
impact of process variation. This work is similar to those in
that it aims to exploit post-silicon tuning that can be used
to mitigate the impact of process variation. The approach
differs from the others in that the focus is not just to exploit
either ABB or DVS to furnish SRAM performance and design
yield but, to amalgamate ABB with DVS based on SRAM
sensitivity to process corners and supply voltages to abate
process-induced SRAM failure probability and power budget.
Key features of our work with previous work [6] [7] [8] [9]
[11] can be summarized as follows:

can be divided into two major groups: 1) Inter-die variation

and 2) Intra-die variation.
Lot

Wafer

Die

Device

Intradie

Interdie

Unlike [6] and [8] which confines themselves to

process mitigation techniques, we amalgamate ABB
with DVS for self-restoring low power SRAM design.

We take the avail of contradiction between read-write

stabilities and uneven conduct of process corners to
Noise Margins (NMs) to execute VBB = f (P C, Mode
of Operation (M OP )) which results much squeezed
distribution for noise margins, read-write times and
leakage current, whereas in [6] and [8] VBB = f (P C)
only.

The uniqueness of the proposed approach, i.e.,

VDDSRAM = f (P C, M OP ) results further squeezed
distribution of write time and, hence, reduced write
failure probabilities and a dynamic/leakage power
redeem in read and hold mode, respectively.

Figure 1. Variation observed at different phase of CMOS fabrication process.

1) Inter-die variation: As shown in Fig. 1, the inter-die

variation is the difference in the value of parameters across
nominally identical dies whether those dies are fabricated
on the same wafer, on different wafers or in different lots.
The inter-die variation is caused by deviation in the photolithographic process and is systematic in nature, affecting all
devices in a given die equally. For the purpose of circuit design,
inter-die variation is accounted as a shift in the mean of some
electrical parameter, such as Vth equally across all devices.
Beyond 45nm technology node, the inter-die variability is
generally larger and the concern is how this variation across
the die may impact design performance and parametric yield.
2) Intra-die variation: In contrast to the systematic interdie variation, intra-die variation contributes to significant mismatch in two identical devices placed next to each other on
the same die. The intra-die variation is unpredictable in nature
and caused by random uncertainties in the fabrication process,
such as Random Dopant Fluctuation (RDF), line-edge and linewidth roughness (LER/LWR) and gate oxide thickness (tox )
variation. It has also been observed that the intra-die variation
strongly depends on the circuit layout and exhibits spatial
correlation [12]. Devices that are close together in the layout
have a higher probability of being alike in characteristics than
devices placed far apart. The intra-die variation is critical for
circuits that rely on relative device matching, such as SRAM.

The rest of the paper is organized as follows: Along

with the implementation of proposed united ABB and DVS
approach, Section II also discuss process variation, experimental framework, SRAM stability and failure probability
analysis. To quantify the effectiveness of the scheme, Section
III provides performance analysis of proposed approach with
a brief comparison to [6]. Finally, some conclusions are drawn
in Section IV.
II.

S ELF -R ESTORING SRAM D ESIGN

Process variation cause suspicion in VLSI integrated circuits. Along with the continued technology scaling, significance of understanding and predicting the process variation
is increasing. Also, to cope with process variation, it is
stringent to analyze SRAM stability and failure probability.
Thus, before elaborate on self-restoring SRAM, we divulge
process variation in deep sub-nanometer regime, and talk
across our experimental framework and SRAM stability and
failure probability.

WL
BLB

BL
PL

D0

Dn

QB

D1

AL
NL

D2
Vthn

A. Process Variation

Vthp

Interdie Variation

Process variation, in general, are refer to the difference

between the intended and obtained device parameters prior
and post fabrication. Process variation, such as variation in
channel length (L) and gate oxide thickness (tox ) translate to
variation in the electrical parameters of circuit devices, such as
threshold voltage (Vth ) and drain current (Id ), which increase
the uncertainty in design and consequently jeopardize the
yield. From a circuit design perspective, the process variation

PR

Vthn

Q
AR
NR

Vthp

Intradie Variation

Figure 2. Inter-die and intra-die variation in Vth of SRAM cell devices [9].

3) Joint Impact of Inter-die and Intra-die Variation: The

systematic inter-die variation equally modifies the threshold
voltage of all nMOS and pMOS devices equally. However, random intra-die variation results mismatch in threshold voltage
between neighboring devices. As shown in Fig. 2, the threshold

117

0.9

0.8

0.8

0.7

0.7

0.7

0.6

0.6

0.6

0.5
0.4

QB(V)

0.9

0.8

QB(V)

QB(V)

0.9

0.5
0.4

0.5
0.4

0.3

0.3

0.3

0.2

0.2

0.2

0.1

0.1

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.1

0.1

0.2

0.3

Q(V)

0.4

0.5

0.6

Q(V)

(a)

0.7

0.8

0.9

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Q(V)

(b)

(c)

Figure 3.

Statistical butterfly curves of SNM (a), RNM (b) and WM (c) with intra-die variation at TT process corner for SRAM cell on PTM 32nm.

Figure 4.

Sensitivity of SNM (a), RNM (b) and WM (c) to supply voltage scaling with inter-die variation at each PC for SRAM cell on PTM 32nm.

(a)

(b)

stability and failure probability. Beside NMs, three more

design metrics, i.e., Read Time (RT), Write Time (WT) and
leakage current are entertained to appraise failure probability.

voltage of all nMOS and pMOS devices in an SRAM die is

shifted first from its nominal value due to systematic interdie variation. Next, if a single die is considered, the threshold
voltage of the individual devices in an SRAM cell can vary
due to random intra-die variation. Hence, the total number of
faulty cells in an SRAM is not only a function of the random
intra-die variation, but also a strong function of the systematic
inter-die variation.

C. SRAM Stability and Failure Probability

Stability of 6T SRAM cell can be examined by scrutinising
the butterfly curves as portrayed in Fig. 3, which consists
Voltage Transfer Characteristics (VTCs) of two cross-coupled
inverters moulded by PL/NL and PR/NR (see Fig. 2). MonteCarlo simulations for 5,000 points, as tabulated in Table I III
illuminate how inter-die variation and supply voltage scaling
administer noise margins, leakage/dynamic power consumption and read-write times, respectively. Fig. 4(a-c) connote
sensitivity of Static Noise Margin (SNM), Read Noise Margin
(RNM) and Write Margin (WM) to supply voltage (VDD ) at
different process corners, respectively. Scrutiny of simulation
results in Fig. 4(a-c) and Table I III avow:

B. Experimental Framework
In our simulation framework, to represent systematic interdie variation, we apply a certain amount of threshold voltage shift, i.e., Vth to all devices of an SRAM cell. Next,
to represent random intra-die variation, we impose different
amounts of threshold voltage shift, i.e., Vth to individual
device. Hence, Vth for individual nMOS and pMOS devices
being influenced by both systematic inter-die and random intradie variation can be expressed as [9]:
interdie
intradie
nominal
Vthn = Vthn
Vthn
Vthn
interdie
intradie
nominal
| Vthp
Vthp
|
Vthp = ||Vthp

(c)

(1)

During read operation, dies in FF and FS process

corners are most severe to process variation and suffers
from read failures. However, excessive RNM in SS
and SF process corners can be taken avail of 14.01%
and 15.72% dynamic power redeem, respectively, by
reducing supply voltage in respective process corner.

As WM is almost evenly distributed over process corners, main cause of write failures is the vast deviation
of write time in SS and SF process corners. Hence,
abatement of supply voltage during write operation
not only extricate from write failures but also reduce
an average dynamic power of 5.2%.

Moreover, in accordance with low-power design, conventional wisdom blindly reduce supply voltage in

(2)

In (1) and (2), different sign combination exhibit different process corners, i.e., Typical-Typical (TT), Slow-Slow (SS), Fastinterdie
Fast (FF), Slow-Fast (SF) or Fast-Slow (FS). As Vthn
,
interdie
intradie
intradie
Vthp
, Vthn
and Vthp
can be considered
as Gaussian distributed independent random variables, MonteCarlo simulations for 5,000 points with 18% variability and
3 deviation are engaged to elicit the nature of Vthn and Vthp ,
respectively.
Further, as NMs are widely used design metrics to quantify
SRAM cell stability, we exercise NM-based Monte-Carlo analysis for 5,000 points at each process corner to estimate SRAM
118

Table I.

S TATISTICAL MINIMUM VALUE OF SNM, RNM AND WM AT EACH PC FOR DIFFERENT SUPPLY VOLTAGES .

Static Noise Margin (mV)

TT
SS
FF
SF
FS
201 225 156 220 150
193 215 142 191 143
175 200 127 164 128
156 175 89
125 120
124 148 36
97
103

VDD (V)
0.9
0.8
0.7
0.6
0.5
Table II.

VDD (V)

Table III.

VDD
(V)
0.9
0.8
0.7
0.6

Hold
SS
38.7
22.4
13.3
06
03

Power (nW)
FF
SF
328.5 99
215.2 64.8
137.2 40.6
85.8
25.2
51.5
15

S TATISTICAL MEAN ()

TT

93 5.5
97 5.1
98 4.7
DR

Write Margin (mV)

SS
FF
SF
300 275 251
252 257 233
226 214 175
163 183 105
95
158

TT
283
258
221
186
133

FS
300
284
253
221
187

P EAK POWER CONSUMPTION IN HOLD , READ AND WRITE MODE AT EACH PC FOR DIFFERENT SUPPLY VOLTAGES .

TT
72.9
44.8
26.6
15
08

0.9
0.8
0.7
0.6
0.5

Read Noise Margin (mV)

TT SS
FF SF
FS
50
104 12 110 06
32
62
03 84

05
19

31

07

SS

124 8.3
129 9.2
137 13
DR

FS
266.4
172
108.5
65.4
39

AND STANDARD DEVIATION

Read Time (ps)

FF
SF

68 5.7 126 8.4

81 6.3 135 3.5
DR
145 14
DR
192 36

Read
SS
32.1
27.6
23.2
19.1
15.1

TT
41.2
35.8
30.5
25.3
20.2
()

Power (W)
FF
SF
47.8 31.8
41.4 26.8
35
21.9
29
16.8
24
11.8

FS
47.8
42
36.3
31.1
27

TT
42.7
42.2
41.2
39.7
37.5

67.7 5.4
DR
DR
DR

108
96
45.6
30.8

TT

Power
FF
52
51.2
50.2
49
46.7

(W)
SF
33.8
33
31.7
29.5
26.2

FS
51.8
51.5
50.8
49.5
48.1

PC FOR DIFFERENT SUPPLY VOLTAGES .

OF READ AND WRITE TIMES AT EACH

FS

Write
SS
33.8
33.1
32.1
30.5
28.4

Write Time (ps)

SS
FF
SF

WF#
68 5.6
WF#
WF#
45 12
WF#
#
WF
30 16
74 23
87 8.1 21 7.4 29 5.3

21.8
36.3
38.2
2.4

FS

84.8
34.7
28.5
21.4

13
7.5
4.2
1.6

DR = Destructive Read and WF# = Write Fail

VDDSRAM = f (P C, M OP )

(4)

Control
Logic

WR

From the above stanza one can educe: ABB and supply
voltage adopted by SRAM cells in accordance with process
corner and MOP may ensure optimal power budget and lessen
failure probability, i.e.,
(3)

C3

C1

RD

S0

VBS = f (P C, M OP )

VDD

VDD

data-retention mode which results either sub-optimal

power budget or hold failures. For example, Fig. 4(a)
evident hold failure in FF process corner beyond 0.5V,
while SS process corner can sustain upto 0.4V.

S5

C0

Dynamic Voltage
Supply (DVS)
f(PC, MOP)

C3

VDD

SRAM

C0

C2

VDD
Calibrate

V DD

InverterChain
SRAM

SRAM

= f(PC, MOP)
VBSn
VBSp

Enable

Disable
RD
WR

where, PC = process corner (i.e., TT, SS, FF, SF or FS) and

MOP = mode of operation (i.e., hold, read or write).

Clk

Counter

Q0

Q5

Latch

S0

S5

BodyBias
Generator
f(PC, MOP)

Reset

D. United ABB and DVS

Figure 5.

As elucidated in previous section, read failures are more

probable in FF and FS process corners, while write failures
emerge in SS and SF process corners. Nevertheless, by redressing the threshold voltage of cell devices which has deviated due
to process variation from its nominal value, failure probability
can be governed. We operate VBS = f (P C, M OP ) to retrieve
SRAM stability and VDDSRAM = f (P C, M OP ) to further
abate write failure probability and to reduce leakage/dynamic
power consumption. As delineated in Fig. 5, the proposed
approach is a amalgamation of ABB with DVS in which: 1) An
on-chip mechanism detect process corners, 2) RD/WR control
signals monitor SRAM mode of operation and 3) Accordingly,
supply voltage and Reverse Body-Bias (RBB), Forward BodyBias (FBB) or Zero Body-Bias (ZBB) are applied to amend
SRAM failure probability and power budget.

Proposed self-restoring SRAM using united ABB and DVS.

Implementation of proposed approach yell for a process

corner detection circuit and a DVS in which input signal
states pilot the output voltage. Since the delay of an inverterchain depends on threshold voltage, we avail of an inverterchain to estimated process corners [6]. To mirror the effect of
process variation, CMOS devices in inverter-chain are designed
identical to SRAM cells. As intra-die variation threaten to
distinguish dies from different process corners, like [6], we
exploit central limit theorem to investigate depth of inverterchain. Using central limit theorem, the distribution of a random
variable (say, Y) which is the summation of a large number
of independent random variables (say, X1 , X2 .....Xn ) can be
119

(a)
Figure 6.

(b)

(c)

Squeezed statistical distribution of SNM (a), RNM (b) and WM (c) at different PC with proposed approach for SRAM cell on PTM 32nm.

assumed to be normal with mean and the standard deviation

given by:
Y =

n

i=1

Xi and Y2 =

n


2
X
i

consumption. The adversity in employing united ABB and

DVS approach is to appoint optimal tradeoff between bodybias and supply voltage which is a 3D optimization between
NMs, RT/WT and leakage/dynamic power. However, Table I
III assist designers to fix the problem.

(5)

i=1

If all the variables are identically distributed, i.e., all with

equal mean X and standard deviation X , we further obtain:

Y
1 X
=
(6)
Y = N X and Y = N X
X
N X
From (6), it can be observed that the spread (standard deviation/mean) of the variable Y is less than the spread in
the variable X. Further, the spread of Y reduces as more
number of variables are added together. Eventually, MonteCarlo simulations for 5,000 points at each process corner
assure ample segregation in delay rendered by 800 stage
inverter-chain. It has also been noticed that inverter-chain size
raise exponentially with technology scaling. Further, a counter
is used to resolve the delay of the inverter-chain which translate
inverter-chain delay distribution to the distribution of counter
states. At the end of count, final state (Q0 Q5) of counter is
sampled to latch by the enable (E) signal. Finally, depending
on the latch output (S0 S5) and MOP (RD/WR), proper bodybias is applied to SRAM cells by body-bias generator which
is implemented using multiplexer and pass-gate methodology.

Figure 7.

Figure 8.

Squeezed statistical distribution of WT with proposed approach.

III.

P ERFORMANCE A NALYSIS

The proposed approach is designed on PTM 32nm CMOS

technology and simulated in SPICE environment to evaluate its efficacy. Monte-Carlo simulations for 5,000 points
interdie
with 18% variability and 3 deviation, i.e., Vthn
interdie
= 85.39mV and Vthp
= 57.89mV are engaged for
statistical analysis. Along with VBB = f (P C, M OP ) and
VDDSRAM = f (P C, M OP ), unlike [6], we exploit seven
different level of body-bias for nMOS and pMOS each, which
results squeezed distribution for noise margins, read-write
times and leakage current. With the proposed approach, as
plotted in Fig. 6(a-c), SNM, RNM and WM mean () value
is augmented by 12.6%, 59.2% and 6.1%, respectively. Figure
8 shows that the distribution of write time with proposed approach is much squeezed because of supply voltage reduction
during write mode of operation in SS and SF process corners
which results reduced write failure probability.

Proposed input signal state piloted DVS output simulation result.

Moreover, to execute VDDSRAM = f (P C, M OP ), we

exercise [13] approach to implement DVS. As shown in Fig.
7 and inset in Fig. 5, DVS generates an output voltage
(VDDSRAM ) which depends on input signal states (C0 - C3).
Based on the latch output (S0 - S5) and MOP (RD/WR),
proper supply voltage is applied to SRAM cells to abate
write failure probability and to reduce leakage/dynamic power

Figure 9.

120

Normalized power redeem in different MOP at different PC.

Further, as proposed approach abate supply voltage in

accordance with process corners and SRAM mode of operation, it is evident from Fig. 9 that united ABB and DVS
adoption assist not only in alleviation of process variation
but also redeem a total leakage/dynamic power consumption
in hold, read and write mode by 67.9%, 13.1% and 5.2%,
respectively. As RNM and WM enforces great challenges to
supply voltage scaling, a minor dynamic power deduction is
feasible in read and write mode, while hold mode results in
tremendous leakage power improvement. Figure 10 shows an
average leakage current reduction in hold mode is by 57.1%.

Figure 12. Proposed approach vs. [6]: SNM, RNM and WM at different PC.

assigning body-bias and supply voltage to SRAM cells in

accordance with process corners and mode of operation. The
proposed approach can effectively be used in current/future
SRAM dies to mend failure probabilities and leakage/dynamic
power budget.
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Normalized leakage current in hold mode at different PC.

As shown in Fig. 5, the proposed approach comprises of

800 stage inverter-chain, 6-bit counter, 6-bit latch, body-bias
generator, control logic and DVS. To accurately predict the
area overhead imposed by the proposed approach requires
complex hand calculations. To make this easy, we extract
layout area of each circuit module using SPICE net-list on
PTM 32nm CMOS technology. As shown in Fig. 11, estimated
area overhead has been reported to decrease exponentially with
memory size and advent less than 0.11% for a memory size
of 1 MB. The proposed approach exhibit larger area overhead
than [8] but comparable to [6]. Further, it has been noticed
that inverter-chain incurs an area penalty of 27.3% which raise
exponentially with technology scaling.

Figure 11.

Area overhead versus SRAM size for proposed approach.

As direct comparison with previous mitigation techniques

is not feasible because of the different experimental environment, technology node and objectives, only a brief comparison
of NMs at different PCs with [6] is shown in Fig. 12.
IV.

C ONCLUSION

The sensitivity of NMs, RD/WR times and leakage/dynamic power consumption to inter-die process variation
have been dissected for the first time. It has been found that
inter-die process variation conduct unevenly to SNM, RNM
and WM. In this paper, we avail of the contradiction between
read-write stabilities and uneven conduct of inter-die process
variation to ameliorate SRAM stability and power budget by

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