Below is diagram of Microsoft XBOX SoC.

Task: Propose and discuss verification strategy and challenges for this SoC
design. Assume all blocks are new design, except for the RAMs and CPU, which
are external IPs. State your assumptions if any.

Assumption:
Assume that it is a bottom up IP integration, where individual IP/Blocks are fully
functionally verified before integration to SoC. Also behaviour modelling is done
and mapped with functional requirements.
1st Level verification strategy:
1. System boot up:
Primary CPU can execute boot sequence and bring itself up.
GPU should boot up.
Reset mechanism.
2. Registers access :
Address decoding verification by accessing all memory mapped
registers.
Access Special Function Registers (SFR) of CPU and external GPU.

3. Basic data flow verification:

PCIE_interface <->IOMMU <->DDR (Write and read).
AVin->GPUMMU->DDR (Write)
AVout <- GPUMMU <-DDR (Read)
CPU->IOMMU->PCIE_interface
CPU->GPUMMU->AVout
4. Handshake and transaction between CPU and GPU
5. Memory access by CPU and GPU
2nd Level Verification Strategy, after system boot up successful.
1. Important functional Tests of individual IP to be ran on SoC.
2. Memory Sharing and synchronised page table by different processors and
applications.
3. Cache Coherence verification: Write to one cache is observed by other
caches.
4. PCIE to AVout data flow via GPU verification.
5. Performance verification: multi thread operations and accessing memory
by different processor at the same time. Offloading opration (need to
check either lockdown happens)
6. Run random test with all functioned enable test cases.

Critical Challenges:
1. To integrate IP/Block Level mUVC/iUVC/testbench component to the SoC
level and sync/handshake methodology between them.
2. High throughput transfers effectively utilising DRAM speed 68Gb/s
3. Multithread processing utilising CPU and GPU for verifying offloading
process to concerned processor to gain maximum performance.
4. High efficiency performance testing of video encoding and decoding at
maximum data rates with limited data loss.
5. DRAM data coherence with CPU caches.