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Truth Table for AND operation

Inputs
A

B
0
0
1
1

0
1
0
1

Outputs
Desired
A. B
0
0
0
1

Observed
0
0
0
1

Truth Table for OR operation


Outputs
Inputs
A

B
0
0
1
1

0
1
0
1

Desired x=A+B
0
1
1
1

Observed
0
1
1
1

Truth Table for NOT operation


Inputs
A

Outputs

0
1

Desired
x=A'
1
0

Observed
1
0

NAND operation
Inputs
A

0
1
0
1

Outputs
Desired
x=(A.B)'
1
1
1
0

0
1
0
1

Output
Desired
x= (A + B)'
1
0
0
0

B
0
0
1
1

Observed
1
1
1
0

Truth Table for NOR operation

Input
A

B
0
0
1
1

Observed
1
0
0
0

Truth Table for XOR operation


Input

Output

B
0
0
1
1

0
1
0
1

Desired
x=AOB
0
1
1
0

Observed
0
1
1
0

Schematic for following logic circuit :

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

F1
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1

F2
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1

Q#1 Part 1
F1(A,B,C,D) =[AB (C+ABD)+AB]C

Truth Table:

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

F1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0

Q#1 Part 2

F2(A,B,C,D) =
Truth Table:
A

F2

Q#2 Part 1
F1(A,B,C,D) =D(AB+CA)+ADC+BCD(A+DCB)

Truth Table:

F1

Q#2 Part 2

F2(A,B,C,D) =

Truth Table:

F2

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