Electronic circuit Lab

FEEE-University of Technology

Lab6- MOSFET LOGIC GATE CIRCUITS

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[1] Nm vng v xy dng c cng o NMOS v CMOS.
[2] o v v c tuyn truyn t p (VTC) ca cng o.
[3] o c v tnh ton thi gian tr (propagation delay).
[4] o c v tnh ton cng sut tiu th ca cc loi cng o.
[5] Kho st cu trc v o c bng s tht ca cng logic NAND v NOR

1. Chun b th nghim
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c li l thuyt v mch cng logic: Microelectronic Circuits, fifth Edition,

Sedra/Smith, pages 336-345 & pages 950-982.

Cho cng o NMOS trn H1.1a, gi s MOSFET c K=0.5mA/V2, Vt=1.5V, hy tnh

ton v v c tuyn truyn t p (VTC) ca mch bng cch tnh Vout khi Vin ln lt
bng 0, 1, 2, 3, 4 v 5V.

Mch H1.1a c ni thm t C ng ra nh H1.1b, gi s C ln b qua cc t

k sinh trong MOSFET, hy xc nh biu thc v gi tr ca thi gian tr cnh ln
(tPLH) v xung (tPHL) ca ng ra khi ng vo l xung vung n cc c bin bng
5V.

Hy tnh ton cng sut ngun cung cp cho cng o H1.1a khi ng vo mc cao
(5V) v mc thp (0V).

Cho cng o CMOS trn H1.2a, gi s MOSFET c Kn=Kp=0.5mA/V2,

Vtn=Vtp=1.5V, hy tnh ton v v c tuyn truyn t p (VTC) ca mch.

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Mch H1.2a c ni thm t C ng ra nh H1.2b, gi s C ln b qua cc t

k sinh trong MOSFET, hy xc nh biu thc v gi tr ca thi gian tr cnh ln
(tPLH) v xung (tPHL) ca ng ra khi ng vo l xung vung n cc c bin bng
5V.

Hy tnh ton cng sut ngun cung cp cho cng o H1.2a khi ng vo mc cao
(5V) v mc thp (0V).

Cho 2 cng logic 2 ng vo nh H1.3a v H1.3b, hy trnh by hot ng ca chng v

cho bit l loi cng g?

c phn 3, thc hin th nghim, sau tm tt cc cng vic chnh phi lm trong
bui th nghim.

Xem li cch s dng dao ng k v my o vn nng o cc i lng lin quan

trong bui th nghim.

Download v c datasheet ca HEF4007

2. Dng c th nghim
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B th nghim chnh ELECTRONIC LAB ANA-MAIN

Module: MOSFET logic gate circuits

Dao ng k: GRS-6052A

My o: Fluke 45

B dy ni

3. Thc hin th nghim

MOSFET l linh kin rt d b hng do tnh in. Do trong qu trnh thao tc th
nghim phi ht sc thn trng tun th ng mt s nguyn tc sau:
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Khng chm tay vo cc G ca MOSFET v rt d gy nguy him cho MOSFET do

tnh in ca tay.

Tt ton b cc ngun cung cp v tn hiu, my o chc nng o in tr, test diode

trc khi thc hin thao tc ni hoc thay i mch.

Khi ni mch, thc hin cc phn ca mch khng lin quan ti MOSFET trc, ni
MOSFET vo sau cng.

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Nu c bt c nghi ng no lin quan ti s h hng ca MOSFET, phi ngay lp tc

bo cho cn b qun l PTN bit kim tra v thay th nu MOSFET b hng. Ch :
s lng MOSFET cho mi bui th nghim l c hn, do vy cn b qun l PTN c
quyn t chi thay th cho nhm TN lm h hng qu nhiu MOSFET.

3.1. Kho st cng o NMOS

3.1.1. o c tuyn truyn t p (VTC)
a. Thc hin mch trn H3.1a dng Block a trn Module MOSFET logic gate circuits
nh H3.1b.

b. My pht sng chnh sng tam gic tn s 500Hz, bin 3V, b ngun DC chnh 3V
lm tn hiu Vin cp cho mch.
c. Dao ng k dng CH1 o ng vo v CH2 o ng ra, Vert mode chn X-Y, hai knh
chn Mode DC.
d. o v v li VTC ca mch, ghi thng tin vo Bng 3.1a.

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3.1.2. o thi gian tr tPHL & tPLH

a. Thc hin mch trn H3.1c dng Block a trn Module MOSFET logic gate circuits
nh H3.1d.

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b. o v v li (Bng 3.1b) dng sng ng ra khi ng vo l sng vung bin 5V, tn

s ln lt l 1KHz v 50KHz.
c. Khi ng vo l sng vung bin 5V tn s 50kHz, hy v li dng tn hiu vo v ra
vo Bng 3.1b, t xc nh tPHL v tPLH.

3.1.3. o cng sut ngun cung cp

a. Thc hin o dng trung bnh ngun cung cp (Iavg) cho cng o trn H3.1c khi
Vin=+5V, t tnh cng sut trung bnh (Pavg) ngun cung cp cho cng.

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b. Thc hin o dng trung bnh ngun cung cp (Iavg) cho cng o trn H3.1c khi
Vin=0V, t tnh cng sut trung bnh (Pavg) ngun cung cp cho cng.
c. Vi mch trn H3.1c, ni Vin vi my pht sng vung bin 5V, tn s
RANGE 100K. Hy o dng trung bnh ngun cung cp (Iavg) cho cng o khi nm
chnh FREQUENCY ca tiu v cc i. T tnh cng sut trung bnh (Pavg)
ngun cung cp cho cng tng ng vi mi trng hp.
d. Ghi cc s liu o c v tnh ton vo Bng 3.1c.
Bng 3.1c Kt qu o cng sut ngun cung cp cho cng o NMOS
i
lng

Vin=5

Vin=0

Vin square wave, RANGE

100k, FREQUENCY Min

Vin square wave, RANGE

100k, FREQUENCY Max

Iavg[A]
Pavg[W]
3.2. Kho st cng o CMOS
3.2.1. o c tuyn truyn t p (VTC)
a. Thc hin mch trn H3.2a dng Block a trn Module MOSFET logic gate circuits
nh H3.2b.

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b. My pht sng chnh sng tam gic tn s 500Hz, bin 3V, b ngun DC chnh 3V
lm tn hiu Vin cp cho mch.
c. Dao ng k dng CH1 o ng vo v CH2 o ng ra, Vert mode chn X-Y, hai knh
chn Mode DC.
d. o v v li VTC ca mch, ghi thng tin vo Bng 3.2a.

3.2.2. o thi gian tr tPHL & tPLH

a. Thc hin mch trn H3.2c dng Block a trn Module MOSFET logic gate circuits
nh H3.2d.

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b. o v v li (Bng 3.2b) dng sng ng ra khi ng vo l sng vung bin 5V, tn

s ln lt l 1KHz v 50KHz.
c. Khi ng vo l sng vung bin 5V tn s 50kHz, hy v li dng tn hiu vo v ra
vo Bng 3.2b, t xc nh tPHL v tPLH.

3.2.3. o cng sut ngun cung cp

a. Thc hin o dng trung bnh ngun cung cp (Iavg) cho cng o trn H3.2c khi
Vin=+5V, t tnh cng sut trung bnh (Pavg) ngun cung cp cho cng.

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b. Thc hin o dng trung bnh ngun cung cp (Iavg) cho cng o trn H3.2c khi
Vin=0V, t tnh cng sut trung bnh (Pavg) ngun cung cp cho cng.
c. Vi mch trn H3.2c, ni Vin vi my pht sng vung bin 5V, tn s
RANGE 100K. Hy o dng trung bnh ngun cung cp (Iavg) cho cng o khi nm
chnh FREQUENCY ca tiu v cc i. T tnh cng sut trung bnh (Pavg)
ngun cung cp cho cng tng ng vi mi trng hp.
d. Ghi cc s liu o c v tnh ton vo Bng 3.2c.
Bng 3.2c Kt qu o cng sut ngun cung cp cho cng o CMOS
i
lng

Vin=5

Vin=0

Vin square wave, RANGE

100k, FREQUENCY Min

Vin square wave, RANGE

100k, FREQUENCY Max

Iavg[A]
Pavg[W]

3.3. Kho st cng NAND v NOR

3.3.1. Kho st cng NAND
a. Thc hin cng NAND dng Block b trn Module MOSFET logic gate circuits
b. o v lp bng s tht (Bng 3.3a) th hin hot ng ca cng NAND.
Bng 3.3a Bng s tht cng NAND
A [V]

B [V]

Y [V]

c. Ng vo A ni 0V, ng vo B ni my pht sng vung bin 5V, tn s 1KHz, dng

dao ng k v li dng tn hiu vo B v ra Y vo Bng 3.3b.
d. Ng vo A ni 5V, ng vo B ni my pht sng vung bin 5V, tn s 1KHz, dng
dao ng k v li dng tn hiu vo B v ra Y vo Bng 3.3b.
e. Ng vo A v B ni my pht sng vung bin 5V, tn s 1KHz, dng dao ng k
v li dng tn hiu vo A, B v ra Y vo Bng 3.3b.

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3.3.2. Kho st cng NOR

a. Thc hin cng NOR dng Block b trn Module MOSFET logic gate circuits
b. o v lp bng s tht (Bng 3.3c) th hin hot ng ca cng NOR.
Bang 3.3c Bng s tht cng NOR
A [V]

B [V]

Y [V]

c. Ng vo A ni 0V, ng vo B ni my pht sng vung bin 5V, tn s 1KHz, dng

dao ng k v li dng tn hiu vo B v ra Y vo Bng 3.3d.
d. Ng vo A ni 5V, ng vo B ni my pht sng vung bin 5V, tn s 1KHz, dng
dao ng k v li dng tn hiu vo B v ra Y vo Bng 3.3d.
e. Ng vo A v B ni my pht sng vung bin 5V, tn s 1KHz, dng dao ng k
v li dng tn hiu vo A, B v ra Y vo Bng 3.3d.
4. Bo co th nghim
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Phn tch so snh kt qu l thuyt vi thc nghim

So snh cng o NMOS vi CMOS

Phn tch hot ng ca cc cng NAND v NOR

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