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Lec8 PDN System Up
Lec8 PDN System Up
Lec8 PDN System Up
Gigabyte 965P-S3
Gigabyte 965P-DS3
IR Drop in PDN
To design a high speed system, the first and primary is to keep a
constant supply voltage on the pads of the chips, and keep it within
a narrow tolerance band. Voltage ripple typically on the order of 5%,
which leads to a limitation on impedance of PDN.
Target Impedance
Hierarchies of PDN
PCB
On-die
On-package
decoupling
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VRM
Successful PDN
Target Impedance
Real PDN depends on current spectrum
If the target impedance were 1 Ohm, this board would work well
in all cases.
Even if the target value were as low as 0.2 Ohm, as long as the
current spectrum did not have any worst case amplitude spikes
in the 5 MHz to 20 MHz range, this board might work just fine.
Target Impedance
In the real world of practical product design, its very
hard to establish the target impedance without
accurate spectrum of current drawn by chips
Target Impedance
In practice, maximum transient current is estimated at
some ratio of the active peak current.
The maximum impedance for the PDN, the target
impedance, is established based on the highest
impedance that will create a voltage drop still below
the acceptable ripple spec.
Target Impedance
ome chip vendors, especially FPGA vendors, will
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provide calculation tools that allow simple estimates of
the current draw of specific voltage rails depending on
the gate utilization. These can be used to estimate the
target impedance specs of the rails.
Example of the target impedance of different voltage rails for Altera FPGA.
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When the regulator is turned on, its output impedance drops by orders of
magnitude at low frequency. A large change in current produces a small
change in voltage, the behavior of a low impedance and exactly what is
expected from a regulator. However, the actual behavior of the VRM, this
low impedance is maintained from DC only up to the kHz range.
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General Guidelines
Reduce the impedances in the PDN:
Use power and ground planes on adjacent
layers, with as thin a dielectric as possible,
and bring them as close to the surface of the
board stack-up as possible.
Use as short and wide as possible surface
trace between the decoupling capacitor pads
and the vias to the buried power and ground
plane cavity and place the capacitors where
they will have the lowest loop inductance.
Use SPICE to help select the optimum number
of capacitors and their values.
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Package Types
Package functions
Electrical connection of signals and power, mechanical
connection of chip to board, heat sink, chip protection,
low cost
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4) On-die Capacitance
The impedance at the highest frequency is established
by the on-die decoupling cap.
the capacitance between the power and ground rail
metallization, the gate capacitance from all the p and
n junctions and any added capacitance.
In a typical CMOS circuit, at anyone time, one of the
gates is on and the other is off.
This means that the gate capacitance of one of the
gates, either the p channel or the n channel is
connected between the power and ground rails.
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at 65 nm, total
cap 1000 nF
On-die Capacitance
When the interactions of the on-die capacitance are added to the package
inductance, the behavior is complicated. The figure suggests that no matter
what the board level PDN does, it can never reduce the impedance the chip
sees below the package lead impedance. When the package equivalent lead
inductance is 0.1 nH, the board cannot influence the impedance the chip sees
to below 10 mOhms at frequencies above 10 MHz (for this simulation).
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