INSTRUCTION SET OF MCS 8051

Classified into following six categories

1.Data Transfer Instructions
2.Arithmetic Instructions
3.Logical Instructions
4.Boolean Variable Instructions
5.Branch instructions

Data Transfer Instructions

MOV, PUSH, POP, XCH are data transfer Instructions. Data
Transfer Instruction will not affect the source operand. No flags
are affected by them.
MOV Instruction
Syntax : MOV Destination Byte , source byte
Function : MOV byte variable
Bytes : 1 or 2 or 3 depending on the type of data transfer
The byte specified by the second operand is copied to the
location specified by the first operand.

1. MOV A , Rn

Ex . MOV A , R6

Description : mov register to accumulator

Operation ; (Rn) (A)
Bytes : 1
If the contents of R6 is 65H , accumulator gets 65H after this
instruction .
2. MOV A , direct

Ex . MOV A , 30H

Description : move direct byte

Operation : (direct) (A)
Bytes : 2
3. MOV A , @Ri
Description : move indirect RAM byte to A
Operation : [[Ri]] [A]
Bytes : 1
Ex. mov A , @Ri

If contents of R1 is 87H and the contents of memory location 87H

is 55H then after the execution of above instruction , A gets 55H.

4 . MOV A , #data
Description : Move immediate data to accumulator
Operation : data [A]
Bytes : 1
Ex . mov A , #25
After execution of above instruction A register contains 25H.
#symbol indicates in instruction that it is immediate data.
5. MOV Rn , A
Description : move data from A to register
Operation : [A] [Rn]
Bytes : 1
Ex. MOV R5 , A
6. MOV direct , A
Description : Move accumulator to direct byte
Operation : [A] [Direct]
Bytes : 2
Ex. MOV 40H , A
If a contents is 22H , after the execution memory location 40H
contains 22H.
7. MOV @Ri , A
Description : Move accumulator to indirect memory specified (i.e.
index register Ri)
Bytes : 1
Operation : [A] [[Ri]]
Ex. MOV @Ro , A

If contents of accumulator is 22H and contents of Ro is 35H, after

execution of instruction contents of location 35H is 22H
8. MOV Rn , direct
Description : Move direct byte to register i.e. move contents of
internal RAM
Operation :[ direct address ] [Rn]
Ex. MOV R1 , 45H

9.MOV Rn , #data
Description : Move immediate byte to register.
Bytes : 2
Operation : Data [Rn]
Ex. MOV R2 , #EFH . Contents of R2 becomes EFH
10. MOV direct , Rn
Description : Move register to direct byte.
i.e. move the contents of register to the internal data memory
Bytes : 2
Operation : [Rn] [direct address]
Ex. MOV 30H , R2

If contents of R2=12H, after the execution location 30H contains

12H.

11.MOV direct , #data

Description : Move immediate data to direct byte i.e. move the
immediate data specified in the instruction to the specified
memory location.
Bytes : 3
Operation : data [direct address]
Ex. MOV 40H , #FFH

After execution of above instruction , memory location 40H

contains FFH.
12. MOV direct , direct
Description : Move direct byte to direct. i.e. move the contents of
data memory specified in the instruction to other internal data
memory.
Bytes : 3
Ex. MOV 40H , 30H

If contents of location 30H is 22H , after execution the contents of

location 40H becomes 22H.
13.MOV direct , @Ri
Description : Move indirect RAM to direct byte i.e. move the
contents of internal data memory indicated by Ri to other internal
data memory location.
Bytes : 2
Operation : [[Ri]] [direct address]

Ex . MOV 40H , @Ro

If register Ro contains 60H and contents of location 60H is 12H ,
after execution [40H] = 12H

14. MOV @Ri , direct

Description : Move direct byte to indirect RAM i.e. Move the
contents of internal data memory to other internal data memory
whose address is specified in the index register .
Bytes : 2
Operation : [direct address] [[Ro]]
Ex . MOV @R1 , 30H
If R1 contains 40H & [30H] = 12H , after the execution of
instruction [40H] = 12H .

15. MOV @Ri , #data

Description : Move immediate data to indirect RAM
Operation : Data [[Ri]]
Bytes : 2
Ex . MOV @Ri , #FFH
After execution if Ri = 35H then [35H] = FFH

16. MOV DPTR , #data

Description : Load data pointer with a 16 bit constant i.e. Move
immediate 16 bit data to DPTR register .This is the only
instruction which moves 16 bits of data at once
Bytes : 3
Ex. MOV DPTR , #1234H
This instruction loads the value 1234 into the data pointer . DPH
will hold 12H & DPL will hold 34H .

MOVC INSTRUCTION
Syntax : MOVC A , @A+ ( base register ) Where base register
may be DPTR or PC .
Function : move code byte
Bytes : 1
Description : The MOVC instruction load the A with a code byte or
constant from program memory . The address of the byte fetched
is the sum of the original unsigned 8 bit accumulator contents and
the contents of a 16 bit base register which may be either data
pointer or PC

1) MOVC A , @A+DPTR
Description : move code byte relative to DPTR i.e. copy the code
byte , found at the ROM address formed by adding A and the
DPTR to A .
Bytes : 1

Ex : MOV DPTR , #1234

MOV A , #06H
MOVC A , @A+DPTR ; Copy the contents of effective
address 123AH to accumulator

[ DPTR ]

[A]

1234

effective address
123A

2)MOVC A , @A+PC
Description : move code byte relative to PC . In this case , The
PC is incremented to the address of the next instruction . Then
the byte is fetched from the address formed by the sum of 8 bit
accumulator contents and the contents of a 16 bit register PC.
Operation : PC = PC+1
Bytes : 1

(A+PC) (A)

MOVX instruction
Syntax : MOVX destination , source
Description : move external data byte . The MOVX instruction
transfer data between the accumulator and a byte of external data
memory. There are two types of instructions , differing whether 8
bit or 16 bit indirect address to external data RAM.

1) MOVX @Ri , A
Description : move A to external RAM ( 8 bit address ) i.e. move
the contents of accumulator to the external data memory pointed
by Ri .
Bytes : 1
Operation : [A] [[Ri]]
Ex : MOVX @Ro , A.
If [A] = 33H and [Ro] = 40H , then after execution of

2) MOVX A , @Ri
Description : move indirect external RAM (8 bit address) to
accumulator
i.e. move the contents of external data memory pointed by Ri to
accumulator
Bytes : 1
Operation : [[Ri]] [A]
Ex : MOVX A , @Ro
If [Ro] = 40H and [40H] = 33H then after execution accumulator
contains 33H

In the second type of MOVX instruction the data pointer

generates a sixteen bit address P2 outputs the high order eight

bits i.e. contents of DPH while Po outputs low order eight bits i.e.
contents of DPL with data .

1) MOVX A , @DPTR
Description : move the contents of external data memory pointed
by DPTR to accumulator
Bytes : 1
Operation [DPTR] [A]
If DPTR contains 8000H , And the contents of location 8000H is
22H , then after execution of instruction , A contains 22H.

2) MOVX @DPTR , A
Description : move the contents of accumulator to external data
memory location pointed by DPTR.
Bytes : 1
Operation : [A] [DPTR]
If [A] = 15H , [DPTR] = 1234 , then after execution the contents of
location 1234H becomes 15H.

PUSH AND POP INSTRUCTIONS

The PUSH and POP opcodes specify the direct address of the
data . The data moves between an area of internal RAM , Known
as the STACK and the specified direct address . The stack pointer
is a special function register ( SP ) contains the address of RAM
where data from the source address will be pushed or where data
to be popped to the destination address . No flags are affected .

1) PUSH direct
Description : Push direct byte on to stack .
The stack pointer is incremented by one . The contents
of the indicated variable are then copied into the internal RAM
location addressed by the stack pointer.
Bytes : 2
Operation : SP = SP+1
(Direct address) ((SP))
Ex : PUSH 0E0H
0E0H is the address of accumulator . If [a] = 25H and
[SP]=30H then the location 31H contains 25H after the execution
of above instruction

2) POP direct
Description : POP direct byte from stack i.e. The contents of
internal RAM location addressed by the stack pointer is read . The
stack pointer is decremented by one . The value read is then
transferred to the direct address indicated in the instruction

Bytes : 2
Ex : POP 80H
If [SP] = 30H and [30H] = 55H , Then the internal

MOV , PUSH , POP instructions all involve copying the data

found in source address to the destination address . But the
original data in the source is not changed .
Exchange instructions actually move data
in two directions , from source to destination and destination to
source . All addressing modes except immediate may be used in
the XCH instruction. XCH opcode provides a very convenient way
to save the contents of A without the necessity of using PUSH and
then POP opcode . All exchanges use register A .

XCH Instruction
Syntax : XCH Operand.
XCH instruction Loads the accumulator with the byte value of
the specified operand while simultaneously storing the previous contents
of the accumulator in the specified operand .
Ex .
1. XCH A , Rn
Description : Exchange register with accumulator

Bytes : 1
Operation : [A]

[Rn]
Swap

XCH A ,R3
If [A] = 10H , [R3] = 15H then after execution [A] = 15H & [R3] = 10H.

2 . XCH A , direct
Description : Exchange direct byte with A .i.e. exchange the contents of
accumulator with the internal data memory.
Operation : [A]

[direct address]

Swap

Ex . XCH A , 40H
If [A] = 30 & contents of location 40H = 20H then after execution .
[A] = 20H & contents of location 40H = 30H.

3. XCH A , @Ri
Description : Exchange indirect RAM with A i.e. exchange the contents
of the memory location specified by the index register Ri with A.
Operation : [A]

[[Ri]]
swap

Ex . XCH A , @Ro

If [Ro] = 20H , [20H] = 15H & [A] = 33H , then after execution
[20H] = 33H & [A] =15H

4. XCHD instruction

exchange digit.

Syntax : XCHD A , @Ri

The XCHD instruction exchanges the lower order nibble of the
accumulator (bits 3-0) with the lower order nibble of the specified
internal RAM location . The higher order nibbles (7-4) of each operand
are not affected .
Bytes : 1
Operation : [A]

[[Ri]]

3-0

3-0

Ex . XCHD A , @Ro
If [Ro] = 30H , [30H] = FFH & [A] = 00H
Then after execution , [30H] = FOH & [A] = OFH.

ARITHMETIC INSTRUCTIONS
ADD , ADDC , SUBB , DA , DIV , MUL , INC & DEC are all
arithmetic instructions used in 8051 micro controller .

ADD Instruction
Syntax : ADD A , Source .
The ADD instruction adds a byte value to the accumulator and stores the
result back in accumulator .The destination operand is always in register

while source operand can be register , immediate data or in memory

location. The source is not changed .The flags affected are C ,AC ,OV,P.
Ex.:
1, ADD A , # data
Description : Add immediate data to accumulator .This instruction adds
the contents of accumulator with the 8bit data and the result is stored
accumulator .
Flags affected : C , AC , OV & P
Bytes : 2
Operation : (A) + data (A)
Ex. ADD A , #37H
If [A] = 13H , after execution ,
[A] = 37+13 = 4AH

2. ADD A , Rn
Description : Add the contents of register and accumulator and stores the
result back on the accumulator .
Flags affected :CY , AC , OV & P
Bytes :1
Operand : (A) + (Rn) (A)
Ex . Add A , R2
If [R2] = 44H , [A] = 15H , after execution [A] = 44 +15 = 59H.

3. ADD A , Direct
Description : Add the contents of memory location and accumulator and
stores the result in A .
Flags affected : CY , AC , OV & P
Bytes :2
Operation : [A] +[Direct address] [A]
Ex . ADD A , 30H
If [30H] = 25H & [A] = 15H , after execution [A] = 3AH.

4. ADD A , @Ri
Description : Add the contents of the memory location specified by Ri
with accumulator store the result in accumulator .
Flags affected : AC , CY , OV & P
Bytes : 1
Description : [A] + [[Ri]] [A]
Ex. ADD A , @Ro
[Ro] = 30H , [30H] = 25H , &[A] = 13H , after execution

ADDC Instruction

The ADDC instruction adds a byte value and the value of the
carry flag to the A. the result of addition are stored back in the
accumulator.

1. ADDC A , Rn
Description : Add register contents to accumulator with carry
flag and store the result in accumulator.
Flag affected: CY, AC, P & OV.
Bytes : 1
Operation: [A] + [Rn] + [C] = [A]
e.g. ADD A, R2
if [R2]=13H, [A]=20H, [C]=0
after execution [A]=20+13+0=33H
2. ADDC A, #data
Description: Add the immediate data to A with carry & store
result in A.
Flags affected: CY, AC, OV & P
Operation: [A] + data + [C] [A]
Bytes: 2
e.g. ADDC A, #25H ;
if [A]=13H
after execution [A] = 25+13+1 = 39H
3. ADDC A, @Ri
Description: Add memory location specified by the index
register& the value of the carry flag to the accumulator & the
result is stored in A.
Flags affected: CY, AC, P & OV
Bytes: 1

Operation: [A] + [CY] + [(Ri)] [A]

e.g. ADDC A, @R0
if [A]=13H, [R0]=30H, [30H]=12H & [C]=1
after execution [A] = 13+12+1 = 16H
4. ADDC A, direct
Description: Add the contents of memory location & value of
carry flag to the A & store the result in A.
Flags affected: CY, AC, OV & P
Bytes: 2
Operation: [A] + [C] + [direct address] [A]
e.g. ADDC A, 30H
if [A]=25H, [30H]=21H & [C]=1
after execution [A] = 25+21+1 = 47H

SUBB Instruction
The SUBB instruction subtracts the specified byte variable & the
carry flag from the accumulator. The result is stored always in
accumulator. This instruction sets the carry flag if a borrow is
needed for bit 7 and clears otherwise.
Syntax: SUBB destination, source

1 .SUBB A, Rn
Description: Subtract the register content and the carry flag
from the contents of accumulator and the result stored back in
the accumulator.
Flags affected: CY, AC, P & OV
Bytes: 1
Operation: [A] [Rn] [C] [A]

e.g. SUBB A, R2
if [R2]=40H, [A]=70H & [C]=1
after execution [A] = [A] [Rn] [C] = 70-40-1 = 29H
2 .SUBB A, address
Description: subtract the content of the address indicated in the
instruction and the carry flag from the contents of accumulator
and store the result in accumulator.
Flags affected: CY, AC, P & OV
Bytes: 2
Operation: [A] [address] [C] [A]
e.g. SUBB A, 30H
if [A]=75H, [30H]=25H &[C]=1
after execution [A] = [A] [30H] [C] = 75-25-1 = 49H
3 .SUBB A, @Ri
Description: Subtract the contents of memory location and the
carry flag from the content of accumulator and store the result
in the accumulator.
Flags affected: CY, AC, P & OV
Bytes: 1
Operation: [A] [(R1)] [C] [A]
e.g. SUBB A, @Ri
if [A]=35H, [R1]=20H, [20H]=13H & [C]=1
after execution [A] [(R1)] [C] = 35-13-1 = 21H

4 .SUBB A, #data
Description: subtract 8 bit data & carry flag from the
accumulator and store the result in the accumulator.
Flags affected: CY, AC, OV & P
Bytes: 2

Operation: [A] data [C] [A]

e.g. SUBB A, #33H
if [A]=56H, [C]=1
after execution [A] = [A] [C] data =56-33-1 = 22H

INC Instruction
The INC instruction increments the specified operand by 1. No
flags are affected by this instruction.

1 .INC A
Description: Increment Accumulator i.e. contents of
accumulator are incremented by 1.
Bytes: 1
Operation: [A]+1 = [A]
Ex. If [A] =33H After execution [A]=34H
2 .INC Rn
Description: The content of register is incremented by 1.
Bytes: 1
Operation: [Rn+1] + 1 [Rn]
Ex. If [Rn] =16H After execution [Rn]=17H
3 .INC direct
Description: The content of internal data memory location is
incremented by 1.
Bytes: 2
Operation: [direct address]+1 [direct address]
Ex. If [direct address]=17H
After execution [direct address]=18H

4 .INC @Ri
Description: The content of the internal data memory location
pointed by index register Ri is incremented by 1.
Bytes: 1
Operation: [(Ri)] + 1 [(Ri)]
Ex. INC @R0
If [R0]=30H, [30H]=12H
After execution [(R0)] =13H
5 .INC DPTR
Description: Increment data pointer i.e. add 1 to the 16 bit
DPTR
Bytes: 1
Operation: [DPTR]+1[DPTR]
Ex . If [DPTR]=1770H
After execution [DPTR]=1771H

DEC Instruction
The DEC instruction decrements the specified operand by 1.
1 .DEC A
Description: Decrement the content of accumulator by 1.
Bytes: 1
Operation: [A] -1 [A]
Ex .If [A]=17H

After execution [A]=16H

2 .DEC Rn
Description: The content of register is decremented by 1.
Bytes: 1
Operation: [Rn] -1 [Rn]
Ex. DEC [R2]
if [R2]=19H after execution [R2]=18H
3 .DEC direct
Description: The contents of memory location is
decremented by 1.
Bytes: 2
Operation: [direct address] -1 [direct address]
e.g. DEC 30H
if [30H]=13H after execution [30H]=12H

4 .DEC @Ri
Description: The content of internal data memory location
specified by register Ri is decremented by 1.
Bytes: 1
Operation: [(Ri)] -1 [(Ri)]
e.g. DEC @R0
if Ro=30H & [30H]=11H after execution [(R0)]=10H

MUL Instruction
Syntax: MUL AB

The MUL instruction multiplies the 8 bit no. that is in accumulator

and the 8 bit no. in B register. The lower order byte of the product
is returned in the accumulator. The higher order byte of the
product is returned to the B register. The OV flag is set if the
product is greater than FFH, otherwise it is cleared. The CY flag is
always cleared.
Byte: 1
Operation: A*B [B][A]
e.g. MUL AB
if [A]=04H & [B]=03H
after execution 04*03=0CH higher byte [B]=[00] lower
byte[A]=0CH
OV flag is cleared because result is less than FFH

DIV Instruction
Syntax: DIV AB
The DIV instruction divides the 8 bit data on accumulator by the 8
bit data in register B. after division, the integer part of the quotient
is stored in the accumulator and the remainder is stored in the B
register. The CY & OV flags are cleared.
Bytes: 1
Operation: A/B= [A] [B] i.e. A Quotient and B Reminder

e.g. DIV AB
if [A]=13H & [B]=02H
after execution [A]=09H & [B]=01H

DA Instruction
Syntax: DA A
Description: Decimal adjust accumulator for addition BCD number
system is from 0000 to 1001
Packed BCD 1000 1000 BCD no. in lower byte & upper
byte
Unpacked BCD 0000 1100 BCD no. in only lower byte
The problem of adding two packed BCD no. is, after adding
packed BCD numbers, the result is no longer a BCD no.
e.g. MOV A, #17H
ADD A, #28H
After adding, we get 3FH which is not BCD because if we
convert 3FH to binary we get 0011 1111. Here 1111 is not BCD.
The DA instruction in the 8051 is provided to correct the
problem associated with BCD addition. The mnemonic DA has
accumulator as its operand. The DA instruction will add 6 to the
lower nibble or higher nibble if needed.
Summary or working of DA instruction

Hex
MOV A, #29H

29

0010 1001

MOV B, # 18H

18

0001 1000

ADD A, B

hex

DA A

41

0100 0001

06

0000 0110

BCD 47

0100 0111

After ADD & ADDC instruction

1) If lower nibble is greater than 9, or if AC=1, add 0110 or 06 to
lower nibble.
2) if higher nibble is greater than 9, or if CY=1, add 0110 to higher
nibble.

Logical Instructions
There are of two bytes
1)Byte level logical operators
2)Bit level logical operators

Byte level logical operators

The byte level logical operators use all four addressing
modes for the source of data byte. The A register or a direct
address in internal RAM is the destination of the logical

operations result. No flags are affected by them, only internal

RAM or SFRs may be logically manipulated.
1. ANL instruction
Syntax : ANL destination operand , source operand
Description : The ANL instruction performs a bit wise logical
AND operation between the variables indicated and stores
the result in the destination .The destination operand may be
accumulator or direct address .When the destination is direct
address , The source can be accumulator .
Ex. 1.ANL A, Rn
Description: AND register to accumulator i.e. AND each
bit of A with the same bit of contents of register Rn and
the result is stored in A.
Bytes: 1
Operation: [A] AND [Rn]
e.g. ANL A, R2
if [A]=7FH, [R2]=A5H, after execution [A]=25H
2. ANL A, direct
Description: AND each bit of A with the same bit of the
content of internal RAM location indicated in the
instruction. Put the result in accumulator.
Bytes: 2
Operation: [A] AND [direct address][A]
e.g. ANL A, 30H
if [A]=38H & [30H]=72H
after execution [A]=30H
3. ANL A, #immediate

Description: AND immediate data to accumulator i.e.

AND each bit of A with the same bit of immediate data
and put the result in A.
Bytes: 2
Operation: [A] AND data = [A]
E.g. ANL A, # 78H
If [A]=32H, then after execution [A]=30H
4 .ANL A, @Ri
Description: AND each bit of A with the same bit of
contents of the RAM location contained in Ri, put the
results in Ri.
Bytes: 2
Operation: [A] AND [(Ri)]= [A]
e.g. ANL A, @R0
if [A]=78H & [(R0)]=42H, after execution [A]=40H
5 .ANL direct, A
Description; AND each bit of A with the contents of the
direct address and put the results in the specified
address
Bytes: 2
Operation: [direct address] AND [A] = [A]
e.g. ANL 30H, A

6 . ANL direct, # data

Description: AND each bit of the RAM location with the
same bit of immediate data and put result in internal data memory
location.

Bytes: 3
Operation: [direct address] AND data=[direct address]
E.g. ANL 30H, #35H

ORL Instructions
Syntax: ORL destination, source
Description: The ORL instruction performs a bitwise logical OR
operation on the specified operand and result of which will be
stored in destination operand. This instruction can be written in all
addressing modes.
1. ORL A , Rn
2. ORL A , direct
3 .ORL A , @ Ri
4 .ORL A , #data
5 . ORL direct , A
6. ORL direct , # data

XRL Instruction
Syntax: XRL destination byte source byte

Description: The XRL instruction performs a logical exclusive OR

operation between the specified operands. The results is stored in
the destination operand.
The two operands allow six addressing mode combination when
the destination is accumulator, the source can use register, direct,
register indirect or immediate addressing. When the destination is
direct address, the source can be the accumulator or immediate
data.

1 . XRL A , Rn
2 . XRL A , direct
3 . XRL A , @Ri
4 . XRL A , #direct
5 . XRL direct , A
6 . XRL direct , #data

CLR Instruction (Clear Accumulator)

The CLR A instruction clears the register A i.e all bits of the
accumulator are set to 0.
Syntax: CLR A
Byte: 1

Function: 00[A]

CPL Instruction (Complement Accumulator)

Syntax: CPL A
This instruction logically complements the contents of register A
i.e. 0s become 1s and 1s become 0s.
Bytes: 1
Function: NOT [A] = [A]

RL Instruction (Rotate Accumulator left)

Syntax: RL A
The RL instruction rotates the eight bits on the accumulator left
one bit position. Bit 7 of the accumulator is rotated into bit 0, bit 0
into bit 1, bit 1 into bit 2 and so on.
Bytes: 1

RLC Instruction (Rotate accumulator left through the carry

flag)
Syntax: RLC A
The RLC instruction rotates the eight bits in the accumulator and
one bit in the carry flag left one bit position. Bit 7 of the
accumulator is rotated into the carry flag while the original value
of the carry flag is rotated into bit 0 of the accumulator. Bit 0 is
rotated into bit 1, bit 1 into bit 2 and so on.
Bytes:1

RR Instruction (Rotate Accumulator right)

Syntax: RR A
The RR instruction rotates the eight bits in the accumulator right
one bit position. Bit 0 is rotated into bit 7 of the accumulator, bit 7
into bit 6, bit 6 into bit 5 and so on.
Bytes: 1

RRC Instruction (Rotate accumulator right through carry

flag)
Syntax: RRC A
The RRC instruction rotates the eight bit on the accumulator and
the one bit in the carry flag. Right one bit position. Bit 0 of the
accumulator is rotated into the carry flag while the original values
of carry flag is rotated into the bit 7 of the accumulator. Bit 7 of
the accumulator is rotated into bit 6 and so on.

SWAP Instruction
Syntax: SWAP A
Swap nibbles within the accumulator.
Bytes: 1
The swap instruction interchanges the lower nibble (A0 A3) with
the upper nibble (A4 A7) inside the register A.
[A]=1001 1010
After SWAP instruction, contents of accumulator becomes

[A]= 1010 1001

Bit level logical operators

Boolean variable instructions
1 .CLR C (Clear Carry Flag)
Syntax: CLR C
This instruction clears the carry flag. No other flags are
affected.
Byte: 1
Function: 0 [CY]
Flags affected: CY
2 .CLR bit (Clear direct bit)
This instruction clears any directly addressable bit. No flags
are affected.
Bytes: 2
Function: 0 [bit]
e.g. CLR 30H
it clears the bit in the address 30H [of bit addressable area in
RAM]
3 .SETB C (Set carry flag)
This instruction sets the carry flag to one. No other flags are
affected.
Byte: 1
Function: 1[CY]
Flags affected: CY

4 .SETB bit (Set bit)

This instruction sets the indicated bit to one. No flags are
affected.
Bytes: 2
Function: 1 [bit]
e.g. SETB 30H
this sets the bit addressable area address 30H.
5 .SETB PSW.2 (Set the bit 2 of PSW register
Bytes: 1
Function: 1 [PSW.2]
6 .CPL C
This instruction complements the content of carry flag i.e. 0
becomes 1 & 1 becomes 0. No flags are affected.
Function:
7 .CPL Bit (Complement direct bit)
This bit instruction complements the contents of the
indicated bit. A bit which had been a one is changed to zero
and vice versa.
Bytes: 2
Function:
e.g. CPL P1.2
if [P1]=2CH after execution, [P1]=28H
8 .ORL C, bit (OR direct bit to carry flag

In this instruction the carry flag is placed in the carry flag.

Therefore if the source bit is one, CY is set, otherwise CY
flag remains unchanged.
Bytes: 2
Function: [C] OR [Bit] = [C]
e.g. ORL C, P2.2
if [C]=0 & [P2.2]=1 then after execution [C]=0 or 1=1
9 .ORL C,/bit (OR complement of direct bit to carry)
This instruction involves ORing CY flag with the source bit
itself is not affected.
Bytes: 2
Function: [C] OR
= [C]
ORL C, /P2.2
If [CY]=0, then after execution [CY]=0 or 1 =1
10 .ANL C, Bit (AND direct bit and carry flag)
Function: [CY] AND [Bit] = [CY]
In this instruction, the carry flag bit is ANDed with a source
bit and result is placed in carry.
e.g. ANL C, 20H
if [C]=1 & [20H]=0 then after execution [C]=0 AND 1 =0
11 .ANL D, /bit (AND complement of direct bit to carry)
This instruction involves ANDing CY flag with the
complement of content of the source bit. But the source bit
itself is not affected.
Bytes: 2
Function:

e.g. if [C]=1 & [20H]=0 then [C]=1 AND

after execution.

= 1 AND 1 = 1

12 .MOV C, Bit (move direct bit to CY flag)

This instruction copies the source bit to carry flag.
e.g. MOV C, 25H
if [25H]=1, then after execution of instruction [C]=1
13 .MOV Bit, C (move carry flag to direct bit)
This instruction copies the contents of the carry flag to the
destination bit.
Bytes: 2
Function: [CY] [Bit]
e.g. MOV 25H, C
if [C]=0, after execution, [25H]=0

Looping
Repeating a sequence of instructions a certain number of times is
called a LOOP.
In the 8051, the loop action is performed by the instruction, DJNZ
reg, label.
1 .DJNZ reg, label (Decrement register and jump if not zero)
Bytes: 2
Operation: Prior to the start of the loop the register is loaded
with the counter for the no. of repetition. In this instruction,
the register is decremented if it is not zero, it jumps to the
target address referred by the label. In this instruction, both
register decrement and decision to jump are combined into a
single instruction.

e.g. Write a program to clear accumulator and then add 03 to

the accumulator ten times.
Solution: MOV A, #00H;
A=0, clear Acc
MOV R2, #10H; load counter R2=10
Again: ADD A, #03H;
add 03 to Acc
DJNZ R2, Again; repeat until R2=0(10 times)
MOV R5, A;
save A in R5
2 .DJNZ direct, label :Decrement direct byte & jump if not zero.

Conditional jumps
1 .JZ (Jump if A=0)
If the contents of A=0, then it jumps to the target address. it
can only check to see whether the A is zero. It does not
apply to any other register.
e.g. MOV A, R0
JZ OVER
MOV A, R1
JZ OVER
:
:
OVER : - -- - - - -

2 .JNC (Jump if no carry)

In this instruction, the carry flag bit in the PSW register is
used to make the decision whether to jump. In executing

JNC label, the processor looks at the carry flag to see

whether CY is 0 or 1. If CY=1, no jump to the label then
execution will be jumped to the label address.
e.g. Program to add array 8 bit no. and store the result in
internal data RAM
ARRAY EQU 30H
ASIZE EQU 20H
SUM EQU 40H
ORG 0000H
MOV R1, ASIZE
MOV R0, #ARRAY
CLR A
MOV B,A
BACK:ADD A, @R0
JNC NEXT
INC B
NEXT:INC R0
DJNZ R1, BACK
MOV SUM, A
MOV SUM+1, B
HERE:SJUMP HERE
END

Result

I/P

ARRAY

30H 01
31H 02
32H 03
33H 04
34H 05

20H 05 A
size
o/p
40H 0F

SUM

41H 00

SUM+1

1 .JMP @A, +DPTR (Jump indirect)

The JMP instruction transfers execution to the address
generated by adding the 8 bit in the DPTR register.
[A] + [DPTR] = [PC]

2 .JNZ (Jump if accumulator not zero)

JNZ label: The JNZ instruction transfers control to the

specified address (label) if the value in the accumulator is
not zero.

3 .CJNE A, direct, label

Compare direct byte to Accumulator and jump if not equal
Compare the contents of A register with the contents of the
direct address, if they are not equal, then jump to the
address given by label.

4 .CJNE Rn, #data, label

Compare the contents of register with immediate data. If
they are not equal, jump to the address given in label.

5 .CJNE @Ri, #data, label

Compare the contents of the memory location specified by
register Ri with immediate data. If they are not equal, then
jump to the address given in label.

6 .CJNE A, #data, label

Compare the contents of the accumulator with the immediate
data. If they are not equal, then jump to the address given by
label.

7 .DJNZ direct, label

Decrement the contents of direct address given and jump if
the content of that address is not zero to the address
specified by label.

8 .JC label (Jump if carry is set)

The JC instruction branches to the specified address (label)
if the carry is set. Otherwise execution continues with the
next instruction.

9 .JNC label (Jump if carry is not set)

The JNC instruction branches to the specified address if the
carry flag is 0, otherwise execution continues with the next
instruction.

10 .JB bit, label (Jump if direct bit is set)

The JB instruction branches to the specified label if the
specified bit in the operand is 1. Otherwise execution
continues with the next instruction.

11 .JNB bit, label (Jump if direct bit is not set)

The JNB instruction transfers execution to the specified label
if the specified bit is not set i.e. if [bit]=0

12 .JBC bit, label (Jump if bit is set and clear bit)

The JBC instruction branches to the label if the bit specified
in operand contains 1. Otherwise, execution continues with
next instruction. The bit content that is 1 is cleared.

CALL Instruction
CALL instruction is used to call a subroutine. Subroutines are
often used to perform tasks that need to be performed frequently.
This makes a program more structured in addition to saving
memory space.
There are two instructions
1 A CALL

2 L CALL

1 .A CALL (Absolute subroutine call)

Syntax; A CALL Saddr
Here Saddar means Short absolute address range
The ACALL instruction calls a subroutine located at the
specified address. The subroutine that is called must be
located in the same 2K byte block of program memory. It is a
2 byte instruction.

2 .LCALL (Long subroutine call)

Syntax: LCALL Laddr (Long address)
LCALL instruction can be used to call subroutines located
anywhere within 64K bytes address space of the 8051. It is a
3 byte instruction. When the subroutine is called, control is
transferred to the subroutine, and the processor saves the
PC on the stack and begins to fetch the instructions from
new location. After finishing execution of the subroutine, the
instruction RET (return) transfers control back to the caller.
ACALL (2
bytes)

LCALL (3
bytes)

(PC)+2(PC)

(PC)+2(PC)

(SP)+1(SP)

(SP)+1(SP)

(PC0-7)(SP)

(PC0-7)(SP)

(SP+1)(SP)

(SP+1)(SP)

(PC8-15)(SP)

(PC8-15)(SP)

3 .RET (return from subroutine)

RET is the last instruction of the subroutine. RET POPs the
higher order and lower order bytes of PC from the stack by
decrementing execution continues from the instruction
immediately following ACALL or LCALL.
Bytes: 1
(SP) (PC8-15)

(SP)-1(SP)
(SP) (PC0-7)
(SP)-1(SP)
4 .RETI (return from interrupt)
The RETI instruction is used to end an interrupt service
routine. This instruction pops the higher order & lower order
byte of the PC from the stack, decrementing the stack
pointer. Execution of this instruction returns to the instruction
immediately after the point at which interrupt was detected.
Bytes: 1

Unconditional Jump Instruction

The unconditional jump is a jump in which control is transferred
unconditionally.
1 .LJMP (long jump)
LJMP is an unconditional long jump. It is a 3 byte instruction
in which the one byte represent opcode and second & third
bytes represent 16 bit address of the target location i.e. jump
to any location from 0000H to FFFFH (64K)
Originally 8051 had only 4K bytes on chip ROM, as every
byte is precious. For this reason SJUMP instruction which is
a 2 byte instruction is used.

2 .SJMP (Shot jump)

This is a two byte instruction. First byte is a opcode and
second byte is the address of the target location (00 to FFH).
1 .NOP (No operation)

Machine Cycle
For the CPU to execute an instruction takes a certain number of
clock cycles. In 8051 family, these clocks are referred as machine
cycle depends on the frequency of the crystal oscillator connected
to 8051 system. One machine cycle lasts 12 oscillations period.
16MHz/12=1.333MHz machine cycles
1/1.333 = 0.75 micro sec