ALLAMA IQBAL OPEN UNIVERSITY, ISLAMABAD

(Department of Computer Science)

WARNING
1.
2.

PLAGIARISM OR HIRING OF GHOST WRITER(S) FOR SOLVING

THE ASSIGNMENT(S) WILL DEBAR THE STUDENT FROM AWARD
OF DEGREE/CERTIFICATE, IF FOUND AT ANY STAGE.
SUBMITTING ASSIGNMENT(S) BORROWED OR STOLEN FROM
AIOU PLAGIARISM POLICY.

Course: Digital Logic Design (3409)

Level: Bachelor

Semester: Autumn, 2016

Total Marks: 100
Pass Marks: 50

ASSIGNMENT No. 1
Note: All questions carry equal marks.
Q. 1 Convert the following:
(a) (10001010)2 (?)16
(b) (100110011)2 (?)8
(c) (7657.1100)8 (?)2
(d) (1234.567)8(?)10
(e) Calculate the binary, octal and decimal equivalents of hexadecimal number
(01ECEB) 16.
(20)
Q. 2 (a) Obtain the decimal values for the following binary number expressed in a 2s
complement representation ( in each the most significant bit is the sign bit).
i.
(0110110)Rc
ii.
(01011010111)RC
(b) What is difference between canonical form and standard form? Which form
is preferable when implementing a Boolean function with gates?
(20)
Q. 3 (a) Write down the ASCII codes (in Hex) for the characters in the string This is
a wonderful course! excluding the quotation marks.
(20)
(b) Write down the ASCII codes (in Dec.) for the characters in the string Hello,
hope you are doing well! excluding the quotation marks.
Q. 4 Simplify the Boolean Function F using the dont care condition d,

(a)
(b)
(C)
Q.5

ABC+ABC+ABC+ABC+ABC+ to AB+BC+AB
ABCD+ABCD+ABCD+ABCD+ABCD+ABCD to BD+DB
AB+ABCD+ABCD+ABCD to BD+AB+ACD

(20)

(a) Obtain the NAND logic diagram of a full-adder from the Boolean function
C = xy + xz + yz and S = C (x + y+ z) + xyz
(20)

ASSIGNMENT No. 2
Total Marks: 100
Pass Marks: 50
Note: All questions carry equal marks.
Q. 1 Design an excess-3-to-BCD code converter using a 4-bit full-adders MSI circuit.
(20)
Q. 2 (a) Describe Moore and Mealy model of sequential circuit.
(20)
(b) Express the behaviour of the following Boolean expressions in form of
circuit.
Z= XQ1
DI = X + QI
D2 = XQ2 + X* QI
Q. 3 (a)
(b)

Differentiate between multiplexer and de-multiplexer.

Draw the logic diagram (showing all gates) of a master-slave
D flip - flop. Using NAND gates.

(20)

Q. 4 Design a mod-5 counter which has the following binary sequence: 0, 1,2,3,4. Use
JK flip-flops.
(20)
Q. 5 a)
b)

Draw the interconnection of I2L gates to form a 2 * 4 decoder.

Calculate the noise margin of the ECL gate.

(20)

ALLAMA IQBAL OPEN UNIVERSITY

(Department of Computer Science)
Course Code:
Course Tile:
Credit Hours:
Session Offered:
Recommended Book:
Audio/Video/ Multimedia CD:
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Pre-Requisite:
Course Coordinator:

3409
Digital Logic Design
4(4,0)4 hours lectures per week
Please see the course offering schedule
Digital Logic Design by Morris Mano
Not Available
None
Mohammad
Tariq
Abbasi,
Department
of
Computer
dcs@aiou.edu. Pk
Face-to-Face

Lecturer
Science,

Teaching Methodology:
Introduction:
This course covers; Binary System, Boolean Algebra and Logic Gates,
Simplification of Boolean Function, Combinational Logic, Combinational Logic
with MSL and LSI, Sequential Logic, Digital Logic Circuits
Course Objectives:
At the end of the course the students are expected to be able to:
1. Be familiar with the functions of Logic Gate & Number System
2. Design Combination Logic
3. Design Sequential Logic
Evaluation Criteria:

i.
ii.
iii.

Assignments (02)
Mid Term Theory / Practical Examination
Final Examination

10%
20%
70%

Course Outlines
Unit1:

Binary System
Binary Numbers Based Conversion of Octal, Hexadecimal and Binary,
Complements, Binary Codes, Binary Logic and ICs

Unit2:

Boolean Algebra and Logic Gates

Definitions, Theorems and Properties, Boolean Functions, Canonical and
STD Forms, other Logical Properties, Gates

Unit3:

Simplification of Boolean Function

Map Method, NAND and NOR Implementation, Tabulation Method, Prime
Implement

Unit4:

Combination Logic
Design Procedure, Adder, Subtractors, Code Conversation Analysis
Procedure, NAND and NOR Functions, Ex-OR and Ex-NOR Function

Unit5:

Combination Logic with MSI and LSI

Binary Parallel Adder, Decimal Adder, BCD Counter, Magnitude
Compactor, Decoders, Demultiplexers, Encoder, Multiplexer, ROM, PLA

Unit6:

Sequential Logic
Introduction, Flip Flop, Triggering, State Reduction Excitation Table,
Design Procedure, Design of Counter

Unit7:

Register, Counter, and Memory Unit

Register Counter, Timing Sequence, Memory Unit

Unit8:

Asynchronous Sequential Logic

Analysis Procedure, Circuits with Latches, Design Procedure, Reductions
of State and Flow Tables, Race Free State Assignment

Unit9:

Digital Integrated Circuits

Bipolar Transistor Characteristics, RTL and DTL Circuits, Transistor,
Transistor Logic, Emitter Coupled Logic (ECL), Metal Oxide
Semiconductor (MOS), CMOS

Activities/ Practicals:
Implement the following functions with Nor Gates:
4

1. Design an excess -3 to- BCD code converter using a bit full adders MSI
circuit.
2. Design a combinational circuit that converts a decimal digit form 8,4,-2,-1,
code to BCD.
3. Draw the logic diagram of a 2 line to 4 line decoder / de-multiplexer
using NOR gate only.
4. Implement a full-sub-tractor with two half-sub-tractor and an OR gate.
5. Design a combinational circuit with four input lines that represent a
decimal digit in BCD and four output lines that generates the 9s
complement of the input digit.
6. Draw the logic diagram (showing all gates) of master-slave, D flip-flop.
Use NAND gates.
Computer usage: Use of Internet for exploring DLD resources
Prepared By: Mohammad Tariq Abbasi, Lecturer, Department of Computer
Science
Last revised : Spring 2006