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10 - A CS6201 DPSD
10 - A CS6201 DPSD
10 - A CS6201 DPSD
Thiruninravur-602024
LECTURE PLAN
JEC/Academic/ 10A/01/20.10.2016
Department : ECE
Semester : II
II
III
IV
Proposed
(To be filled at the
Beginning of the semester
based the No. of Hours
alloted in the Time table)
Actual
(To be filled at the end of
each unit)
Signature of Faculty
(To be filled at the end of
each unit)
Signature of HoD
(To be filled at the end of
each unit)
Previous Year
Pass %
Highest grade
Class Average
Faculty handled the
subject in the previous
year
PREPARED BY
APPROVED BY
Name: MR.M.HARIHARAN
Name:MRS.J.JESU MEJULA
Signature:
Signature:
LECTURE PLAN
JEC/Academic/ 10A/01/20.10.2016
UNIT I
BOOLEAN ALGEBRA AND LOGIC GATES
Review of Number Systems Arithmetic Operations Binary Codes Boolean Algebra and Theorems Boolean
Functions Simplification of Boolean Functions using Karnaugh Map and Tabulation Methods Logic Gates
NAND and NOR Implementations.
Topics to be covered
Period
Ref.
Books
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
Tabulation Methods
T1
BLACK BOARD
Logic Gates
T1
BLACK BOARD
T1
BLACK BOARD
T1. Morris Mano M. and Michael D. Ciletti, Digital Design, IV Edition, Pearson Education, 2008.
NO. OF MINI PROJECTS DONE BY THE STUDENTS:
SIGNATURE OF HOD
Note: 1. Faculty should get HoDs signature after completing every unit.
2. The Faculty member can prepare a single Model/ Mini project for all the 5 units (if a model can be used for
all the 5 units or for each unit/topic if possible.
3. After completing each Unit, students should be encouraged to do a mini project and present in the class in front of all the
Students.
LECTURE PLAN
JEC/Academic/ 10A/01/20.10.2016
UNIT II
COMBINATIONAL LOGIC
Combinational Circuits Analysis and Design Procedures Circuits for Arithmetic Operations, Code
Conversion Decoders and Encoders Multiplexers and Demultiplexers Introduction to HDL HDL Models
of Combinational circuits.
Topics to be covered
Period
Ref.
Books
Combinational Circuits
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
Code Conversion
T1
BLACK BOARD
Decoders
T1
BLACK BOARD
Encoders
T1
BLACK BOARD
T1
BLACK BOARD
Introduction to HDL
T1
BLACK BOARD
T1
BLACK BOARD
T1. Morris Mano M. and Michael D. Ciletti, Digital Design, IV Edition, Pearson Education, 2008.
NO. OF MINI PROJECTS DONE BY THE STUDENTS:
SIGNATURE OF HOD
Note: 1. Faculty should get HoDs signature after completing every unit.
2. The Faculty member can prepare a single Model/ Mini project for all the 5 units (if a model can be used for
all the 5 units or for each unit/topic if possible.
3. After completing each Unit, students should be encouraged to do a mini project and present in the class in front of all the
Students
LECTURE PLAN
JEC/Academic/ 10A/01/20.10.2016
UNIT III
SYNCHRONOUS SEQUENTIAL LOGIC
Sequential Circuits Latches and Flip Flops Analysis and Design Procedures State Reduction and State
Assignment Shift Registers Counters HDL for Sequential Logic Circuits.
Topics to be covered
Period
Ref.
Books
Sequential Circuits
T1
BLACK BOARD
Latches
T1
BLACK BOARD
Flip Flops
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
Shift Register
T1
BLACK BOARD
Counters
T1
BLACK BOARD
Counters
T1
BLACK BOARD
T1
BLACK BOARD
T1. Morris Mano M. and Michael D. Ciletti, Digital Design, IV Edition, Pearson Education, 2008.
NO. OF MINI PROJECTS DONE BY THE STUDENTS:
SIGNATURE OF HOD
Note: 1. Faculty should get HoDs signature after completing every unit.
2. The Faculty member can prepare a single Model/ Mini project for all the 5 units (if a model can be used for
all the 5 units or for each unit/topic if possible.
3. After completing each Unit, students should be encouraged to do a mini project and present in the class in front of all the
Students
LECTURE PLAN
JEC/Academic/ 10A/01/20.10.2016
UNIT IV
ASYNCHRONOUS SEQUENTIAL LOGIC
Analysis and Design of Asynchronous Sequential Circuits Reduction of State and Flow Tables Race-free
State Assignment Hazards.
Topics to be covered
Period
Ref.
Books
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
Hazards
T1
BLACK BOARD
Hazards
T1
BLACK BOARD
T1. Morris Mano M. and Michael D. Ciletti, Digital Design, IV Edition, Pearson Education, 2008.
NO. OF MINI PROJECTS DONE BY THE STUDENTS:
SIGNATURE OF HOD
Note: 1. Faculty should get HoDs signature after completing every unit.
2. The Faculty member can prepare a single Model/ Mini project for all the 5 units (if a model can be used for
all the 5 units or for each unit/topic if possible.
3. After completing each Unit, students should be encouraged to do a mini project and present in the class in front of all the
Students
LECTURE PLAN
JEC/Academic/ 10A/01/20.10.2016
UNIT V
MEMORY AND PROGRAMMABLE LOGIC
RAM and ROM Memory Decoding Error Detection and Correction Programmable Logic Array
Programmable Array Logic Sequential Programmable Devices Application Specific Integrated Circuits.
Topics to be covered
Period
Ref.
Books
T1
BLACK BOARD
Memory Decoding
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
T1
BLACK BOARD
CHART
T1. Morris Mano M. and Michael D. Ciletti, Digital Design, IV Edition, Pearson Education, 2008.
NO. OF MINI PROJECTS DONE BY THE STUDENTS:
SIGNATURE OF HOD
Note: 1. Faculty should get HoDs signature after completing every unit.
2. The Faculty member can prepare a single Model/ Mini project for all the 5 units (if a model can be used for
all the 5 units or for each unit/topic if possible.
3. After completing each Unit, students should be encouraged to do a mini project and present in the class in front of all the
Students