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Low Voltage Analog Circuit Design Techniques
Low Voltage Analog Circuit Design Techniques
Analog Circuit
Design Techniques
by S. S. Rajput and S. S. Jamuar
AbstractAnalog signal processing is fast and can address real world problems. The applications of battery powered analog and mixed mode electronic
devices require designing analog circuits to operate at low voltage levels. In this
paper, some of the issues facing analog designers in implementing low voltage
circuits are discussed, and possible low voltage design techniques are examined.
We do not intend to present a review of state-of-the-art technology, but we do
describe briefly almost all low voltage design techniques suitable for analog
circuit structures along with their merits and demerits.
Introduction
24
S. S. Rajput received the B.E. in electronics and communication engineering and the M. E. in
solid state electronics engineering from University of Roorkee, India, (Now Indian Institute of Technology, Roorkee) in 1978 and 1981, respectively, and was awarded the University gold medal in 1981.
He joined National Physical Laboratory, New Delhi, India, as Scientist B in 1983, where he is presently
serving as Scientist EII. He has worked for the design, development, testing and fabrication of an instrument meant for space exploration under the ISRO-NPL joint program for development of scientific
instruments for the Indian Satellite SROSS-C and SROSS-C2 missions. His research interests include
low voltage analog circuit design, instrument design for space applications, digital signal processing
applications, fault tolerant design, and fault detection. He joined the Ph.D. program of Indian Institute
of Technology, Delhi, under the supervision of Professor S. S. Jamuar and submitted a thesis on low
voltage current mode analog circuit structures and their applications. He has more than 20 publications
in national and international journals
26
S. S. Jamuar was born on November 27, 1949. He received the B.Sc. Engineering Degree in electronics and communication from Bihar Institute of Technology, Sindri, in 1967, and the M.Tech and
Ph.D. degrees in electrical engineering from Indian Institute of Technology, Kanpur, India, in 1970 and
1977, respectively. He worked as research assistant, senior research fellow and senior research assistant
between 1969 and 1975 at IIT Kanpur. During 197576, he was with Hindustan Aeronautics Ltd.,
Lucknow. Subsequently he joined the Lasers and Spectroscopy Group in the Physics Department at IIT
Kanpur, where he was involved in the design of various types of laser systems. He joined IIT Delhi in
1977. Presently he is professor in the Department of Electrical Engineering at IIT Delhi since 1991. His
area of interest includes electronic circuit design, instrumentation and communication systems. He was
recipient of Meghnad Saha Memorial Award from IETE in 1976 and the Distinguished Alumni Award
from BIT Sindri in 1999. Dr. Jamuar is senor member of IEEE and Fellow member of IETE (India).
27
VDG
ID
IG
VDS
VGS
Circuits operating in the subthreshold region have gained importance in recent years because of the
need for low voltage and low power
battery powered circuits in human implantable biomedical instruments.
When the applied drain source
voltage in a MOSFET (Fig. 1) exceeds
the threshold voltage, the drain current
VB
V in
I in
I out
M2
M1
V GS1
VGS2
V SS
28
-0.4
-0.6
-0.8
-1.0
0
200
400
600
800
1000
Input current in nA
Figure 3. Input voltage characteristics of the CM.
V
)
GS
T
L
2
and the drain current is zero when
VDS < VT.
This model was derived for small
values (both positive and negative) of
VDS, which correspond to the ohmic
region of operation. In the above equation W, L, and K (Cox) represent the
channel width, channel length and
trans-conductance parameter respectively. The drain current (IDS) is assumed to be zero for VGS < VT and nonzero for VGS > VT. In a physical device,
such an abrupt change does not occur.
IDS is, however, much smaller for VGS
< VT than for VGS > VT and is attributed
to diffusion in the region (VGS < VT,
known as the sub-threshold region). In
the sub-threshold region IDS is given by
[6, 11, 13, 26, 27]
I DS =
2K' W nkT
q(VGS VTN )
exp
(2)
nkT
L qe
where n is the sub-threshold slope factor and lies between 1.2 and 2. Parameters q, k, VTN, and T represent the electronic charge, Boltzman constant,
threshold voltage of NMOSFET and
temperature respectively.
In sub-threshold region, MOSFETs
have low saturation voltages
( 100mV). This gives larger voltage
swings at low-supply voltage even in
cascaded MOSFET structures. Similar
to a bipolar transistor, the trans-conductance (gm) equals (q IDS / nkT) and
is expected to be large. However, it
may be noted that the current IDS itself
is low in sub-threshold region, and gm
cannot be high as in the case of bipolar transistors.
As an example the circuit diagram
of a CM based on sub-threshold
MOSFETs is shown in Fig. 2, which
is similar to any conventional CM. The
simulated output current characteristics of the CM are shown in Fig. 3.
Though these characteristics are similar to any conventional CM, the re29
1.2
I in = 1.0 A
1.0
I in = 0.8 A
0.8
I in = 0.6 A
0.6
I in = 0.4 A
0.4
I in = 0.2 A
0.2
0.0
-1.0
-0.5
0.0
0.5
1.0
VDD
M
V in
VSS
Figure 5. Bulk-driven MOSFET structure.
V DD
Bulk
Source
Drain
n Channel
n+
n+
p Substrate
VDD
I DSS
I DSS
I in
I out
VB
VB
M1
M2
VSS
Figure 7. CM based on bulk-driven MOSFETs.
31
Low Voltage
Analog Circuit
Design Techniques
I in
I out
M1
M2
V SS
Figure 8. JFET equivalent circuit of CM based on bulk-driven MOSFETs.
Current mirror
I out
I in
Vb
M2
M1
V i
V i+
I bias
Current mirror
I out
I in
Self-Cascode Approach
As device sizes are shrinking, the
output impedance of the MOSFET is
also becoming smaller because of
channel length modulation. For high
gain, one needs high output impedance
of the devices, and short channel
MOSFETs cannot provide high gain
structures. To obtain high output impedance, one uses cascode structure as
shown in Fig. 11, where two
MOSFETs are placed one above the
other [9, 1214]. The use of cascode
structure increases the gain but it decreases the output signal swing at the
same time. The output signal swing
reduces at least by one VT if used in the
M1
M2
V i+
V i
I bias
33
Iin
Iout
M4
M3
M1
M2
V SS
design of current mirrors. This decrease
in the output voltage is due to the structure followed in the design of cascode
biasing. Because VT is of the order of
0.75V, cascode structures cannot be
Iin
Iout
Iref
M4
M3
M1
M2
V SS
34
D
ID2
M2
D
m W/L
ID
V GS2
ID1
W/L
M1
VX
V GS
VGS1
S
S
(a)
(b)
Iin
Iout
M3
M1
M2
V SS
35
0.6
I in = 0.5 mA
Output current in mA
0.5
I in = 0.4 mA
0.4
I in = 0.3 mA
0.3
I in = 0.2 mA
0.2
I in = 0.1 mA
0.1
0.0
-1.0
-0.5
0.0
0.5
1.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0.00
0.02
0.04
0.06
0.08
0.10
Input current in mA
Figure 16. Input voltage characteristics.
D
FG
ID
V G1
V G2
V Gn
V GS
Figure 17. Multi-input
floating gate MOSFET.
S
37
Current mirror
I out
I in
Vb
M1
M2
V i+
38
V i
I bias
I in
I out
Vb
M2
M1
VT
W2 L3 I DO2
Ibias exp
(4)
L2 W3 I DO3
Vther
V in
I in
V DD
V GS3
I bias
VB
I out
M3
M1
M2
V DS1
V GS1
V SS
Figure 20. Modified CM based on level shifter technique.
39
Ioffset
2Ibias
= 2
+ VTP3 VTN 2 .
2 3
(5)
For the condition where threshold voltages of PMOS and NMOS are
matched, the minimum offset current
is K2W2L3Ibias / K3L2W3.
Thus, Ioffset is sufficiently high in
the case when M3 is operated in the
saturation region. This follows because
Ibias is higher and K2 / K3 equals 3.
Here K2 and K3 are the trans-conductance parameters (= COX) for M2 and
M3 respectively.
In this configuration, the number
of MOSFETs increases, which is likely
to increase the power dissipation. The
most desirable characteristics include
40
Available
BW
Supply Voltage
Requirements
Power
Consumption
Technology
Requirements
Sub-threshold MOSFETs
Low
2VT
Low
Standard
Bulk-driven MOSFETs
Low
2VT
High
Special
Self-Cascode MOSFETs
Medium
> 2VT
High
Standard
Medium
< 2VT
Medium
Special
High
< 2VT
Medium
Standard
High
< 2VT
Medium
Standard
41
Low Voltage
Analog Circuit
Design Techniques
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42