Professional Documents
Culture Documents
Anil Content & Abstract11
Anil Content & Abstract11
Anil Content & Abstract11
TABLE OF CONTENTS
LIST OF TABLE
LIST OF FIGURES
ABSTRACT
CHAPTER 1
INTRODUCTION TO LOW POWER VLSI
1.1 Introduction
1.2 Basic idea
1.3 Need of the project
1.4 Sub threshold operation
01
01
01
02
02
03
1.7 Summary
04
CHAPTER 2
LITERATURE SURVEY
2.1 Gate Diffusion Input Technique
05
06
07
08
09
09
10
11
12
13
15
CHAPTER 3
IMPLEMENTATION OF PROPOSED DESIGN
3.1 Serial in serial out shift register
17
3.2 Applications
18
3.3 Merits
18
3.4 Demerits
19
CHAPTER 4
ELECTRIC TOOLS DESCRIPTIONS AND COMMANDS
4.1 Electric & LT-spice
20
22
27
31
35
CHAPTER 5
LT SPICE AND SIMULATION DESCRIPTION
5.1 Aim
38
38
45
49
57
CHAPTER 6
RESULTS
6.1 Simulation waveforms
60
CHAPTER 7
CONCLUSION AND FUTURE SCOPE
REFERENCES
63
64
LIST OF TABLES
Table: 2.2.1: Truth table for position of triggering in D-flip flop
Table 2.2.2: Truth table of D-flip flop
Table-6.1.1 Power comparisons between existed and Proposed GDI Based D-Flip
Flop
Table-6.1.2Comparison of area (transistor Count) with existed and proposed
D-flip flop
Table-6.1.3Power comparison of SISO with existed and proposed D-flip
flop
07
07
62
62
62
LIST OF FIGURES
Fig 1.5.1 Basic GDI cell
Fig 1.5.2 Basic Flip Flop Diagram with GDI Multiplexer
Fig 2.1.1Basic GDI cell
Fig 2.2.1 D-flip flop diagram
Fig 2.2.2 Positive-edge triggered diagram
Fig 2.2.3 positive edge triggered D-flip flop diagram
Fig 2.2.4 master slave edge triggered D-flip flop
03
03
05
06
07
08
09
09
11
12
12
13
13
14
14
Fig 2.6.3 Proposed D-Flip-Flop layout diagram using NMOS as delay element
15
Fig 2.7.1 4-bit serial in serial out shift register block diagram
15
Fig 3.1.1 SISO implementation by using four D-flip flops schematic diagram
17
Fig 3.1.2 SISO implementation by using four D-flip flops layout diagram
18
20
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
32
32
33
33
34
34
35
35
36
36
37
37
38
47
48
48
49
50
51
51
52
53
54
55
55
56
60
60
61
Fig 6.1.2 GDI based D-flip flop using PMOS as delay element waveform.
61
Fig 6.1.3 proposed GDI based D-flip flop using NMOS as delay element
61
Simulation waveform.
Fig 6.1.4 waveforms of SISO with basic D-flip flops multiplexer Simulation.
Fig 6.1.5 Waveforms of SISO with proposed NMOS as a delay element.
ABSTRACT
Power consumption minimization is constantly required to meet increasing
demand for Energy performance requirements. For this, designers of next-generation
systems are trying hard to explore new approaches for least possible power
consumption. Major factor to reduce the power consumption is Scaling of power supply
voltage. To achieve higher drive current and hence better speed, threshold voltage may
be reduced but at the cost of increase in the stand-by power. Operating the circuit with a
supply voltage lower than the threshold voltage i.e. sub threshold region is the technique
to achieve ultra-low power. Sub threshold operation is being examined to stretch lowpower circuit designs beyond the normal modes of operation, with the potential for large
energy savings. Ultra low-power consumption can be achieved by operating digital
circuits with scaled supply voltages. In this report proposed sub threshold circuit is
based on GDI (Gate Diffusion Input)-a new technique of low power digital
combinational circuit design.
This technique allows reducing power consumption, delay and area of digital
circuits, while maintaining low complexity of logic design as compared to other CMOS
circuits. Electric Tool is used to design the schematic and layout level diagrams of our
project. The LT-SPICE tool will be used for simulation of the Spice code which tests
the functionality of our generated layout and schematic blocks.