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Shiwani Ref1
Shiwani Ref1
1, JANUARY 2007
169
Poh Chiang Loh, Member, IEEE, D. Mahinda Vilathgamuwa, Senior Member, IEEE,
Chandana Jayampathi Gajanayake, Li Tyan Wong, and Chiew Ping Ang
I. INTRODUCTION
NE of the commonly used inverter topologies for medium
and high power industry applications [1], [2] is the traditional current-source (CS) inverter. The CS inverter is known
to have the advantages of implicit output short-circuit protection and improved load harmonic filtering achieved by its ac
output capacitors. Despite these advantages, CS inverter suffers
from the limited capability of only dcac current-buck conversion and requires a relatively more complex pulsewidth modulator (PWM) [3]. The constraint of CS inverter allowing only
currentbuck power conversion makes it not suitable for low
voltage operation, and usually requires an addition of a controlled front-end buck rectifier for stepping down the dc link
Manuscript received August 16, 2005; revised January 17, 2006. This
paper was presented at the 40th IEEE IAS Annual Meeting Conference,
Kowloon, Hong Kong, October 26, 2005. This work was supported by the
Defense Science and Technology Agency, the Ministry of Defense (Singapore),
and Nanyang Technological University under Grants MD-NTU/05/04 and
SUG30/04. Recommended for publication by Associate Editor P. Barbosa.
P. C. Loh, D. M. Vilathgamuwa, C. J. Gajanayake, and C. P. Ang are with the
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore S639798 (e-mail: pcloh@ieee.org; emahinda@ntu.edu.sg;
chan0178@ntu.edu.sg).
L. T. Wong is with Citibank Singapore, Ltd., Singapore S639798.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2006.886618
170
Fig. 1. Topologies of
Z -source:
link current
, a -source CS inverter can assume an additional open-circuit state by turning OFF all switches without
breaking any inductive current. The impact of open-circuiting
the -source CS inverter can be explained by considering the
equivalent circuits in Fig. 2. During the open-circuit time interval , the inverter side of the -source network is opened by
turning OFF all switches (equivalent to switch OFF in Fig. 2).
At the same time, diode turns ON to conduct the excess curas observed later), and to allow magnetic
rent of (
and
to be transferred to electrostatic enenergy stored in
and . Assuming that
and
ergy stored in
, the circuit equations can be written as
(1)
When in the non-open-circuit state during interval , an
upper and a lower switch of the inverter conducts to connect the
line voltage across the ac filter capacitors, represented as voltage
source in Fig. 2, to the inverter side of the -source network
with diode on the source side reverse-biased. would have
a finite value if the upper and lower ON switches are from different phase-legs (active state, e.g., SW1 and SW2), and zero
if both switches are from the same phase-leg (null state, e.g.,
are
SW1 and SW4). Regardless of the value of , , and
and
charged during the non-open-circuit interval, while
release their stored energy to boost the inverter dc-link current
. The circuit equations for the -source impedance network
can now be rewritten as
(2)
Averaging the current through a -source capacitor over a
and assuming a lossless system,
switching period
, or ) and
the peak dc current , peak ac current (
Fig. 2. Equivalent representations of Z -source CS inverter when in (a) opencircuit and (b) non-open-circuit states.
can be written as
(3)
(4)
(5)
-SOURCE CS INVERTER
LOH et al.:
171
or
where
(6)
,
,
and
2). The relative placement and
switch assignment of (6) are shown in the lower half of Fig. 4.
For illustration of the shoot-through insertion process,
consider the two positive references
S1 and
S4 for
switching S1 and S4 of a phase-leg. Having the additional refer,
ence
S1 causes Gate S1 to turn ON earlier at
causes
Gate
S4
to
turn
OFF
at
the
origwhile reference
S4
inal time instant
. These switching actions obviously insert a
172
TABLE I
SINGLE-PHASE Z -SOURCE VS TO CS STATE MAPPING
-Source VS
CS PWM Conversion
(7)
S1 S4 S3 S6
SVSHOOT S1 S3 S4 S6
(8)
used for switching SW3 SW1) and SW6 SW4). Modifications needed for controlling a -source CS inverter would
still involve the use of the four references in (6) with their
switch assignments and relative placements slightly modified,
as shown in the lower half of Fig. 5. In the figure, the upper
positive reference
SW3 is now used for switching SW3
0.5 , while the lower positive reference
OFF earlier at
. An open-circuit state
SW1 is for switching SW1 ON at
0.5
to
since during
is therefore introduced from
that interval, none of the upper switches are ON to conduct the
outgoing ac current. Based on the same reasoning, a second
0.5
to
is also introduced
open-circuit state from
by the negative references, confirming the implicit open-circuit
insertion of a MRPWM modulator with a minimum of four
device commutations per half carrier period after a simple
reference-to-switch reassignment is implemented.
IV. MODULATION OF THREE-PHASE
-SOURCE CS INVERTER
LOH et al.:
173
C.
or
where
(9)
,
,
,
are three sinusoidal
0.5
is the triplen offset
references and
used to maintain equal null durations at the start and end of a
half carrier period to achieve optimal harmonic performance
[8].
The relative placements of (9) are shown in the lower half of
Fig. 7, where three shoot-through states are inserted immediately adjacent to the active states with the active intervals kept
-Source VS
CS PWM Conversion
174
S1 S6
S2 S3
S4 S5
SW4
SW6
SW2
S3 S4
S5 S6
S1 S2
S1
S3
S2
S5
S4
S1
S6
S4
S3
S6
S5
S2
G1
G1
G1
G1
G1
G1
G2
G2
G2
G2
G2
G2
SVNULL
SVNULL
SVNULL
SVNULL
SVNULL
SVNULL
TABLE II
NULL MAPPING BASED ON RESIDING SEXTANT
(11)
SVSHOOT S1 S4 S3 S6 S2 S5
SW1 SVSHOOT S1 S6 G1 G2 SVNULL
SW4 SVSHOOT S3 S4 G1 G2 SVNULL
SW3 SVSHOOT S2 S3 G1 G2 SVNULL
SW6 SVSHOOT S5 S6 G1 G2 SVNULL
SW5 SVSHOOT S4 S5 G1 G2 SVNULL
SW2 SVSHOOT S1 S2 G1 G2 SVNULL (12)
which give an open-circuit state with all switches (SW1SW6)
1, and one of the non-open-circuit
OFF when SVSHOOT
0. Although (12) fully mapped out
states when SVSHOOT
the required CS gating signals, its use can still result in unwanted
switching when commutating across sextants in the null state.
As an example, assume that the CS inverter is initially in sex30
30 , and is about to cross over to sextant
tant
30
90 in the null state SC7. At the instant of cross
over, the sextant identifier {G1, G2} changes from {00} to {01},
which in turn causes the inverter to switch from SC7 to SC9.
This null-to-null switching involves turning OFF both SC1 and
SC4, and turning ON SC2 and SC5 (four transitions in total),
which should be avoided. A simple method to overcome this
complication is to latch the identifier {G1, G2} (using -latches
or flip-flops), preventing it from changing when in a null state
even when a sextant commutation occurs. The identifier is allowed to update only after a null-to-active state transition occurs. Effectiveness of this method in maintaining a minimum of
LOH et al.:
175
Fig. 10. Simulated filter capacitor voltage v , filtered current i and unfiltered
current i (top to bottom) of a single-phase Z -source CS inverter without open0 and M
0.6.
circuit state, T =T
(13)
where
lag
by 30 (the introduced
gain of 3 can conveniently be compensated by normalization).
as intermediate references for CS moduUsing
lation described above (see Fig. 9) would then result in a set of
by 30 , but in
three-phase line currents leading
as required.
phase with the original references
V. SIMULATION AND EXPERIMENTAL RESULTS
The performance of the derived generic CS switching logic
has been verified in Matlab/Simulink simulation for single and
three-phase -source CS inverters using both EIPWM and
MRPWM. The results obtained show that the generic logic
functions equally well with both EIPWM and MRPWM,
and to meet the given page limit, only results for the theoretically more complex MRPWM are presented here for
performance demonstration. Experimental verification using
the more commonly adopted three-phase CS inverter prototype
has also been performed. The prototype was implemented
by connecting an existing laboratory CS inverter (rated at
600 V, 50 A using Semikron semiconductor modules) to a
-source impedance network constructed using existing com40 mH (rated at 10 A) and
ponents of
15 F (rated at 450 V) with an input source
3 A powering the network. The ac output of the
of
network emulating a
inverter was in turn connected to a
filter and an external load implemented using
second-order
2 mH (rated at 10 A),
15 F (rated at 450 V) and a
resistive load bank adjusted to 15 . The resulting -source
CS inverter was switched digitally at 5 kHz using the control
arrangement shown in Fig. 9, where the digital signal processor
(DSP) with VS PWM peripheral was used for generating the
Fig. 11. Simulated filter capacitor voltage v , filtered current i and unfiltered
current i (top to bottom) of a single-phase Z -source CS inverter with open0.288 and M
0.6.
circuit state, T =T
VS gating signals and the external digital logic card was used
for converting the VS signals to CS signals using the generic
logic presented in the paper.
Figs. 10 and 11 show the single-phase inverter output wave0,
0.6) and with (
0.288,
forms without (
0.6) open-circuit states respectively. In the figures, the
peak inverter dc link current is boosted from 3 A to 7.1 A,
while the inverter ac output is boosted from 1.8 A to 4.2 A with
kept constant at 3 A, hence clearly confirming the currentbuck and boost functionalities of the -source CS inverter. Experimental waveforms obtained using the three-phase inverter
prototype are shown in Figs. 12 and 13 under the same operating conditions and with the same voltage boosting observed
at the inverter dc link and ac output. Another feature noted from
Figs. 1013 is that the voltage across the ac filter capacitor
(
, , or ) is also boosted during the shoot-through state
insertion. This can be explained by noting that with a larger
, , or ) flowing through the fixed
boosted current (
load (15 , 2 mH) used in this work, the corresponding load (or
filter capacitor) voltage is also boosted with more power conis kept constant, a corsumed. Since the dc source current
must happen
responding increase in average source voltage
176
TABLE III
SUMMARY OF PRESENTED PWM TECHNIQUES FOR CONVENTIONAL AND Z -SOURCE CS INVERTERS
Fig. 12. Experimental filter capacitor voltage v (25 V/div), filtered current i
(2 A/div) and unfiltered current i (5 A/div) (top to bottom) of a three-phase
0 and M 0.6.
Z -source CS inverter without open-circuit state, T =T
Fig. 14. CS gate signals (level 1 for upper switches and level 0.5 for lower
30 with (shaded) open-circuit state, T =T
switches) during 30
0.288 and M
0.6.
Fig. 13. Experimental filter capacitor voltage v (50 V/div), filtered current i
(5 A/div) and unfiltered current i (10 A/div) (top to bottom) of a three-phase
Z -source CS inverter with open-circuit state, T =T
0.288 and M 0.6.
Fig. 15. CS gate signals (level 1 for upper switches and level 0.5 for lower
switches) during transition from 30
90 to 90
150 with
0.288 and M
0.6.
(shaded) open-circuit state, T =T
LOH et al.:
from 30
90 to 90
150 . Clearly, Fig. 14 shows
the use of only null state SC7 (SW1 and SW4 of Phase A ON simultaneously, see uppermost plot in Fig. 14) at the start and end
30 ,
of every half carrier cycle when in sextant 30
while Fig. 15 shows the avoidance of null-to-null state transition (SC9 SC8, see Table II), and hence unwanted switching
30 ms by using the -latch
during sextant commutation at
logic described in Section IV-C. The inverter starts to use the
new null state SC8 only from the next null interval onwards
150 .
when in 90
VI. CONCLUSION
This paper presents the development of single- and threephase -source CS inverters controlled using appropriate carrier-based reference formulations and synthesized digital logics
(see Table III for a summary of the various modulation logics
discussed). Some particular advantages of digital logic control
are that it allows the use of a VS modulator for controlling
a -source CS inverter with complications such as commutation difficulties, many-to-many state assignments , and digital sampling coordination resolved, and can be implemented
using a low-cost DSP with embedded VS PWM peripheral and
a programmable logic device. The practicality and proper functioning of the designed inverter have been confirmed in simulation and experimentally using a three-phase laboratory inverter
prototype.
177
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Li Tyan Wong received the B.Eng. degree in electrical and electronic engineering from the Nanyang Technological University, Singapore, in 2005.
Since 2005, she has been with Citibank Singapore, Ltd., as a Financial Advisor.
Chiew Ping Ang received the B.Eng. degree in electrical and electronic engineering from the Nanyang Technological University, Singapore, in 2005.