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Topic 3
Topic 3
Topic 3
CIRCUIT DESIGN
CHAPTER OUTLINE
3.1: Know NMOS and PMOS transistor
3.2: Understand static CMOS inverter
in
CMOS
inverter
equipment,
e.g.
mobile
phone,
computer,
Symbol
Thin oxide
Cross section
Symbol
Thin oxide
Cross section
Cut-off
Linear / Resistive
Saturation
I-V
characteristics
of NMOS
transistor
NMOS
PMOS
CMOS
NMOS AS SWITCH
Vout
Vout
PMOS AS SWITCH
Vout
a)
Vout
b)
ON
Direct path exist
between Vout
and VDD
OFF
NMOS
OFF
ON
Direct path exist
between Vout and
ground node
DROP
implement a logic.
Allow primary inputs to drive gate terminal as well as
source/drain terminals.
MOS transistor as pass-transistor
g
s
Input g = 1 Output
0
strong 0
g=1
NMOS
d
g=0
g
s
s
g=1
Input
d
d
g=1
PMOS
degraded 1
g=0
Output
degraded 0
g=0
strong 1
CMOS INVERTER
Inverter is the most basic logic gate in Boolean
OPERATION
PMOS
NMOS
CMOS INVERTER
When Vin is high and equal to VDD, the NMOS transistor is ON, while the
PMOS is OFF. A direct path exists between Vout and the ground node,
resulting in a steady-state value of 0V.
When the input voltage is low (0V), NMOS transistor is OFF, while PMOS
transistors in ON. A direct path exists between VDD and Vout, resulting in a
steady-state value of VDD.
VOLTAGE TRANSFER
CHARACTERISTICS (VTC)
Combining the IV characteristics of PMOS and NMOS
NMOS off
PMOS res
NMOS sat
PMOS res
NMOS sat
PMOS sat
NMOS res
PMOS sat
NMOS res
PMOS off
CMOS inverter VTC is produced from IV curve of both NMOS and PMOS.
CHARACTERISTIC PARAMETERS
OF CMOS INVERTER
NOISE MARGIN
Noise margin is a measure of sensitivity of a gate to noise.
Represents the level of noise that can be sustained when
VM
can
be
found
graphically
at
the
Logic 0
between
ON
NOISE MARGIN
How much noise can a gate input see before it does not recognize the input?
PROPAGATION DELAY
PROPAGATION DELAY
Propagation delay of a gate defines how quickly it
to output waveform.
PROPAGATION DELAY
Turn
OFF
power
supply
entirely.
Leakage
stack
effect
leakage
Number of inputs.
The number of inputs to the gate.
Fan-out:
Small transistors
BJT
PMOS and NMOs never conducting TTL cannot function without some
at the same time. So, there is little
current drawn at all the time due to
or no current drawn by the circuit
the biasing condition.
from power supply except for what
is necessary to source current to
load.
In static (unchanging) condition, it
BJT is current-controlled device.
dissipates zero power (ideally)Current is drawn all the time and
static power dissipation.
contribute to power dissipation.
CMOS gate draw transient current
during switching- dynamic power
dissipation.
CMOS is voltage-controlled device.
So, it draw less current compared to
BJT.
VOLTAGE TRANSFER
CHARACTERISTIC (VTC)
Recap
Typical VTC
Ideal VTC
TRANSISTOR SIZING
(W/L RATIO)
Minimum length permitted by the technology is usually used as
TRANSISTOR SIZING
(W/L RATIO)
TRANSISTOR SIZING
(W/L RATIO)
Impact of process variation on VTC curve
The good transistor has:
smaller oxide thickness
smaller length
higher width
smaller threshold voltage
The bad transistor has:
larger oxide thickness
larger length
lower width
larger threshold voltage
Conclusion:
The variations cause a small shift in the
switching threshold, but that the operation
of the gate is not affected.
Process variations (mostly) cause a shift in
the switching threshold.
TRANSISTOR SIZING
(W/L RATIO)
IMPACT OF SUPPLY
VOLTAGE SCALING
o The
inverter
characteristic
can
still
be
transistor.