User Application

Completer Request Interface

Completer Completion Interface

PIO Read Transaction

PIO Read Transaction

Figure 5-5 depicts a Back-to-Back

Memory Read request to the PIO
design. The receive engine deasserts
m_axis_rx_tready as soon as the first
TLP is completely received. The next
Read transaction is accepted only after
compl_done_o is asserted by the
transmit engine, indicating that
Completion for the first request was
successfully transmitted.

PIO Write Transaction

PIO Write Transaction

Figure 5-6 depicts a back-to-back

Memory Write to the PIO design. The
next Write transaction is accepted only
after wr_busy_o is deasserted by the
memory access unit, indicating that data
associated with the first request was
successfully written to the memory
aperture.