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Switching Electronics - Betz
Switching Electronics - Betz
R.E. Betz
School of Electrical Engineering and Computer Science
University of Newcastle, Australia.
email: Robert.Betz@newcastle.edu.au
1999,
c 2000, 2001, 2002, 2003, 2004
The notes in this document are for a course in the School of Electrical Engi-
neering and Computer Science at the University of Newcastle, Australia. This
course covers a number of topics that can be broadly grouped under the title of
“switching electronics”. Electronic switching is the unifying factor that provides
the theme for the course. The notes were written because the subject material
covers such diverse areas as digital logic switching families, switched transmis-
sion lines and printed circuit boards, switch mode power supplies (SMPSs), and
(to a lesser degree) converters. No single text book covers such material.
The general approach of the course is to emphasise the practical aspects of
switching and how design has to be changed to account for its effects. The
theory behind many of these ideas is presented in detail in the appendices. This
is particularly true in relation to switching in digital systems with transmission
lines.
The structure of the course is as follows. The first part will consider a variety
of issues related to switching in digital systems. This will include a review of
logic families and interfacing of different logic families. Then issues related to
interfacing logic components on a printed circuit board will be considered. This
will include noise issues, transmission line effects, terminations, cross coupling,
printed circuit board layout, decoupling issues.
The second section of the course will look at switch mode power supplies in
their various forms. The main structures for switch mode power supplies will be
considered. Again practical issues will be emphasised. Design of the magnetics
for switching supplies will be considered, as well as some control issues. The
control issues are only briefly considered due to the lack of background of some
students doing the course.
The final part of the course considers high powered converter and inverter
topologies. At this stage there is only an introduction to high power switch-
ing devices, and a brief look at naturally commutate converters, mostly single
phase. Eventually there will be a reasonable treatment of three phase naturally
converters and forced commutated inverters (using thyristors as well as transis-
tors).
1999 First version of the notes created for the 5 credit point subject ELEC322.
Only included the digital switching and transmission line material.
2000 A major upgrade of the material to include switch mode power supplies,
and some material on higher powered converters. This upgrade was nec-
essary because the subject changed from ELEC322 to ELEC323, and dou-
bled in credit points to 10.
2001 Prior to the issue of the notes, corrections were made to the notes from
2000. Added a chapter on the practical design of switch mode power
supplies. Minor corrections and additions made to the notes through the
course of 2001.
August 19, 2003 Made a few typo corrections as well as a change to an in-
correct diagram.
July 19, 2004 Made typo corrections and added extra remarks in relation to
magnetic utilisation with push-pull converters. Also added an extra re-
mark in relation to the derivation of the fact that harmonics do not con-
tribute to real power. Corrected a few minor diagram errors. Added the
assignments to the appendices.
vi
Contents
List of Figures xi
I Digital Systems 1
1 Logic Families 2
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Review of Logic Family Properties . . . . . . . . . . . . . . . . . 2
1.2.1 A Brief History . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.2 The CMOS Logic Family . . . . . . . . . . . . . . . . . . 3
1.2.2.1 Logic Levels and Noise Margins . . . . . . . . . 6
1.2.2.2 Fanout . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.2.3 Specific CMOS Logic Families . . . . . . . . . . 9
1.2.3 Bipolar Logic Families . . . . . . . . . . . . . . . . . . . . 10
1.2.3.1 Bipolar Logic Noise Margins . . . . . . . . . . . 12
1.2.3.2 Fanout . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.3.3 Specific TTL Logic Families . . . . . . . . . . . 13
1.3 Issues in TTL–CMOS Interfacing . . . . . . . . . . . . . . . . . . 13
IV Appendices 353
A List of Course Materials 354
E Assignment 1 375
E.1 How to Answer the Questions . . . . . . . . . . . . . . . . . . . . 376
E.2 Software Tools to Aid Report Production . . . . . . . . . . . . . 376
F Assignment 2 383
F.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
F.2 Equipment Required . . . . . . . . . . . . . . . . . . . . . . . . . 385
F.3 The Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
F.3.1 The Buck Converter . . . . . . . . . . . . . . . . . . . . . 385
F.3.2 Boost converter . . . . . . . . . . . . . . . . . . . . . . . . 386
F.3.3 Forward converter . . . . . . . . . . . . . . . . . . . . . . 388
xiv CONTENTS
Bibliography 437
List of Figures
4.2 Approximate current flows with low and high frequency spectral
content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.3 Distribution of current in the ground plane when the currents
have high frequency components. . . . . . . . . . . . . . . . . . . 113
4.4 Two traces above a ground plane and the resultant current dis-
tribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.5 Current paths with a slot cut in the ground plane of a PCB. . . . 115
4.6 Current flow through connect hole grids. . . . . . . . . . . . . . . 115
4.7 Layout of a two layer power plane. . . . . . . . . . . . . . . . . . 117
4.8 Layout of a finger power and ground plane system. . . . . . . . . 118
4.9 Guard trace configuration. . . . . . . . . . . . . . . . . . . . . . . 120
4.10 Model for the coupling of a distributed transmission line. . . . . 120
4.11 Mutual inductively coupled transmission lines with Tr = 210psec 122
4.12 Waveforms for capacitively coupled transmission lines and Tr =
210psec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.13 Mutual coupling waveforms with both inductive and capacitive
coupling and Tr = 210psec. . . . . . . . . . . . . . . . . . . . . . 124
9.19 Waveforms for a single phase rectifier with active current wave-
shaping – (a) the input current and voltage; (b) the boost con-
verter input voltage and inductor current. . . . . . . . . . . . . . 326
9.20 Block diagram of the control system for a single phase rectifier
with active current waveshaping. . . . . . . . . . . . . . . . . . . 328
9.21 Single phase rectifier showing the point of common coupling. . . 329
9.22 Single phase rectifier voltage doubler. . . . . . . . . . . . . . . . . 330
9.23 Single phase rectifiers loads in a three phase, four wire distribu-
tion system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
9.24 Basic three phase, six pulse, full wave rectifier circuit. . . . . . . 333
9.25 Waveforms of a three phase rectifier with a constant current
source load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
D.1 Simple single phase, half wave rectifier, with an LR load. . . . . . 362
D.2 Initial screen upon invoking SaberSketch. . . . . . . . . . . . . . 363
D.3 An example of a parts gallery screen. . . . . . . . . . . . . . . . . 364
D.4 The wire attributes window. . . . . . . . . . . . . . . . . . . . . . 367
D.5 An example of SaberSketch with the Saber guide toolbar activated.368
D.6 An example dc/transient simulation set-up window. . . . . . . . 369
D.7 The input-output table of the dc/transient analysis window. . . . 370
D.8 The initial SaberScope window. . . . . . . . . . . . . . . . . . . . 371
D.9 A signal plotted in SaberScope. . . . . . . . . . . . . . . . . . . . 372
D.10 An example of a waveform calculation in SaberScope. . . . . . . 373
D.11 Fourier analysis dialogues in Saber. . . . . . . . . . . . . . . . . . 373
H.1 Two wire transmission line and a single element model. . . . . . 401
H.2 Semi-infinite transmission line with source . . . . . . . . . . . . . 410
H.3 Plot of pulse in the time and distance domains . . . . . . . . . . 410
H.4 DC voltage transient on a transmission line . . . . . . . . . . . . 412
H.5 Voltage reflection diagram . . . . . . . . . . . . . . . . . . . . . . 414
H.6 Terminated transmission line and the equivalent circuit . . . . . 423
H.7 Thevenin equivalent circuit of a transmission line . . . . . . . . . 425
Digital Systems
Chapter 1
Logic Families
1.1 Introduction
This chapter will consider various issues related to the switching aspects of the
main digital logic families. Some consideration will be given to the internal op-
eration of the main logic families, with particular emphasis on how the internal
operation manifests itself in the terminal characteristics of logic devices.
An understanding of logic families is important in order to reliably interface
components coming from different types. In addition the switching character-
istics of the different families have implications on the design of printed circuit
boards and the noise induced on them.
introduced in the 1960s, and has now developed into several related logic families
that are compatible with each other but differ in speed, power consumption and
cost.
The other major logic family is based on metal-oxide semiconductor field
MOSFETs effect transistors (MOSFETs), more commonly known as the MOS transistor.
These devices were actually invented 10 years prior to BJTs, but did not initially
become popular due to fabrication difficulties. Many of these initial problems
were solved by the 1960s and number of products become available based on
this technology, although the performance lagged behind BJT based devices at
this time.
MOS transistor development continued through the early 1970s, and accel-
erated at the end of the 1970s and early 1980s with the development of large
scale integrated (LSI) circuits, and particularly the microprocessor. The MOS
transistor is also used in a closely associated technology known as CMOS (com-
plementary MOS). The advantage of this configuration of MOS transistors is
the low power dissipation that can be achieved. This is becoming increasingly
important as integration densities escalate, since removing the internally gener-
ated heat from ICs is a problem when there are millions of transistors on a chip.
By far the majority of electronic devices now produced use MOS transistors in
a CMOS configuration.
There is an equivalent set of SSI (small scale integrated) circuit devices
using CMOS technology. These devices have similar capabilities to their TTL
counterparts, and in many cases are designed to be input and output compatible
with TTL. In fact most VLSI (Very Large Scale Integrated Circuits) are also
designed to have TTL compatible inputs and outputs.
Depletion
Region n+ n+
Substrate
drain and the substrate. If sufficient positive voltage is applied between these
terminals then electrons are attracted under the gate area, and conversely holes
are repelled. If a large enough voltage is applied then the material under the
gate will change from p material to n material. Therefore there is an n-channel
from the two n+ wells and electrons can then flow between the two.
The MOSFET of Figure 1.1 has a p substrate. An alternative is to have a
n substrate and p+ wells. These are known as PMOS transistors . In this case PMOS transistor
a p channel has to be enhanced with the application of the gate voltage, which
implies that the gate voltage has to be negative compared to the substrate. If
the substrate is connected to the source then if VGS is zero then no current
can flow (due to a reverse biased diode being formed as in the case of the n-
channel device), and if VGS < Vt , where Vt is a threshold voltage then current threshold voltage
will flow. The circuit symbols commonly used for the n-channel and p-channel
MOSFETs are shown in Figure 1.2. Notice that the inverted input to the p-
channel MOSFET is signified in one of the symbols by an inversion circle.
The MOSFETs discussed thus far are enhancement mode devices, and they
require a voltage to be applied in order to turn the devices on. There are
MOSFET devices that are “normally-on” devices – that is they conduct cur-
rent without any applied voltage, and a voltage has to be applied to turn the
device off. These are known as depletion mode MOSFETs as the applied volt- depletion mode
age depletes an existing channel. Depletion mode devices found widespread use
in early LSI technologies where they were used for providing pull-up resistors.
However, all VLSI chip technology today is based on the CMOS circuit topol-
ogy, which does not involve the use of depletion mode devices. Therefore the
devices will not be considered any further. The main problem with the NMOS
based technology was the power dissipation due to the voltage drop across the
depletion mode MOS transistor based resistors in these designs.
6 Logic Families
{
n-channel p-channel
The concept of the threshold voltage (Vt ) was mentioned above. This is
the voltage which causes the MOSFET to conduct a significant current. From a
digital logic viewpoint the voltage which “turns on” the device is very important.
Fortunately the MOSFET designer has a number of techniques of controlling
Vt [6]. In general the threshold voltage is a function of a number of parameters
including the following:
• gate material
• channel doping
Two common techniques used for adjusting the threshold voltage entail vary-
ing the doping concentration at the silicon-insulator interface through ion im-
plantation, or using different insulator material for the gate. An example of the
last approach is to use a layer of silicon nitride (Si3 N4 ), which has a relative
permittivity of 7.5 compared to that of silicon dioxide (SiO2 ) which is 3.9. Use
of this is equivalent to using a much thinner gate insulator, and hence the gate
capacitance is increased meaning that for the same applied voltage more charge
is accumulated under the gate.
After our brief review of MOSFETs we will now return to the CMOS imple-
mentation of MOSFETs. The abbreviation CMOS stands for Complementary
Complementary Metal Oxide Semiconductor transistor . It refers to a configuration of MOS-
Metal Oxide FET transistors as shown in Figure 1.3. It is a totem pole structure in which
Semiconductor the top transistor is a p-channel enhancement mode device, and the bottom de-
Transistor vice is a n-channel enhancement mode device.1 This structure is a basic inverter
implemented in MOSFET technology.
1 The supply voltage is denoted as V
DD for historical reasons. The first MOS circuits were
based on NMOS devices where the drain was connected via a resistor to the positive supply.
The VDD voltage is often called VCC .
1.2 Review of Logic Family Properties 7
VDD
p-channel
Vout
Vin
n-channel
Logic levels and noise margins are one of the most important aspects of any noise margins
logic family in relation to interfacing members of the family together, and the
reliability of operation in the presence of noise.
One of the most important characteristics of a CMOS inverter is the transfer
characteristic . A typical characteristic is shown in Figure 1.4. Emphasis should transfer character-
be placed on the word typical, since the exact positioning and shape of this char- istic
acteristic varies depending on the IC fabrication line, width to length ratios of
the p and n transistors, doping levels, and random variations in the manufac-
turing process. However a manufacturer will guarantee certain characteristics
of the circuits they manufacture.
Figure 1.4 illustrates an aspect of digital systems that is not always appre-
ciated – a digital inverter is essentially an analogue inverting amplifier, albeit a
very high gain amplifier.2 Ideally the transition from the high to the low level
would be vertical (i.e. infinite amplifier gain) and ViL and ViH would be equal.
The noise margins of a digital device refer to the amount of electrical noise
that can be tolerated on the output of a device before the input of a following
device will see a high level as a low level, or vice-versa. The noise margins are
closely related to the transfer characteristic in Figure 1.4.
Noise margins are usually specified by two values – the low noise margin,
N ML and the high noise margin, N MH . The following discussion is with refer- low noise margin,
ence to Figure 1.5, which shows the generic definitions of logic levels. We need high noise margin
to define a few of the variables in this figure:
2 The analogue amplifier properties of inverters are used when one constructs a crystal
Slope=-1
Vout
Supply current
VDD
0.5VDD
Vin
Vtn VDD -Vtp VDD
ViL ViH
Given these definitions we can now formally define the noise margins:
Therefore N ML is the difference between the highest low level voltage that
the CMOS output produces and the highest input voltage that the CMOS input
will still recognise as a low (i.e, any higher voltage cannot guaranteed to be seen
as a low). Similarly N MH is the difference between the lowest output voltage
that can be produced, and the smallest input voltage that is still recognised as
a high input.
As an example of typical values let us consider the HC-series CMOS family
operating with a 5V supply voltage.
Using these values for the various voltage levels together with 1.1 and 1.2
one can see that N ML = 1.4V and N MH = 1.4V , which is not only symmetric
1.2 Review of Logic Family Properties 9
VDD
Logical high
output Logical high
range input
range
VOH NM H
min
VIH
min
Indeterminate
region
VIL
max
VOL NM L
max Logical low
Logical low input
output range
range
VSS or GND
IOLmax The maximum current that the output can sink in the the LOW state
while still maintaining an output voltage no greater than VOLmax .
IOHmax The maximum current that the output can source in the HIGH state
while still maintaining an output voltage less than VOHmin .
The inputs in CMOS circuits have a very low DC current loading, although
the capacitive loading can be very important under transient conditions. A
typical input current value for a HC-series CMOS gate is ±1µA.
Many CMOS data sheets will contain values of IOLmax and IOHmax for both
CMOS loads as well as TTL loads. In the case of TTL loads the noise margins
are significantly degraded relative to CMOS loads. For example, if a TTL load
is connected to HC-series CMOS devices output voltage limits are: VOLmax =
0.33V (compared to 0.1V with CMOS load), and VOHmin = 4.3V (compared to
4.9V with a CMOS load). The effect of these changes in output voltage levels
is not obvious in quantitative terms until we consider the input performance of
TTL logic.
One can also consider the behaviour of the circuits with non-ideal inputs. non-ideal inputs
This refers to a situation where the inputs are not clamped hard to the VSS or
VDD supply rails. Therefore we can have a situation where both the transistors
are both at least partially on, and therefore the outputs are created by a resistive
dividing action. If there is a current sink or source load (such as a resistive
load or a TTL input) then the situation is even more complicated in terms
of calculating the output voltage level. In addition the output transistors of
10 Logic Families
the CMOS devices will also be consuming power under these conditions. If
connected to a CMOS load there is virtually no current flowing when the logic
levels are constant, and therefore there is little power dissipation.
1.2.2.2 Fanout
fanout The term fanout refers to the ability of a logic gate to drive a number of inputs
without exceeding its worst case loading specifications. The fanout is clearly
dependent on two things – the output drive capability and the loading of the
inputs connected to the output.
As an example consider fanout of HC-series CMOS. When driving CMOS
inputs the IOLmax value is 20µA giving a VOLmax of 0.1V. The inputs for these
CMOS components have a loading of ±1µA, which implies that 20 inputs can
be connected to a low output without exceeding the maximum output voltage
low state fanout specification. This is called the low state fanout . Similarly the maximum high
high state fanout state output current is −20µA. 3 Therefore the maximum high state fanout is
also 20. This symmetry between low state and high state fanout is not usual,
overall fanout and therefore the overall fanout is the minimum of the two fanout numbers.4
DC fanout The fanout properties that we have just discussed is the DC fanout, since
we are considering constant output values. However, in some cases the so-called
AC fanout AC fanout , which is largely determined by the capacitance of the inputs and
the propagation that can be tolerated. This fanout restriction occurs due to
the RC time constant issues associated with the resistance of the output stages
of the CMOS devices and the input capacitance associated with the gate of
the inputs. Clearly as the capacitance increases then the switching edges slow
down. Therefore skew is introduced into the edges, and hence the propagation
delay of signals is increased. In addition slow edges can cause problems in noisy
environments.fine
is positive
4 The fanout can be increased if one is willing to sacrifice noise margin.
5 ‘54’ denotes a military specification component
1.2 Review of Logic Family Properties 11
CMOS only logic system. They offered higher speed and better drive capabilities
compared to the 4000-series. The input logic levels were different than those
for TTL, therefore interfacing this logic with TTL was problematic. The HCT-
series on the other hand were designed to be compatible with TTL logic levels. HCT-series
Therefore the inputs would work at the same voltage levels as those for TTL
gates.
Introduced in the mid-1980s the AC-series (advanced CMOS) and the ACT- AC-series (ad-
series (advanced CMOS TTL compatible) were very fast logic families that could vanced CMOS)
source and sink even larger currents than TTL. As with the HC-series the dif- ACT-series (ad-
ference between the two was that the ACT components were TTL input com- vanced CMOS TTL
patible. The typical AC-series components have a propagation time of 5nsec for compatible)
a NAND gate, as compared to 18nsec for the HC-series components. The price
paid for this extra performance is higher power dissipation per logic cell.
In the 1990s another even faster CMOS logic family was introduced – the
FCT-series (Fast CMOS, TTL compatible) . There are several different speed FCT-series (Fast
grades available. Compared to the AC-series this family had a significantly CMOS, TTL
better speed-power product. The other point to note was that there are not compatible)
individual gates in this family, but it tends to concentrate on chips with a
complexity equal to a 74x138 decoder or larger.
VCC = +5V
D1X
X Q3
D1Y Q4
Y D3
Q2 R6 = 4kW
D4
Z
R3 = 12kW
D2X D2Y Q5
R4 = 15
. kW R7 = 3kW
Q6
[
[
[
Diode AND gate
and input protection
Phase splitter Output stage
that the voltage at the base of Q2 cannot rise much above 1.2V . Under this
condition Q2 turns on. Depending on how hard it is on, the voltage on the
base of Q3 will drop and that on Q5 will rise. Therefore Q3 will tend to turn
off (and consequently so will Q4 ), and Q5 will be tending to turn on. The Q6
transistor is diverting current away from the base of Q5. This ensures that Q2
is turned on “hard” before there is enough current to turn Q5. This in turn
ensures that the inputs really have to be at about 2V before this will happen.
Clearly with inputs below 2V and above 0.8V it is difficult to say exactly what
will happen. This is a grey area in the operation of TTL, and the specifications
will not say what the output will be under these conditions.
push-pull The output stage of TTL is a push-pull or totem-pole output. The top
totem-pole two transistors are configured as a Darlington Pair to provide sufficient current
output and the dual diode drops across the base emitter junctions help prevent
simultaneous turn on of Q4 and Q5. The diodes D3 and D4 are provided to
discharge the stored charge in the Q4 transistor and a capacitive load, thereby
improving speed.8
Remark 1.1 A totem-pole output stage is virtually the same as the output stage
on the CMOS components. Consequently it also suffers from the problem that
there is a time during switching transients that both the top and bottom transis-
tors are on at the same time. Hence there is a spike of current that flows during
this period, which results in extra noise in the digital system. The resistor R5
8 The Q4 transistor is an ordinary transistor since it cannot go into deep saturation when
1.2.3.2 Fanout
The fanout restrictions for TTL are more restrictive than those for CMOS due
to the fact that substantial currents flow out of the inputs for TTL.
The amount of current flow for a TTL component is different depending on
whether the input is a high or low value:
IILmax This is the maximum current that an input requires to pull it LOW. For
a LS-TLL component a typical value is −0.4mA. 9
IIHmax This is the maximum input current required in a HIGH state. This is
essentially the current that leaks through the reverse biased input diodes.
Typical values for LS-TTL is +20µA.
The other aspect to the determination of fanout is the output drive capa-
bilities of the circuits. As with the inputs there is an asymmetry in the output
drive of TTL:
IOLmax The maximum output current that one can sink in the LOW state whilst
still maintaining the VOLmax output voltage. Typical value is 8mA for LS-
TTL.10
IOHmax The maximum current that can be sourced in the HIGH state whilst
maintaining a minimum output voltage of VOHmin . A typical value is
−400µA for LS-TTL.
If one examines the asymmetric input and output behaviour of TTL then it
can be seen that the LOW and HIGH fanout are the same at 20.11 LOW and HIGH
9 Thecurrent convention is that current flowing into a TTL IC is positive.
fanout
10 Because TTL can sink large amounts of current (as compared to sourcing current) it is
known as current sinking logic.
14 Logic Families
Note 1.1 The asymmetric output of TTL can cause problems in some applica-
tions. For example if one wishes to drive a LED or relay then one cannot use
current sourced from a TTL component to do this. One would have to arrange
the circuit so that the current sinking capability can be utilised. Clearly there
would be a problem driving high capacitance loads as well, since the switching
edge would be rather slow under these circumstances.
Practical Issue 1.1 Unused inputs in TTL circuits should be tied to an appro-
priate logic level (as was the case with CMOS circuits). However, if an input
pull-up resistor should be tied HIGH it is better to tie it via a pull-up resistor . In theory this is
not required, and we could tie the input directly to the VCC supply rail. However,
if the input transiently goes above 5.5V then damage to the input may result. A
pull-up resistor limits the current that can flow in this situation and prevents
damage. The value of the resistor is also important as well since the inputs take
a significant amount of current in the HIGH state. Therefore the resistor must
be chosen so that the input is well within the range of the logic value required.
One can also have a pull-down resistor. However the same overvoltage issue
does not apply so a LOW input is often tied to the GND supply. A pull-down
can be used if one wishes to drive the tied input in a testing situation, although
one is sacrificing some noise margin in order to achieve this. For example a
1kΩ pull-down resistor would give a low voltage of approximately 0.4V.
TTL designs. However, both in speed and power performance ALS has largely replaced LS.
1.3 Issues in TTL–CMOS Interfacing 15
OUTPUTS INPUTS
5.0
{ {
AC, ACT 3.76
VOH
min
AS
LS, S, ALS,
2.0 AS, HCT,
High Levels ACT
INDETERMINATE
TTL LEVEL 1.35 HC, AC
{
Low Levels
0
AS, HCT,
ACT
max
is between 4.5V and 5.5V . By comparing the output max or min logic levels
on the left side of this figure with the appropriate max or min value on the
right side one can calculate the worst case DC noise margins for the various worst case DC
logic families. Furthermore, one can also calculate the noise margins when logic noise margins
families are mixed.
One interesting case of mixing logic families is TTL and HC-series CMOS.
Recall that HC-series CMOS was not designed to be TTL compatible. The
problems can be seen by looking at the HIGH level performance. HC-series
CMOS is not guaranteed to see a HIGH until 3.85V is on the input, but TTL
outputs are guaranteed to only produce 2.7V . Even the CMOS TTL compatible
families will not produce enough voltage to trigger the HC-series CMOS input
under TTL loading conditions. Even if they did there would be virtually no DC
noise margin.
Another factor to consider is the fanout . This is especially true in the case fanout
of interfacing CMOS outputs with TTL inputs, since the latter source much
more current than CMOS inputs when held in the LOW state. Each loading
situation must be considered individually, and is dependent on the mix of logic
types. For example, the 74HC or HCT output can drive 10 74LS but only two
74S loads. Note that we are assuming the VOLmax = 0.5V for this condition,
and IOLmax = 0.8mA.
16 Logic Families
The last factor to consider is the capacitive loading of the inputs. This is
especially important when using the HC-series of components, since there is
about a 1nsec increase in rise times for every 5pF of load capacitance.
Note 1.2 With CMOS logic it is possible that poor quality inputs (e.g. a HIGH
input near 2V ) can result in both the top and bottom transistors being on to
some extent. This results in a larger than usual current flowing through the
output in steady state and therefore the IC may heat up considerably.
Practical Issue 1.3 A price that one pays when mixing TTL with a CMOS
design is the loss of noise margins. Therefore, if noise immunity is a major
issue in a design then it is better to use a CMOS logic only design, and use the
CMOS family that is designed to only work with other CMOS components (HC
or AC-series), since these have the highest noise margins.
Of course if one resorts to the HCT, ACT etc. families of CMOS then one
immediately has the noise margins of TTL. The only benefits gained are in the
power consumption area.
Chapter 2
Introduction to Digital
Switching
2.1 Introduction
This chapter introduces some of the concepts and background material required
to understand future chapters. In addition some rules of thumb will be intro-
duced, and backed up where appropriate by simulations to demonstrate the
particular effect that the rule relates to.
This chapter essentially covers a variety of issues that tend to be left out of
most digital systems courses. The chapter considers the effects that the rapid
rise times of digital signals have on the operation of digital systems. There-
fore the emphasis is on self induced “noise”, rather than externally induced
noise. This noise takes to various forms from transmission line effects through
to ground bounce and crosstalk. The approach when considering these issues is
very practical, and where appropriate suggestions are made as to how a design
can be altered to minimise problems related to high speed switching.
Much of this chapter is based on [1] which is an excellent reference on high
speed digital design.
0.5
Fknee = (2.1)
Tr
where:
1. If a circuit has a flat frequency response up to the Fknee then it will pass
a digital signal practically undistorted.
2. The behaviour above Fknee of a digital circuit will have little effect on how
it processes digital signals.
F3dB frequency at which the impulse response (i.e. the frequency response)
rolls off by 3dB
K depends on the type of pulse shape – 0.338 for gaussian pulses
and 0.35 for single pole exponential decay
frequency at which a box-shaped frequency response would pass the same amount of white
noise energy as H(f ).
2.3 Propagation, Time and Distance 19
The total delay for the transmission line is calculated using the formula: total delay
Td = l L0 C0 (2.5)
where l length of the transmission line. Clearly this means that the velocity
of propagation in the transmission line is:
1
v=√ (2.6)
L0 C0
v_pulse
initial:0 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12 1.1e-12
pulse:5 64
t_r:0.5ns
Length = 11cm
Figure 2.2 shows a series of voltage versus time plots for the ‘p’ points from
Figure 2.1. The initial input voltage has a rise time of 0.5nsec. Notice the
successive delay of the signals further down the transmission line. The total
delay can be visually seen to be approximately 800psec, which is very near the
theoretical calculation of the delay. The length of the pulse rising edge down the
transmission line is from (2.7) calculated as 7cm.
After some processing of the voltage versus time plots of Figure 2.2 one can
generate voltage versus transmission line distance plots for various times after
the application of the voltage signal. Three of these plots are shown Figure 2.3.
Notice that the voltage propagates down the transmission line, and at various
times before the voltage eventually stabilises at 5V the voltage is not uniform
2.5 Four Kinds of Reactance 21
with distance along the line. Furthermore the length of the voltage edge is ap-
proximately 6cm (compared to the theoretical calculation of 7cm for an ideal
transmission line). At 410psec the pulse has not risen to 5V because of the
500psec rise time of the input voltage (which is typical for a digital logic signal).
Remark 2.2 An ideal lumped circuit does not have any propagation delay. In
othe words the input signal is the same at all points in the lumped circuit. Clearly
no circuit behaves in this way, but if the circuit dimensions are small relative to
the length of the rising edge then the circuit can be approximated as a lumped
circuit.
• Ordinary capacitance.
• Ordinary inductance.
• Mutual capacitance.
• Mutual inductance.
Voltage source
pulse p1 p11
6.0
5.0
4.0
3.0
2.0
1.0
0.0 200p 400p 600p 800p 1n 1.2n 1.4n 1.6n 1.8n 2.0n
t(s)
Td ª 800psec
4
906psec
Voltage (V)
3
602psec
410psec
2
1
Short line
voltage
differential
0
0 2 4 6 8 10 12
Position down the tx line (cm)
Most of the features in Figure 2.4 can be deduced from the basic equation
for a capacitor:
dvc (t)
ic (t) = C (2.8)
dt
For a circuit such as that of Figure 2.4 one has an exponential rise in the
voltage across the capacitor. Assuming a infinitely fast rise time for the input
waveform the voltage across the capacitor and the current into the capacitor
can be shown to be:
vc (t) = V (1 − e− RC )
t
(2.9)
V
ic (t) = e− RC
t
(2.10)
R
Of course the waveforms are more complex when one has a rise time on
the input waveforms. Equation (2.9) can be used to find the approximate ca-
pacitance associated with a circuit by considering the time constant of a rising
signal. Of course one must know the resistance in the circuit in order to do this.
di
vL (t) = L (2.11)
dt
With the inductor in the circuit of Figure 2.5 we can write the following
expressions for the voltage across the inductor and the current through the
inductor (assuming the the rise time of the input voltage is zero):
24 Introduction to Digital Switching
R ic (t )
+
+
V (t ) C Vc (t )
-
-
V (t )
ic (t )
Voltage becomes V (t )
Vc (t )
Vc (t )
ic (t )
Starting to
Initially become an
short circuit open circuit
R iL (t )
+ +
V (t ) L VL (t )
-
-
V (t )
V (t )
Current approaches
R
iL (t )
VL (t ) Long-term impedance
is zero
iL (t )
vL (t) = V e− L
tR
(2.12)
V
iL (t) = (1 − e− L )
tR
(2.13)
R
In order to evaluate the inductance of a circuit one could again use the time
constant of the exponential rise of the current, or the exponential fall of the
voltage. These measurements are often difficult to make accurately. A better
technique is based on the area under the voltage response of the circuit. The
validity of this method is shown via the following analysis.
area under the in- Consider the expression for the area under the inductor voltage :
ductor voltage
∞ ∞
diL (t)
vL (t)dt = L dt (2.14)
dt
0 ∞ 0
Therefore one can see that the area under the inductor voltage curve is equal
to the total change in current through the inductor multiplied by the inductance
value. Hence one can write:
area
L= (2.16)
∆iL
where ∆iL = iL (∞) − iL (0).
Equation 2.16 can be further refined if we use the fact that the resistance is
known (as this test is usually carried out in a test circuit where we select the
resistance). Therefore we can write:3
∆VL
∆IL = (2.17)
R
where ∆V = vL (0) − vL (∞). This allows (2.16) to be written as:
(area)R
L= (2.18)
∆VL
Practical Issue 2.1 Equation 2.18 allows a noise free evaluation of the induc-
tance, as the area calculation effectively filters noise from the measurements.
Note 2.3 Equation (2.18) is only valid when the circuit with the inductance
has only a resistive element. If a capacitor, for example, is included then the
expression does not give the correct result.
of the loop of wire. For loops with a large diameter the inductance is a weak
function of the wire diameter (as one would intuitively reason).
In order to place this guesstimate on a more sold theoretical footing let us
consider the approximate inductance of a circular loop of wire with a loop radius
of “a” and a wire radius of “R” [7]:
8a
L = µ0 a[ln − 2] (2.19)
R
where h the height of the wire above the ground plane; d the diameter of
the wire; x the length of the wire in centimetres.
28 Introduction to Digital Switching
Field lines
Field cancellation
dvAB
im = Cm (2.23)
dt
where:
Equation (2.23) is an exact value of the current flowing through the ca-
pacitor. However, under certain assumptions one can ignore the difference in
voltages across the capacitor and assume that the current is due solely to the
voltage change in circuit A or B. If we assume that circuit A is the circuit with
the voltage change then the assumptions are:
1. The coupled current flowing in Cm is much smaller than the primary signal
current in circuit A. Therefore the capacitance does not load circuit A.
Remark 2.3 When the coupled noise voltage is less than 10% of the signal step
size these approximations are accurate to about one decimal place. This is good
enough to tell whether one has a problem with coupled noise. If the coupling is
greater than 10% then a digital circuit probably won’t work anyway.
Example 2.2 This example comes from [1]. Consider the situation in Fig-
ure 2.7, which depicts two resistors on a FR-4 printed circuit board (which is a
0.063in thick epoxy board). Note that the board has a ground plane on the non-
component side. We are interested in the coupling between the two 1/4 watt
resistors R2 and R3 . R1 is on the board to terminate the driving signal from
the pulse generator.
Consider that the signal generator drives the a 2.7V signal with a rise time
of 800ps. We can simulate this situation to get some idea of what would happen
(in [1] experimental data is presented). An approximate circuit for the situation
in Figure 2.7 is shown in Figure 2.8. This circuit has been implemented in the
Saber simulation package. If we integrate the area under the voltage across the
RB resistor then we should be able to estimate the coupling capacitance.
Figure 2.9 shows the output of the simulation with the resistors in Figure 2.8
each being 25Ω and the mutual capacitance 0.4pF. Note the plot of the integral of
the output voltage – its value is 54pV-sec. To work out the mutual capacitance
we use this value in (2.28):
54 × 10−12
Cm =
50 × 2.7
= 0.4pF (2.29)
4 We will be using the fact that im (t) = vRB (t)/RB .
2.5 Four Kinds of Reactance 31
Therefore the calculation predicts the correct value for the capacitance.
The cross coupling can be evaluated using (2.26):
RB Cm (50 × 0.4pF )
Crosstalk = = = 0.025 (2.30)
Tr 800ps
One interesting point about Example 2.2 that was not obvious is that it does
not matter where one imagines the coupling capacitor to be in relation to the
resistors. For example, if we imagine that the effective capacitor is connected
as shown by the dashed capacitor in Figure 2.8 and we carry out the same
simulation then for all practical purposes the plots we obtain as exactly the same
as those obtained for the first case. This seems counter intuitive at first since in
this configuration we have halved the amount of resistance in the circuit. There
is little difference however because it is the effective impedance of the capacitor
that is dominating the circuit. This dominance together with the ramping input
voltage effectively makes the voltage source capacitor combination behave as a
high impedance source – i.e. as an effective current source. Therefore the
current flowing in the load resistance is not effected by the change in the overall
circuit resistance.
To oscilloscope
R3
RB = 50W
From pulse Cm
generator
50W
R2
R1 = 50W
Cm
0.063in R2 R3
0.1in
Solid ground plane
The effective impedance of the capacitor to the rise edge of the voltage can
be roughly calculated by evaluating the frequency content of the edge using
(2.2). Applying this to the test waveform we find that the frequencies in the
32 Introduction to Digital Switching
R3
V
{ { R2
Cm
50W
Other parasitics
Output
voltage
50W
(V*sec) : t(s)
60p
integ(output_voltage)
40p
(1.1558n, 53.944p)
20p
0.0
(A) : t(s)
0.002
i(m)
0.001
0.0
-0.001
-0.002
(V) : t(s)
0.08
output_voltage
0.06
0.04
0.02
0.0
(V) : t(s)
4.0
input_voltage
3.0
2.0
1.0
0.0
signal go to 437.5MHz – i.e. the -3db point in the signals frequency content. If
we consider a sine wave at this frequency then the impedance magnitude of the
coupling capacitor is (using the standard impedance expression):
1
Zceff = (2.31)
ωCm
1
=
2π × 437.5 × 106 × 0.4 × 10−12
= 909Ω
which is much greater than the total resistive component of 100Ω. Hence the
current flow is governed totally by the rate of change of voltage across the
capacitor. This can be checked by calculating this rate of change and using it
in (2.8). Therefore we have:
dvcm
icm = Cm
dt
2.7
= 0.4 × 10−12
800 × 10−12
= 0.00135A (2.32)
which is the same number as can be seen in the capacitor current plot of Fig-
ure 2.9. We can assume that all the voltage appears across Cm because of its
relative impedance compared to the resistors.
Note 2.4 The above example is implicitly using the assumptions list in Sec-
tion 2.5.3. The low values of the resistors in the circuit compared to the effective
impedance of the capacitor means that the current flowing through the parasitic
element is small compared to main current flowing in the pulse generator section
of the circuit. In other words the mutual capacitance does not load down the
circuit. This is another way of reasoning that we can use the driving voltage
as the voltage across the capacitor (instead of having to calculate the voltage).
However, if the resistive impedances were significantly larger then we could no
longer use this assumption.
Note 2.5 If the coupling capacitance was to be calculated in this case then one
has to halve the circuit A voltage (to account for the grounding in this circuit)
34 Introduction to Digital Switching
and take into account the current division in circuit B. One cannot blindly
apply the integration of the output voltage technique without accounting for the
impedances in the circuits.
(V) : t(s)
3.0 input_voltage
2.0
1.0
0.0
Remark 2.4 Two circuits with mutual inductance between them is analogous to
a very small air cored transformer, where the originating circuit is the primary,
and the coupled circuit is the secondary. As in the transformer situation, the
mutual inductance coefficient has the same value regardless of which circuit is
the primary.
A mutual inductance Lm between circuit A and B injects a noise voltage vm
into B proportional to the rate of change of current in circuit A according to
the mathematical relationship:
diA (t)
vm (t) = Lm (2.33)
dt
Remark 2.5 Equation 2.33 is exactly the same equation as the standard in-
ductance equation.
Remark 2.6 Equation 2.33 demonstrates the fact that rapid changes in the
current in circuit A will induce substantial voltages in circuit B, even under
conditions of very low Lm . Hence the importance in digital circuits.
Practical Issue 2.3 In digital systems the mutual inductive coupling is usually
larger than the capacitive mutual coupling.
Figure 2.11 shows a typical situation in a digital circuit where mutual induc-
tive coupling may occur. Notice that the voltage induced effectively appears in
series with whatever voltage is being produced at the source end of circuit B.
Depending on the direction of the current the induced voltage may add to the
source voltage of circuit B, or it may subtract. Another fact that can be seen
from the figure is that current in circuit B can influence the current in circuit A
(using the same mutual inductance process). However, in the following analysis
we shall make some assumptions so that these effects can be ignored.5
One can use (2.33) to carry out mutual inductance calculations in digital
circuits under the following assumptions: assumptions
1. The voltage induced due to Lm is much smaller than the primary signal
voltage. Therefore the presence of Lm does not load down circuit A. The
noise voltage coupled to circuit B is always smaller than the signal voltage
in digital products.
2. The coupled signal current in circuit B is smaller that the current in A. We
can ignore the small coupled current in B and assume that the difference
between the primary and secondary currents is iA .
3. Assume the secondary impedance is small compared to the impedance to
ground of circuit B. The coupled voltage is added to the circuit B source
voltage, and interactions of the coupled voltage with circuit B are ignored.
Remark 2.7 The above assumptions, if true, mean that we can consider what
is happening in circuit A without having the worry about the reciprocal effects
from circuit B back into A. This greatly simplifies thinking about these effects,
and gives answers that are accurate enough to allow one to find out if there is
a mutual inductance coupling problem. The assumptions made in Section 2.5.3
in relation to mutual capacitance also allowed this to be done in that case.
5 These are similar to the assumptions made in the capacitive coupling case.
36 Introduction to Digital Switching
Circuit A
iA (t )
RA
Lm
+ vm (t ) -
Remark 2.8 Mutual inductance coupling differs from its capacitive counterpart
in that voltages of differing polarities can be induced depending on the relative
direction of the current in the primary circuit. The relative direction can be
different depending on the physical layout of the circuit. The magnitude of the
voltage is also very susceptible to the orientation of the primary and secondary
circuits.
Faraday’s Law From Faraday’s Law we know that the voltage induced in a loop of wire due
to a uniform magnetic flux density of B tesla is:
d(BA) dφ
v= = (2.34)
dt dt
where A the area of the loop through which the magnetic flux density passes.6
Equation (2.34) clearly indicates that for a given flux density that the voltage
induced in a coil is proportional to the area of the coil. Therefore, in order to
keep the mutual inductance low the loop area of the secondary circuit should
be kept as small as possible. The sensitivity of the induced voltage to the
orientation of the sending a receiving circuits can also be seen. The flux density
in (2.34), as mentioned previous is the component of the flux density that is
orthogonal to the surface of the coil area. Therefore, if the flux density has a
zero orthogonal component then the induced voltage would be zero.
Practical Issue 2.4 An approximate expression for the mutual inductance be-
tween two loops can be obtained under the condition that the separation of loops
is far enough to satisfy the following condition:
6 Note that we are assuming that the flux density is orthogonal to the surface of the loop
in this expression.
2.5 Four Kinds of Reactance 37
d> A1 (2.35)
d> A2 (2.36)
where A1 the area of loop 1 in cm2 , and A2 the area of loop 2 in cm2 and
d the distance between the loops in cm. It is assumed that the loops are parallel
to each other (i.e. the mutual inductance is maximised).
The expression for the mutual inductance is therefore:
2A1 A2
Lm ≈ (2.37)
d3
where:
diA (t) ∆V
= (2.40)
dt R A Tr
We can now calculate the mutually induced voltage appearing in circuit B:
∆V
vm = Lm (2.41)
R A Tr
The final part of the derivation is the divide by ∆V to get the inductive
crosstalk : inductive crosstalk
Lm
Crosstalk = (2.42)
R A Tr
38 Introduction to Digital Switching
Practical Issue 2.5 Similarly to the capacitive coupling case there are usually
multiple sources of coupling in practical situations. To calculate the inductive
coupling in these cases estimate the mutual coupling from each of the individual
sources and then add together the individual cross couplings to give the total.
Example 2.3 This is a similar example to Example 2.2 for the capacitive cross
coupling. The approach will be similar, in that we shall consider the coupling
between two resistors. Figure 2.12 schematically shows the test circuit. The
physical configuration of the resistors is shown in Figure 2.13. Notice that some
lines of flux density emanating from the circuit A resistor link the circuit loop
containing resistor B, and if these flux density lines change with respect to time
then a voltage will be induced in circuit B (as shown in Figure 2.12).
In this example we assume that the self inductance of the resistors is 10nH,
and the mutual inductance between them is 1nH.
The scope connection is assumed to have an impedance of RT , and con-
sequently the induced voltage is divided between the RB resistor and the RT
resistor. Usually the scope termination is 50Ω so the voltage across the scope
input will be halved.
In a manner similar to the estimation of the capacitance in the capacitive
coupling situation we can estimate the inductance using (2.18). We shall setup
a simulation of this example in the Saber simulator. The equivalent circuit is
shown in Figure 2.14.7
A plot of the important variables in the simulation appear in Figure 2.15.
Notice that the area of the voltage appearing across the load is 26.908pV-sec.
Therefore substituting this into the area section of (2.18) with the value of the
resistor R = 2RB = 100Ω and ∆V = 2.7V then we get Lm = 0.996nH ≈ 1nH.8
The inductive crosstalk can be calculated using (2.42) (remembering to use
RB + RT for the resistance):
1.0 × 10−9
Crosstalk = = 0.0125 (2.43)
100 × 800 × 10−12
The crosstalk due to the capacitance in this situation is from (2.30) 0.025/8
= 0.003 (remember the grounded resistors result in an 8 fold reduction in the
crosstalk). Hence the inductive crosstalk in this situation is four times the ca-
pacitive crosstalk.
Note 2.6 If we were physically carrying out this experiment we would not only
have the inductive coupling present, but we would also have capacitive coupling.
Due to the way the capacitive coupling test was carried out in (2.2) we have
very little inductive coupling (there is no through current in the components).
Therefore, the capacitive coupling can effectively be separated from the inductive
coupling.
For this particular situation we could therefore subtract the capacitive area/8
(remember the resistors are grounded – see Example 2.2) from the area measured
and then do the inductive calculation.
7 Note that one could easily solve this circuit analytically, but the simulation approach
allows one to play with the values and ready obtain plots. Furthermore it is analogous to
doing an experiment.
8 Note that we are using 2R in the expression since the voltage in the coil is being halved
B
due to the voltage division effect caused by the presence of the scope impedance.
2.5 Four Kinds of Reactance 39
Input
From pulse
generator
RA
Lm 50W
RB
+ v -
m 50W
To scope
Output
0.063in RA RB
0.1in
Solid ground plane
Flux density lines
Flux density linking resistor B.
field lines
L = 10nH
RB 50W RT 50W
Lm = 1nH (Scope)
L = 10nH
Remark 2.9 We have included the derivative of the current in Figure 2.15.
This is shown in order to allow comparison of this simulation with a later one
where load capacitance has been included in the modelling.
Practical Issue 2.6 In most high speed digital systems the inductive coupling
is more significant than the capacitive coupling. The reason for this has not been
answered in this section, but will be given in Section 2.6.2.
Practical Issue 2.7 Given two logic families with identical propagation delays,
the logic family with the slowest output switching times will be easier and cheaper
to use.
In recognition of these facts some more recent logic families now incorpo-
2.6 Speed of Digital Systems 41
Inductive coupling
(A/s) : t(s)
80meg
60meg (880.7p, 65.891meg) deriv(i(l.l1))
40meg
20meg
0.0
-20meg
(A) : t(s)
0.06
i(l.l1)
0.04
0.02
0.0
(V*sec) : t(s)
0.0
(2.0486n, -26.908p) integ(output)
-20p
-40p
(V) : t(s)
0.02
output
0.0
-0.02
-0.04
(V) : t(s)
4.0
input
2.0
0.0
rate circuitry to slow down the switching edges to acceptable levels.9 Prior to
this the switching edges were largely uncontrolled. For example, a technology
in the early 1980s for output drivers on high speed logic circuits was VMOS.
These output devices had very fast switching times, but they made it extremely
difficult to build a printed circuit board that would work.10
0.5
Fknee = (2.44)
Tr
Therefore as the rise time becomes smaller, then the frequencies which the
circuit has to cope with increase. Therefore, all data paths, integrated circuit
packages and physically layout has to be able to function with frequencies up
to this value. As noted in (2.26) and (2.42) both the capacitive and inductive
crosstalk are inversely proportional to the rise time of the voltage (Tr ). Since
crosstalk is a relative measure then it is independent of ∆V . Therefore the
T10−90 edge time is the really important value and not ∆V .
v(t) dv(t)
i(t) = + C (2.45)
R
dt
Resistive current Capacitive current
In order to calculate the effect that this current has on the inductances in
the circuit we have to differentiate (2.45) with respect to time:
9 In fact circuitry of this nature was introduced in the MECL 10K family in 1971, but is
wasn’t until 1990 that it was introduced into the more common FCT CMOS family.
10 This was especially true in the early 1980s as there were no such things as 4 layer printed
i(t )
v(t ) R C
(A/s) : t(s)
200meg
deriv(i(l.l1))
100meg
(A/s)
0.0
-100meg
(A) : t(s)
0.1
i(l.l1)
0.08
0.06
(A)
0.04
0.02
0.0
(V) : t(s)
0.04
0.02 output
0.0
(V)
-0.02
-0.04
-0.06
-0.08
(V) : t(s)
3.0
input
2.0
(V)
1.0
0.0
VCC
Totem pole output
drivers
SW A Output circuit
vin +
-
SW B
+
LGND idischarge C
vGND Ground pin
inductance
-
Ground Plane
This induced voltage shifts the internal ground reference from the board
ground plane. It is this phenomena that is called ground bounce. The voltage
vGN D is usually small compared with the output voltage swing and does not
significantly impair the transmitted signal. However, it can have dramatic effects
on the reception of signals.
Note 2.8 In Figure 2.18 we can see that the input circuit is sensing the input
voltage relative to its own local ground rail (as emphasised by the differential
amplifier representation of the input circuit). This situation is representative of
the TTL logic family. Other logic families (e.g. ECL and GaAs) compare the
46 Introduction to Digital Switching
input to VCC . CMOS circuits tend to compare inputs against a weighted average
of VCC and ground.
The other important issue in relation to the references is the reference for
the outputs. In the case of TTL if the output is high then the output reference
is VCC (since the bottom output transistor is open circuit), and when the output
is low then the reference is the 0V rail. Note that the output reference does not
necessary match the input reference, and this must be carefully considered when
looking at the effects of noise on the ground and VCC rails.
Consider the situation depicted in Figure 2.18. The input voltage seen on
across the differential input amplifier is:
vin = vin − vGN D (2.48)
In this equation vGN D can be either positive or negative depending on the
direction of the current through the ground lead inductance. From the point
of view of the input the noise voltage across the lead inductance is effectively
superimposed on the input voltage.
If there is only one output switching then ground bounce should not cause
a problem. However, in an IC with N outputs switching at the same time
then the problem will get N times worse. Further exacerbation can occur if
the N outputs are driving capacitive loads, since as noted in Note 2.7 the rate
of change of current increases under these conditions. This leads to a double
humped waveform in the ground bounce voltage, as can be deduced from the
current derivative waveform in Figure 2.17 (since v = Ldi/dt).
Propagation
delay Time B Time C
Time A
3nsec Time D
After clock glitch
outputs may switch
to another state
Q outputs FF 00 XX
Data bus FF 00 XX
3nsec setup
1nsec hold
Clock
VGND
Clock - VGND
Glitch at Time D
clocks XX into
the latches
Figure 2.19: Example waveforms for an octal latch driving a capacitive load.
48 Introduction to Digital Switching
For a resistive load the voltage induced in the lead inductance is obviously:
LGN D ∆V
|vGN D | = (2.49)
R T10−90
If we have a capacitive load, and assuming a gaussian shape for the derivative
of the input step, then it is possible to show that the rate of change of current
is [1]:
dic d2 v ∆V
= C 2 = 1.52C 2 (2.50)
dt dt T10−90
and hence the voltage induced is:
∆V
|vGN D | = 1.52LGN D C 2 (2.51)
T10−90
Typical values for switching times and voltage swings for common logic fam-
ilies appear in Table 2.2.
Some other components attack the problem by bringing out a separate wire
internal reference for the internal reference. An example of a family that does this is the 10K
ECL family. This separate pin does not carry the large ground currents and
therefore does not suffer ground bounce. Differential inputs are an even more
effective technique to achieve the same end.
If one is prepared to embrace more radical packaging technologies then the
lead inductance can be decreased considerably. The most promising techniques
are wire bond, tape automated wire bond (TAB) and flip-chip. All of these
techniques involve mounting the chip directly on the printed circuit board – i.e.
the lead inductance has been eliminated by eliminating the package.
Wire bonding is a technique akin to the bonding technique used in the current wire bonding
integrated circuit packages. The IC is placed back side down on the printed
circuit board, and one the top side there are a number of small pads on the
chip. Very fine wires are then bonded to these pads and then bonded to a
corresponding connection on the printed circuit board. The IC and the wires
are covered with a covering material and then the whole lot is hermetically
sealed with a lid. This technique has the capability of hand production for
small volumes.
Tape bonding is an enhancement of the wire bonding technique. It uses a tape bonding
flexible circuit with wire tapes on it. This flexible circuit may have multiple
layers, including a ground to control impedances. This is overlaid on the IC so
that the wire tapes align with the IC pads (which have solder balls on them) and
the printed circuit board connections. The tape wires are then reflow soldered
to the IC and the printed circuit board and the whole lot sealed as in the
wire bonded case. Therefore this technique improves on the wire bonding by
providing a much faster technique of connecting the wires all at once. The multi-
layer capability also improves the signal transmission. The disadvantage of the
technique is that the flexible circuit must be changed if there is any change to
either the IC or the printed circuit board connection points.
The flip-chip technique places solder balls on each chip attachment pad. The flip-chip
chip is then placed face down on the printed circuit board and directly reflow
soldered in place. This technique is often using in ceramic multi-chip structures
that incorporate advanced cooling techniques. The whole device is hermetically
sealed. From the inductance viewpoint this technique is excellent, as the lead
inductances are almost totally eliminated. However, from a mechanical and
thermal viewpoint it has some deficiencies. The differing thermal expansion
of the IC and the printed circuit board can cause undue stresses on the IC.
The only compliance in the set up is the solder balls. Furthermore the IC can
become hotter because it is held off the printed circuit board by the solder balls.
The wire bond and tape bond techniques had the back of the IC contacting the
printed circuit board (usually glued to it), this offering a heat sink.
Table 2.3 shows typical values of the lead inductance for a variety of package
types.13
mutual capacitance CM is the mutual capacitance between the pins. One may compute the crosstalk
in circuit 2 from the rising edge in circuit 1 by using the expression (2.26) and
realising the RB value is 75/2Ω, since the transmission line and termination
resistances are in parallel. Therefore we have:
RCM (37.5Ω)(4pF)
Crosstalk = = = 0.03 (2.52)
Tr 5nsec
which is 3% cross coupling. This situation becomes significantly worse if the rise
time decreases, or if the impedance of the circuit coupled to increases. One way
of alleviating the problem with higher impedances is to add capacitance to the
lines with the high impedance so that the impedance is lowered at high frequen-
cies. However, whilst this may solve the capacitance cross coupling problem, it
may exacerbate ground bounce problems in some circumstances.
Table 2.4 shows the typical values for the inter-pin capacitances for common
logic packages.14
C M = 4pF
VCC
2 Transmission line
Z 0 = 75W
75W termination
t1 t12 + t 22 t12 + t 22 + t 32
Input Response of the Composite response
probe to input of probe and vertical
amplifier
pulses)15 :
1
Trcomposite = (T12 + T22 + · · · + TN2 ) 2 (2.53)
1
F-3dB = (2.54)
2πRC
15 Although this is only exact with gaussian pulses, other pulse shapes give almost the same
result.
52 Introduction to Digital Switching
0.35
T10−90 =
F-3dB
= (0.35)(2πRC)
= 2.2RC (2.55)
Example 2.4 This example is taken from [1]. A person buys an oscilloscope
rated at 300MHz bandwidth with a probe at 300MHz bandwidth (both are −3dB
bandwidths). How does this combination affect signals having a rise time of
2nsec?
Assuming the pulses are gaussian in nature then we can compute the rise
time of each of the components as:
0.338
Trprobe/scope = = 1.1nsec (2.58)
300M Hz
Trsignal = 2nsec (2.59)
Therefore this oscilloscope will display the 2nsec input signal as a signal with
a rise time of 2.5nsec.
Source
resistance Probe input
capacitance and
RS resistance
{
+
To
vS C in Rin scope
-
L
The presence of the inductance in the probe lead has several significant
affects on the performance of the CRO. Firstly, the input circuit has a rise time
associated with it. Recall (2.57) for the RLC rise time. In order to use this
expression we need a representative value for the probe inductance. In order
to obtain this assume that we have a earth clip loop of width 2.54cm (1in) and
length 7.62cm (3in) with American Wire Gauge (AWG) 24 wire which has a
diameter of 0.0508cm. Substituting these values into (2.21) we have:
2 × 7.62 2 × 2.54
L ≈ 4 2.54 ln + 7.62 ln
0.0508 0.0508
= 198nH ≈ 200nH (2.61)
Therefore the intrinsic rise time of the probe is (assuming critical damp-
ing)16 , using (2.57):
√
T10−90 = 3.4 LC = 3.4 (200nH)(10pF) = 4.8nsec (2.62)
This rise time spells trouble. We calculated in (2.58) that the rise time of the
CRO itself was 1.1nsec. Therefore the presence of the probe inductance has
severely degraded the rise time (and hence bandwidth) of the measurement
system.
The other interesting aspect of the circuit shown in Figure 2.22 is that it is
a resonant circuit. Therefore it will have a quality factor (given the symbol Q). resonant circuit
16 An overdamped circuit rise time is even slower than the critical damped rise time, but an
For a series circuit the expression for Q is (see Appendix G for a summary of
second order series and parallel RLC circuits):
1 L
Q= (2.63)
RS C
It should be noted that Q is the ratio of the total stored energy in the system
to the energy lost per radian. A very high Q circuit for example would have
a very low value of resistance, meaning that the losses are very low. Such a
circuit would tend to resonant for long periods of time. In the particular case
of the CRO probe it is clear that the Q will be very dependent on the source
impedance of the particular logic gate driving the probe.
Let us consider the frequency response of the probe circuit. Using simple
transfer function circuit analysis one can deduce that the transfer function is:
vin Rin 1
= (2.64)
vs Rs + Rin 1 + CinRRs +R
in Rs +L
in
s + CRin LRin 2
s +Rin
s
If we plot this transfer function over the area of the frequency response of interest
we get Figure 2.23. As one can see the peak of the resonance is very dependent
on the value of the source resistance. Clearly if the input signal has energy at
a frequency of approximately 700Mrad/sec (or 110MHz) then there is going to
be some oscillations in the output. Therefore this limits the rise time to avoid
oscillations to:
0.5
Tr > = 4.54nsec (2.65)
110MHz
Note 2.9 This particular rise time limitation is purely a product of the partic-
ular lead inductance-input capacitance combination.
time domain re- Let us consider the time domain response of the CRO probe equivalent cir-
sponse of the CRO cuit. Whilst one can analytically evaluate the response from the transfer func-
probe tion, a experimental/simulation approach has been opted for.17 A Saber sim-
ulation has been set up of the circuit, with the previously mentioned input pa-
rameters for the probe (Cin = 10pF, L = 200nH, Rin = 10M Ω) and the source
resistance of 30Ω (which is equivalent to a TTL output source resistance). The
plot of the input voltage to the CRO appears in Figure 2.24.
As can be seen from Figure 2.24 the response seen by the CRO input is
very oscillatory due to the presence of the LC circuit. Also note that with the
resistance of the TTL source the Q in the circuit is quite high. In fact to get to
a critically damped circuit the value of the source resistance has to be closer to
282Ω. With this value of resistance the rise time of the circuit is very near that
calculated in (2.62).
Practical Issue 2.8 The response of a CRO probe can have a very important
effect on the observed waveforms.
Remark 2.11 The scope ground undergo very large voltage excursions in Fig-
ure 2.24. It is this “ground bounce” that is the source of the scope display
problems.
17 The simulation approach will be used repeatedly throughout these notes as it simulates
5W
30W
30
20
100W
10
Magnitude:dB
0
-10
-20
-30
-40
-50
Phase:deg
-100
-150
8 9 10
10 10 10
Frequency (rad/sec)
Ground bounce
(V) : t(s)
10.0
(output-scope_gnd)
8.0
6.0
(V)
4.0
2.0
0.0
(V) : t(s)
4.0
scope_gnd
2.0
(V)
0.0
-2.0
-4.0
(V) : t(s)
6.0
input
4.0
(V)
2.0
rise: 1.8377n
0.0
Figure 2.24: Response of the CRO probe equivalent circuit with the input rise
time of 1.8nsec.
2.6 Speed of Digital Systems 57
The other interesting thing to look at with this circuit is what happens when
we slow down the input edge. We calculated in (2.65) that if the rise time was
greater than 4.5nsec that the circuit oscillations would become substantially
smaller. If we redo the same simulation as shown in Figure 2.24 but with the
rise time of the input equal to a 5.5nsec T10−90 rise time we get the plot of
Figure 2.25. Notice that the oscillations are substantially less in this figure,
and one could say that the scope is now producing a much more acceptable
waveform.
Ground bounce
(V) : t(s)
8.0
(output-scope_gnd)
6.0
(V)
4.0
2.0
0.0
(V) : t(s)
1.0
scope_gnd
0.0
(V)
-1.0
-2.0
(V) : t(s)
6.0
input
4.0
(V)
2.0
rise: 5.5469n
0.0
Figure 2.25: Response of the CRO probe equivalent circuit with the input rise
time of 5.5nsec.
If we slow the edge even more then the overshoot continues to decrease. If
the rise time is about 10nsec then the scope input waveform has virtually no
overshoot.
Remark 2.12 In summary, we can see from this section that the presence of
the CRO probe ground lead and clip has dramatic effects on the effective rise
time of the probe, and dramatically effects the observed waveforms – particularly
in relation to the overshoot observed on the edges.
Table 2.5 lists the Q and rise times for TTL logic and ECL logic. It is
assumed that the source resistance for these logics are 30Ω and 10Ω respectively.
58 Introduction to Digital Switching
Ground loop
inductance
(nH) T10−90 QTTL QECL T10−90 QTTL QECL
Table 2.5: Rise time and Q for 10pF and 2pF capacitance probes for various
inductances.
Another effect from having a probe lead connected is that it acts as a pick up
electrical noise for electrical noise . This noise cannot be distinguished from noise on the signal
being observed. The main mechanism for this noise pick up is magnetic mutual
magnetic mutual coupling between the loop of the probe lead and another loop in the circuit
coupling being probed. The orientation of the two loops is important in determining
the magnitude of the observed noise voltage – as noted in Section 2.5.4 if the
areas of the loops are such that there is no component of the flux from one loop
orthogonal to the area of the other loop then the mutually induced voltage is
zero.
In a practical situation the loop generating the interfering magnetic field is
generally a loop consisting of printed circuit board tracks running to and from
an integrated circuit that is driving some load (usually with some capacitance).
Figure 2.26 illustrates this particular situation. As can be seen from the diagram
some of the magnetic field produced by the signal and ground return current in
a nearby integrated circuit is coupled to the loop represented by Loop B. If the
orientation of the loops is such that this field is orthogonal to the area of Loop
B then there will be a mutual inductance between the two loops and hence,
depending on the rate of change of the magnetic flux density, a voltage will be
induced in the CRO lead.
One can get a rough estimate of the magnitude of the induced voltages in
this situation by using (2.37) together with the rate of change of current and
(2.11).
Example 2.5 Consider the situation where Loop A in Figure 2.26 is 0.7cm ×
0.7cm and Loop B is 2.5cm × 7.5cm. The loops are separated by 5cm. If we
2.6 Speed of Digital Systems 59
Loop B
Magnetic field
lines from Loop A
to Loop B
Loop A
1. Standard 10× probe with 10pF and 10M Ω input capacitance and resis-
tance respectively.
2. A 10× FET active input probe with 1.7pF and 10M Ω input capacitance
and resistance respectively.
3. A passive probe with 0.5pF and 1000Ω input capacitance and input impedance
respectively.
The equivalent circuit we are using is shown in Figure 2.27. Notice that there
is no inductance in the ground of the circuit. This means that we are assuming
the the ground shield of the probe is connected directly to the ground plane of
the circuit under test (and the ground inductance is therefore negligible).
Source
resistance Probe input
capacitance and
RS resistance
{
+
vin
vS C in Rin To
scope
-
and similarly the input impedance transfer function can be written as:
Rin
Zin (s) = (2.69)
1 + sCin Rin
Plotting these transfer functions for the above mentioned probe parameters
and Rs = 50Ω we get Figures 2.28 and 2.29.
Remark 2.13 It can be seen from Figure 2.28 that the standard 10M Ω, 10pF
probe causes a substantial roll-off in the source to probe input transfer function
for rise times smaller then 3nsec.
62 Introduction to Digital Switching
0
-2
-4
vin dB
-6
-8
-10
0
Phase:degs
-20
-40
-60
7 8 9 10
10 10 10 10
314ns 31.4ns 3.14ns 0.314ns
Frequency (rad/sec)
Rise Time
Figure 2.28: Source to probe input transfer function for a CRO probe.
. pF
100,000
10,000
1000
100
7 8 9 10
10 10 10 10
314ns 31.4ns 3.14ns 0.314ns
Frequency (rad/sec)
Rise time
Remark 2.14 The active FET probe and the very low capacitance passive probe
have good frequency response characteristics, and will handle frequencies into
the 500MHz plus range of operation (which corresponds to rise times of approx-
imately 1nsec or less).
Remark 2.15 The reason for the poor performance of the standard 10M Ω,
10pFf probe can be seen from Figure 2.29. The input impedance of the probe
falls to levels of approximately 100Ω when the input signals have a rise time
of approximately 3nsec. Therefore the input impedance is placing a substantial
load on the circuit when there is a 50Ω source resistance (which is typical for a
digital circuit).
Practical Issue 2.10 For the loading to be small the input impedance magni-
tude needs to be approximately 10 times the source impedance.
The most important component of a probes input when it comes to its loading
effects at high frequencies is its capacitance.
Remark 2.16 The home brew probe approximates the circuit of Figure 2.31.
Notice that in this probe the capacitance is parallel to the 1000Ω resistor, and
this combination is in series with the input impedance of the50Ω coaxial cable. In
addition there is the source resistance RS which represents the output impedance
of the driving gate.
The frequency response of this probe, instead of having a pole, has a zero and
pole produced by 1000Ω in parallel with CS and in series with the gate output
impedance RS . If CS is very small then the zero will be at a very high frequency.
The CS capacitor is the parasitic capacitance across the 1000Ω resistor, and is
usually ≤ 0.5pf.
The fact that the frequency response contains a zero, is itself, a better char-
acteristic. This will mean that the higher frequencies are emphasised, rather
than attenuated.
The total input impedance into this probe is 1000Ω + 50Ω = 1050Ω. The
coax looks resistive, therefore the only capacitance is associated with the shunt
64 Introduction to Digital Switching
To 50W
termination at
scope
1000W
50W
Sense ground
loop
Transmission line
impedance
CS
RS
1000W 50W
capacitor between the ends of the resistor, which is typically about 0.5pF for
a 1/4 watt resistor (this can be lowered by using a 1/8Watt resistor, but one
must be careful about power dissipation with this).
The input voltage is undergoing voltage division, and the ratio is:
50
vscope = vs = 0.048vs (2.70)
50 + 1000
Therefore with the scope set to 50mV/div the vertical sensitivity is 0.05/0.048
= 1.04V/div. One can use the vertical sensitivity to tweak the vertical scaling
to 1V/div if necessary.
The advantages of this probe are: advantages of this
probe
• The DC input impedance is 1050Ω with makes the loading on a 25-75Ω
source small.
• The shunt capacitance is very small meaning that the loading does not
change dramatically until very high frequencies.
Remark 2.17 The price one pays with this probe is that the voltage range is
severely limited due to the high attenuation of the probe. This may be a prob-
lem with many analogue signals, but the most common digital signals have high
enough voltage values that this is not a problem.
One would not normally think of a connector having a rise time. For slow
signals it effectively hasn’t a rise time, but at the frequencies being dealt with in
high speed digital systems the rise time can be significant. The rise time arises
from the series inductance introduced in the 50Ω at the point where the shield
spreads out away from the centre conductor to connect to the BNC fitting.
Table 2.6 shows the series inductance associated with several types of coax
connectors and the T10−90% time constant that goes with these inductances. If
the coax cable has to be terminated at the scope then one should ensure that a
good quality termination is used, else there will be further rise time degradation.
The next part of the propagation path of the signal in the probe is the coax
cable itself. A coax cable has a frequency response – i.e. there is a frequency at
66 Introduction to Digital Switching
which the attenuation in the cable is 3.3dB, this corresponding to the frequency
knee point. Therefore we can apply (2.1) to find the rise time. However, in
the case of coax cables this expression only works for short lengths of cable.
Note that at high frequencies the attenuation is proportional to the square root
of the frequency, and this fact can be used to interpolate between attenuation
points in the cable manufacturers catalogues. Table 2.7 shows the rise time
characteristics for some common cables.18
The final section of the signal propagation path that we are interested in
is the probe sense loop. This loop introduces inductance to the signal path,
in a manner similar to that introduced by the probe lead in Section 2.6.5.2.
However in this case the 1000Ω resistance dominates the impedance of this
path and this decreases the influence of the inductance substantially. This can
be seen quantitatively by considering the time constant of the loop, L/R. For a
given L then the time constant is reduced for a large R. This effect can be seen
in Table 2.8.
rise time of our We are now in a position to calculate the rise time of our home brew probe.
home brew probe Assume that we have built a probe with 5 feet of RG-174 double-crimped BNC
connector and a probe loop of 12mm. Considering Tables 2.6, 2.7 and 2.8 we
can develop the expression for the rise time of the probe as:
2
Trcomposite = (TBNC )2 + Tcable 2
+ Tloop
= (0.011)2 + (0.088)2 + (0.06)2
= 0.107nsec (2.71)
18 These figures are taken from [1], where the lengths are quoted in imperial measurements.
2.6 Speed of Digital Systems 67
Rin Rs
(Cs + Cin ) = Cs Rs (2.73)
Rs + Rin
If pole-zero cancellation is achieved then the frequency response of the speed- pole-zero cancella-
up circuit would look like Figure 2.33. tion
CS
RS
vS Rin C in vin
Magnitude dB
1 + sC S RS
Resultant response
1 + s(C S + C in )
LM R R OP
in S
NR + R Q
in S
log10 f
Figure 2.33: Ideal frequency response for a correctly compensate speed-up cir-
cuit.
2.6 Speed of Digital Systems 69
Curly wires
Scope
probe
Ground
Signal
Figure 2.34: Use of wire connection to lower sense loop inductance.
Scope probe
Sleeve
Printed circuit
board (PCB)
large extent alleviated this problem, although the loading could still be impor-
tant in certain applications. Another approach is to build correctly designed
test points test points into a circuit a design time. These test points ensure that when the
circuit is probe the loading does not change, and consequently the signals seen
when probing will be exactly the same as the signals when the probe is not
present.
Figure 2.36 shows the general arrangement of an on-board probing set up.
Effectively a home brew probe has been built onto the PCB, and the user can
use a link to connect an on-PCB probe load to the signal, or connect the actual
probe cable.
Signal to other
parts of the circuit
Ground
via 50W terminator
To
RG-174 50W coax
scope
When a CRO is connected to a digital system we connect two leads – the sense
lead and a ground lead. The sense lead is usually the centre conductor of a coax
cable and the ground lead is connected to the shield of the coaxial cable. Let
us consider the ground lead – it is usually connected to the CRO ground and
to the digital system ground. The CRO ground in turn is usually connected to
the power supply ground via the ground wire in the power cable to the CRO.
Figure 2.37 shows this configuration. In this figure the sense wire and shield
connection are connected together at the digital system. With this configuration
there would be no voltage registered on the scope if no shield current is present.
If there is a current, then the voltage that is on the scope is the shield voltage,
Vshield .
shield voltage The shield voltage is induced in the shield due to a shield current causing
a resistive voltage drop across the resistance of the shield. This current results
from the different ground potentials between the digital system and the scope.
These different ground potentials can be caused by a variety of influences –
2.6 Speed of Digital Systems 71
Scope
Vshield
Digital vin +
-
System
for example large currents flowing elsewhere in other equipment can cause such
ground differences.
Note 2.10 The shield voltages are a result of the shield resistance, and not
the shield inductance. Because of the coaxial nature of the cable the inductance
induced voltage in the shield and the sense conductor are the same, and therefore
no difference voltage will appear at the CRO amplifier. However, the currents
due to ground differences only flow in the shield, and this lack of balance between
the shield and the sense conductor will result in a voltage at the CRO amplifier.
Figure 2.38 shows the general arrangement for differential probing. Notice
that the shields are connected together at both ends, but one end of the shield
is not connected to anything. Therefore there cannot be a path for the shield
2.6 Speed of Digital Systems 73
current. With this configuration the input amplifiers each measure the noise
voltage, but the subtraction of the two signals effectively eliminates this. Most
dual or more channel CROs offer the option of being able to subtract the signals
of two of the input amplifiers. Any differences between the amplifiers can be
eliminated by tying the signal wires to a common point and then tweaking the
gains until no signal is seen.
Scope
Sense
loop + +
-
1 2 S
Probe
Pro
be +
- -
Digital
System
Noise +
Ground strap Green wire
voltage - safety ground
The twisting of the probe cables together is to ensure that any magnetic
pick-up is the same on both cables, this then being seen as a common mode
signal and being eliminated. The ground strap is necessary if the digital system
is floating with respect to the true earth ground. It is to make sure that the
voltage of the digital system does not float above the common mode range of
the CRO input amplifiers.
The effectiveness of the differential probe technique depends largely on the
performance of the input amplifiers. The common mode rejection ratio of dif-
ferential amplifiers is frequency dependent, and sometimes does not go to very
high frequencies. However, this technique would be very effective at eliminat-
ing shield currents up to several hundred kilohertz without any difficulty for
most CROs. High frequency rejection would dependent on the CRO amplifier
common mode bandwidth.
74 Introduction to Digital Switching
Chapter 3
According to the Section 2.4 states that if line lengths are < lr /6 then we can
consider the lines to behave as lumped circuits and distributed line effects can be
ignored. In this particular case lr = 3.9in, therefore the designers thought that
4in was close enough to regard the line equivalent circuits to be lumped circuits,
and transmission like effects would not be significant. The designers therefore
mistakenly thought that the circuit would not ring because there would not be
any transmission line effects.
The reader of these notes will be aware that a lumped circuit can ring if it
contains capacitive and inductive elements. This is not a sufficient condition for
ringing though – the Q (known as the Quality Factor) of the circuit is crucial as
to whether ringing will occur (see Appendix G for a definition and derivation of
expressions for Q). If Q < 0.5 then the circuit is over-damped and no ringing
will occur, if Q = 0.5 then the circuit will not ring, but it has the fastest step
response without ringing (called critically damped), and if Q > 0.5 then the
circuit will have overshoot and ringing. The larger the value of Q the greater
the overshoot and the longer it takes for the ringing to die out.
It was shown in Appendix G that the maximum overshoot in a second order
circuit with Q > 0.5 is:
Vovershoot − √ π
4Q2 −1
=e (3.2)
Vstep
where Vstep the input step (in other words the expected steady state response).
One can plug some numbers into this expression and we get for Q = 1 that
the overshoot is 16%, for Q = 2 the overshoot is 44%. It should be noted that
these are the figures obtained for an ideal step input. We shall see that the
degree of ringing experienced by a circuit is a function of the rise time of the
input signal and the natural ringing frequency of the circuit.
In order to work out the equivalent circuit of the wire wrap wiring we need
to know the inductance, capacitance and effective resistance of the wiring and
IC drivers. The inductance of the wires can be calculated using (2.22) for a
average net length:
4h 4 × 0.2in
L = 2x ln = 2 × 2.54 × 4in × ln = 89nH (3.3)
d 0.01in
The other relevant parameters for this circuit are R = 30Ω (the typical output
resistance of a TTL or CMOS gate – see Section 2.6.5.2), and a typical input
capacitive load is C = 15pF. Therefore:
1 L 1 89nH
Q= = = 2.6 (3.4)
Rs C 30 15pF
For an instantaneous step the overshoot can be calculated using (3.2) as:
− √ π
where Vstep = 3.7, assuming that this is being produced by a lightly loaded TTL
output.
3.1 Shortcomings of Point-to-Point Wiring 77
The resonant and natural resonant frequency of this particular circuit are
(see Appendix G):
1 1
Fresonant = √ = √ = 137.7MHz (3.6)
2π LC 2π 89nH × 15pF
2
1 1 R
Fnatural resonant = −
2π LC 2L
1 1 30
= − = 135MHz (3.7)
2π 89nH 2 × 89nH
and:
1
Fknee = (3.9)
2Tr
If Tr = Tperiod /2 then:
Fknee = Fresonant (3.10)
Therefore if the rise time of the input is greater than half the period of the
natural resonant frequency then the oscillations will be small. If, on the other
hand, the rise time of the input is shorter than the natural resonant period then
the oscillations in the circuit will be significant.
In conclusion, the wire wrap board built by our Silicon Valley company had
significant ringing problems.
from the ground plane, and this also limits the area and provides a degree of
field cancellation. For example, if one has a track on a ground planed printed
circuit board, with the track separated from the plane 0.005in, it will radiate
32dB less field energy per wire compared to the situation in a typical wire wrap
board, where the wire is 0.2in above the ground plane.
If one is building a wire wrap board it is very important to get the wires as
close to the ground plane as possible. Unfortunately this is not always possible.
3.1.2 Crosstalk
We have previously discussed crosstalk in general (both capacitive and inductive
– see Sections 2.5.3 and 2.5.4). The bottom line in relation to inductive mutual
coupling was, that if one has conductors close together with large loop areas,
then there will be significant coupling between them. The other main conclusion
is that inductive coupling is usually more significant than capacitive coupling.
In this particular case, as discussed in the previous section, the wiring loops
are relatively large. Therefore one would expect significant mutual coupling.
Let us now generate some numbers to verify this assertion. Assume that we
have two average length wires on the board running parallel to each other. If
we apply (2.38) we can write for the mutual inductance between the wires as:
1
Lm = L 2
1 + hs
1
= 89nH 2 = 71nH (3.11)
1 + 0.2
0.1
This value of mutual inductance is very high – it is not much different from the
self inductance of the wire, which means that a lot of the flux density lines of
one wire loop are linking to the other wire loop.
To work out the crosstalk in this situation we need to use the expression
(2.50) for di/dt when there is a capacitive load:
Note that we are using 3.7V as a step TTL input, and then adding the maxi-
mum 2.0V overshoot. In addition the rise time of the signal is the rise time of
this overshooting signal, which we are estimating to be the time to the initial
maximum overshoot, which from (G.35) is 3.6nsec.
The crosstalk is:
vm di
Lm dt 71 × 10−9 × 1 × 107
= = = 0.19 = 19% (3.13)
Vsteady state Vsteady state 3.7
Note that we have used the normal steady state value of the voltage in the
denominator in this expression rather than the overshoot value.
A crosstalk value of 19% is very large. In absolute terms this is 0.7V, which
is almost the switching level of TTL. With this amount of crosstalk this circuit
will not work. It should also be noted that the above calculations are for a
single wire. If one has a bus system on the board then the crosstalk will be
3.2 Uniform Transmission Lines 79
additive from each wire. This fact also leads one to realise that bundling wires
together in bus structures so that they look nice on a wire wrap board is not
a good idea. It is better to wire the wires directly from point to point so that
there is a randomness to their relative orientation.
With all the problems cited in this section in relation to the performance
of this board it is not a surprise that the company in question never got it to
work, and had to abandon this approach and build a prototype printed circuit
board.
Remark 3.1 The wire wrap circuit example above has been presented to show
the pitfalls of point to point wiring. Given the fast rise-time of modern digital
devices, point to point wire wrap wiring should no be used.
Remark 3.2 The properties of the ideal transmission line are fascinating. As
shown in Appendix H transmission lines can be modelled as LC circuit elements,
which normally form frequency selective networks. However, when they are
connected together in a distributed fashion (as in a transmission line) then the
delicate balance between the inductance and capacitance of the line leads to the
effective impedance of the line appearing to be resistive. Because a resistor is not
a frequency selective component then the line has an infinite frequency response.
Dielectric
Outer jacket
Outer shield Ground plane
Inner dielectric
Inner conductor
the inductance of the cable we short circuit one end of the cable, and again using
a good quality measurement bridge we are able to measure the inductance of
the cable length. In this particular case this turns out to be 50.4nH. We can
also measure the resistance of the cable with this configuration if we have access
to a high sensitivity resistance bridge. To get the per unit length values simply
divide by the length of the cable.
L = 20cm
Leave end of
line open
Measure
capacitance C = 24pF
here C/cm = 1.2pF
L = 20cm
t0 t1
Time delay = t1 - t 0 = (Y - X ) LC
We can work out the current required to charge this capacitance if we know
the time that it takes for the waveform to traverse this region. As shown in
Figure 3.3 this time is: √
td = (Y − X) LC (3.17)
therefore:
q V C(Y − X)
i= = √ (3.18)
td (Y − X) LC
To find the characteristic impedance we form the ratio of V /i giving:
L
R0 = (3.19)
C
Typical impedances range from 10Ω between the inner and outer shields of
triaxial cable, to 300Ω for balanced cable used for television antennae. Figure 3.4
shows typical dimensions for 50Ω and 75Ω characteristic impedances on printed
circuit boards. Refer to Section I.3.12 for the general equations to work out the
characteristic impedance of microstrip and strip lines.
75W 50W
Microstrip Microstrip
H 2H
H H
Stripline Stripline
H H
H H
8 3
Figure 3.4: Typical dimensions of PCB traces to produce 50Ω and 75Ω charac-
teristic impedances.
However, if the line is terminated with a short circuit then we know that
the voltage at this point must be zero. We also know that when the reflections
on the line settle out (assuming that the line has some losses in it, as all real
transmission lines do) then the voltage at any point on the line must be zero.
Consequently, since the short circuit forces the zero terminating voltage, then
a reflected wave is generated at the termination that has an equal an opposite
polarity to the incident wave. The incident and reflected wave are added (since
the system is linear and superposition holds) to give the resultant wave. The
reflected wave flows back toward the source.
Eventually the wave reflected from the end termination will reach the source.
If the source is voltage source, then the voltage here must be fixed to the source
voltage. Consequently then will be another inversion of the incident wave (which
in this case is the reflected wave from the termination) to give a resultant volt-
age equal to the source voltage. Therefore, as with the end termination, the
reflection is produced such that the end boundary condition is satisfied.
The initial current flow into the transmission line is equal to Vs /R0 . The zero
impedance at the end of the line means that the current is unconstrained – i.e.
one can have any current flowing into this termination and still have no voltage
appearing across the termination. Therefore it is the voltage constraint that
determines what the reflected waveform is, and the current simply follows suit.
The negative reflection results in doubling of the resultant current at the end
termination, this eventually reaching the source where its value again increases,
and a further reflection occurs. Consequently the current continues to build up
in the line, and for an ideal line will go towards infinity as t → ∞.
One can mount similar arguments if the end of the transmission line is ter-
minated with an open circuit. In this case when the incident wave reaches the
84 Point-to-Point Wiring and Transmission Lines
open circuit the current must be zero, where as the voltage is unconstrained.
In order for the current to be zero there must be a current flow in the opposite
direction to the incident current. This means that there must be an equal volt-
age pulse, but in the opposite direction, flowing down the line. Therefore the
cumulative voltage at the end termination at this incident is twice the incident
voltage pulse. The reflected voltage will produce an equal, but opposite di-
rection current, flowing down the transmission line, and therefore the resultant
current is zero. What happens after this is determined by the nature of the load.
If the load appears as an AC short circuit, then the open circuit reflection will
be reflected as per the short circuit reflection above so that the source voltage
constraint is satisfied.
where Tr v is the length of the rising edge. The term Txr v is the number of rise
edge lengths along the transmission line, and therefore we are ensuring that
there are more than 10 segments for each of these.
If the C and L parameters for the transmission line are given as the C or L
per metre, then the segment values of these are:
(x)(C/metre)
Csegment = (3.21)
num of segments
(x)(L/metre)
Lsegment = (3.22)
num of segments
and so on for the R and G values if applicable.
Figure 3.5 shows the Saber model of a terminated transmission line using
coupled LC sections. The accuracy of this line is dependent on the rise time of
the signal on the line.
3.4 Some Practical Effects in Transmission Lines 85
p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11
4.5nH 4.5nH 4.5nH 4.5nH 4.5nH 4.5nH 4.5nH 4.5nH 4.5nH 4.5nH 4.5nH
3.0V 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF 1.1pF
step
Consequently there will be more current at the outer surface of the conductor
compared to the centre. As the frequency of the current increases then the rate
of change of the flux density increases and therefore the voltage induced inter-
nally in the wire increases, and consequently the crowding of the current on the
outer surface of the wire increases.
This effect can be considered to be happening on an infinitesimally small
elements, therefore the currents i1 and i3 will cancel and there is no net current
in the radial direction.
Area A
i3
i2 i4
Wire
i1
Flux density
lines
i
where:
As one might well imagine the main effect of the skin effect it that the resis-
tance of a wire increases with increased frequency. It should also be noted that
the skin effect is the same for a round conductors as it is for square conductors.
Skin effect begins to become significant for a round conductor when the skin
depth becomes less than the radius of the conductor. This is the point where
the AC resistance of the conductor will begin to rise. The rise is proportional
3.4 Some Practical Effects in Transmission Lines 87
to the square root of the applied frequency. For a flat rectangular conductor
the critical depth is half the conductor thickness.
An approximate expression for the resistance of a conductor at from DC to
an arbitrary frequency is:
1
R(f ) = {(RDC )2 + [RAC (f )]2 } 2 (3.24)
where:
RAC = (3.25)
πd
where:
d wire diameter in cm
RAC the AC resistance in Ω/cm
ρr relative resistivity compared to copper (Copper = 1.00)
f frequency in Hz (3.26)
One can get a feel for the magnitude of the resistance changes with skin
effect from Figure 3.7.
101
Resistance (Ohm/in)
10 -1
10 -3
10 -5
10 -7
101 10 3 10 5 10 7 10 9
Frequency (Hz)
Figure 3.7: Resistance of AWG 24 round wire (diameter = 0.02in) with fre-
quency (reproduced from [1] page 158).
Since skin effect is a surface phenomena then increasing the surface area
should decrease the effect. This is what happens. Litz wire consists of multiple
strands of very fine wire, each strand insulated from the others and woven in a
specific weave pattern. This weave ensures that each individual wire is subject to
88 Point-to-Point Wiring and Transmission Lines
similar magnetic forces which ensures equal currents flow in each of the strands.
Litz wire is very useful up to frequencies of 1MHz. Beyond this it is very difficult
to keep the currents in the strands balanced.
+ -
When currents flow in the same direction in two parallel wires the wires
experience a force that tends to pull the wires together. Similarly if the currents
are in the opposite directions the wires tend to repel each other. These forces
occur for all currents from DC upwards. This is not the proximity effect.1 The
proximity effect only occurs when high frequency currents are present. The
reasons for the effect are similar to those for the skin effect. The currents will
tend to distribute themselves in the wire in order to lower the inductance of the
loop of current. Clearly this will occur if the currents flow around the inside edge
of the loop as opposed to the outside edge. Under this condition the currents
experience less back-emf, this effect forcing the current distribution.
The proximity effect at equilibrium is determined by the ratio of wire separa-
tion between centres, to the wire diameter. The effect is most pronounced when
wires are nearly touching. The effect will increase the AC resistance above that
from just the skin effect alone. Proximity effect, unlike the skin effect, tends to
plateau at rather low frequencies.
1 Proximity effect does not exert any physical forces on the wires.
3.5 Termination of Transmission Lines 89
where:
that the subscriber is from the exchange. The transmission lines are conventional twisted pair
phone lines.
90 Point-to-Point Wiring and Transmission Lines
→
− →
−
If l = 0 then clearly V L = V s , which makes intuitive sense since one has a zero
→ −
− →
length line. Also note that if βl = π/2 then V L / V s = ∞.3 This corresponds
to a quarter wavelength transmission line, since λ = 2π/β (see (H.130)). If
→ −
− →
βl = nπ where n = 1, 2, 3 · · · then we get V L / V s = ±1. This corresponds to a
line that is multiples of half a wavelength on the transmission line.
Let us consider an open circuit load and a source impedance the same as
the characteristic impedance – i.e. will are considering the case where we have
ZL = ∞ and Zs = R0 . If we let ZL → ∞ in (3.27) then we get:
→
−
VL R0
→ = R cos(βl) + jR sin(βl)
− (3.30)
Vs 0 0
therefore: −
→
V L R0
−
→ = =1 (3.31)
Vs
R0 cos2 (βl) + sin2 (βl)
Therefore the voltage at the load end of the line is the same as the voltage at the
source. This is known as source or back matching, and intimately relies on the
reflection being produced at the open circuited load end of the line. However,
it should be realised that the waveform at the source end of the line will be
distorted. Initially when the pulse is applied the voltage at the source end of
the line will be: →
− →
−
→
− Zin V s R0 V s 1−→
V sl = = = Vs (3.32)
Zin + Zs R0 + R0 2
This initially launched voltage in the line will reflect totally at the load end
→
−
of the line, and hence double in value which obviously brings it back to V s .
However, the reflected wave will then propagate back to the source where it will
be absorbed by the source impedance. The voltage at this point will then be
→
−
V s.
Now consider the situation where one has a source termination of Rs and a
load termination of R0 . Substituting these values into (3.27) one can get:
−
→
V L R0
−→ = (3.33)
V s Rs + R0
→
− →
−
3 This implies that if V s = , where is a very small value, then V L = ∞. Therefore the
line is resonating.
3.5 Termination of Transmission Lines 91
Therefore, as with the back termination one does not get any reflection, and
therefore the transfer function is 1.
If one considers the phasor form of the transfer function:
−
→
VL 1
→ = cos(βl) + j sin(βl)
− (3.35)
Vs
one can see that there is a phase shift of − tan(βl) in the signal. This fact should
be clear from a consideration of the physics of a signal propagating at a velocity
down a line.
using the γ definition in (H.112). The H(ω) function describes the amplitude
and phase of a sinusoidal waveform that is propagating down a transmission
line, and an explicit form of the function can be seen in (H.121) (note that
this equation also contains the initial amplitude whereas (3.37) doesn’t). The
distance down the line is indicated by x.
Remark 3.3 The correspondence between the H(ω) representation and the ac-
tual signals that propagate down the line can be more readily seen by the use of
phasors. From Appendix H one can write:
−
→ →
−
V 1 (x) = V 1 H(ω) (3.38)
−
→
where V1 (x) denotes the voltage phasor at any point x down the transmission
→
−
line, and V 1 denotes the input phasor voltage (at x = 0), which can be written
as:
→
−
V 1 = V1 ejθV (3.39)
92 Point-to-Point Wiring and Transmission Lines
We can therefore expand the frequency domain expression into its time do-
main form as follows:
−
→
V1 (x) = V1 ejθV e−xγ
= V1 ejθV e−xα e−jxβ
Using the definition of the phasor to time domain conversion:
−
→
⇒ v(t) = R{V1 (x)ejωt }
= R{V1 e−xα ej(ωt−xβ) }
= V1 e−xα cos(ωt − βx) (3.40)
One can see from (3.40) that the voltage along the transmission line is a
function of α and β, and hence γ. Equation (3.40) specifically shows that the
amplitude of the voltage decreases as one travels down the line (i.e. decreases
with x), and at any specific point x along the line the voltage varies with respect
to time as a sinusoid.
The above analysis shows that H(ω) captures all the information required to
ascertain the variation of the voltage with respect to time and distance along the
transmission line.
The acceptance function for a transmission line is the transfer function re-
lating the signal amplitude and phase at the beginning of the line to that of the
source itself. Therefore the acceptance function is defined as:
Z0 (ω)
A(ω) = (3.41)
ZS (ω) + Z0 (ω)
At the far end of the line a fraction of the attenuated signal that has propa-
gated down the line emerges, and a fraction of the signal is reflected (note that
both these depend on the load termination). The fraction of the signal that
emerges (i.e. appears at the load) is called the transmission function and is
defined as:
2ZL (ω)
T (ω) = (3.42)
ZL (ω) + Z0 (ω)
which is derived from 1 + ρ, where ρ is the reflection coefficient.
Remark 3.4 Note that the transmission function states the proportion of the
signal that emerges across the load termination. For example, if ZL (ω) = 0 (i.e.
the load termination is a short circuit) then clearly T (ω) = 0, which means that
there is no signal across the load termination. If on the other hand the load
is an open circuit then there is voltage doubling at the load and therefore the
transmission function is 2.
The reflection coefficient is the ratio of the reflected signal to the incident
signal and was formally derived in Appendix H and will only be written here
without proof for the load termination:
ZL (ω) − Z0 (ω)
ρL = (3.43)
ZL (ω) + Z0 (ω)
3.5 Termination of Transmission Lines 93
The incident signal on the load will in general reflect. This reflected signal
is subjected to the attenuation function of the transmission line and a further
reflection at the source end of the line. This second reflection then continues
back down the transmission line and is again reflected at the load termination,
and the process continues. As the reflections continue the reflected signals grad-
ually decrease in amplitude (the rate depending on the size of the α parameter),
eventually settling out.
If we consider the second reflection, we can write the expression for the
incident signal on the source termination as:
This reflected signal then reaches the load termination again. It is again
attenuated by travelling down the line. Considering only the signal emerging
from the reflected signal we can write:
Figure 3.9 shows the series of reflections from the load and source terminations
as the signal propagates up and down the transmission line.
As discussed above this situation continues infinitely. For the nth emerging
signal we can find that the expression is:4
The total emerging signal is the sum of the all the Sn values for n =
0, 1, 2, · · · , ∞. Therefore the final steady state value for the emerging signal
is:
S∞ (ω) = Σ∞n=0 Sn (ω) (3.50)
There is a closed form solution for this infinite sum:
A(ω)Hl (ω)T (ω)
S∞ (ω) = (3.51)
1 − ρL (ω)Hl2 (ω)ρS (ω)
4 Note that this expression is only for the component of the incident signal that emerges
from the line. The total signal at this point is the addition of all the signals present – i.e. the
initial signal plus all the subsequent incident signals resulting from the reflections.
94 Point-to-Point Wiring and Transmission Lines
H l (w )
A(w )
ZS T(w )
Z0
A(w )H l (w )T (w )
+ ZL
H l (w ) r L (w )
T(w )
r L (w )
A(w )H l (w )[ r L (w )H l2(w )r S (w )]2T (w )
Equation (3.51) is the total frequency response function for the transmission
line. The frequency response expressions calculated in Appendix H are for the
initial incident waveform on the termination.
Using (3.51)) we can now revisit the effects of different terminations in a
more general setting. Using the expression T (ω) = 1 + ρL (ω) we can write
(3.51) as:
Hl (ω)A(ω)(ρL (ω) + 1)
S∞ (ω) = (3.52)
1 − ρL (ω)ρS (ω)Hl2 (ω)
If we assume that Hl (ω) is fixed (i.e. the cable parameters are fixed) then we
can alter the ρL (ω) and ρS (ω) functions via the load and source termination
values. Note that changing ρS (ω) also modifies A(ω).
Using (3.52) it is possible to ascertain very quickly the effects of the two
main termination types – load or end termination, and source termination.
As can be seen from this expression the input signal simply propagates down the
line and none of the signal is reflected back along the line. The magnitude and
phase of the signal is totally represented by the propagation characteristic of the
line and the acceptance function at the input source to the line. For sensible
terminations there should not be any ringing in the line since there are no
delayed versions of the input signal propagating up and down the transmission
line.
Remark 3.5 Note that load terminations have the undesirable characteristic
that if the driving voltage is high then power is being dissipated in the terminating
resistor. This power can be quite high, since the terminating resistor for most
PCB traces would be to the order of 80-200Ω.
Remark 3.6 The power dissipation problem mentioned in Remark 3.5 can be
overcome by using a series combination of a resistor and capacitor in the load
termination. If the capacitor is chosen appropraitely, then it will be a short
circuit at the frequencies that approach those in the switching edge. Therefore,
these frequencies will see the characteristic impedance terminating resistor as
the load, but the termination will be an open circuit at low frequencies. Con-
sequently, there will be no power dissipation under constant output voltage con-
ditions. Figure 3.10 shows a conventional load termination and two different
types of capacitor based load terminations.
vS Z0 (a)
vS Z0 C (b)
Transmission line
VCC
C
2
2Z 0
(c)
2Z 0
vS
C
2
As can be seen from this expression the line does what we would hope it would
do it it is short – nothing. The circuit behaves exactly as a lumped circuit.
When can one consider that the transmission line essentially acts as a lumped
circuit element – i.e. the transmission line must act like a wire which instantly
conducts the voltage from one end to the other. The usual answer is that the
line must be much shorter than one-sixth the electrical length of the rising edge
of the signal. We can state this mathematically as follows:
1 Tr
Length √ (3.56)
6 LC
where the parameters are defined as:
Tr rise time of the signal (sec)
L line inductance (H/m)
C capacitance (F/m)
Length maximum line length (m) (3.57)
98 Point-to-Point Wiring and Transmission Lines
Z0 Z0
For simplicity we shall assume that the right hand transmission line is ter-
minated with its characteristic impedance, therefore the line impedance seen
looking right from the capacitor is Z0 .5 Using this assumption we can calculate
the effect load impedance at the capacitor as follows:
1
jωC Z0
ZL (ω) = 1
Z0 + jωC
Z0
= (3.58)
1 + jωCZ0
Using this load in the expressions for reflection coefficient we can write:
−jωCZ0
ρC (ω) = (3.59)
2 + jωCZ0
Examining the denominator of this expression one can see that the mag-
nitude of the frequency component of the denominator is equal to the real
component when:
1
ωCZ0 = 2 ⇒ fC cut-off = (3.60)
πCZ0
For frequencies at fC cut-off the reflection coefficient magnitude is 1/2, and the
reflection is significant. For frequencies
fC cut-off the reflection is almost total.
5 We could also assume that the line is terminated with an arbitrary termination, but the
line is long enough that any reflections will arrive well after the immediate reflections from
the capacitor.
3.5 Termination of Transmission Lines 99
This can be easily deduced by realising that as ω → ∞ then ρc (ω) → −1. The 2
in the denominator becomes irrelevant in relation to the frequency based terms.
Therefore one should not use the transmission line with a capacitor attached to
it in this fashion under this frequency condition.
If we consider frequencies below fC cut-off then we can write the following
approximation ρC (ω) = −jωCZ0 /2 = −CZ0 s/2. The complex frequency do-
main operator s is the Laplace transform for the derivative operator. Therefore
the reflection coefficient is acting as a negative derivative operator, with the
constant of differentiation equal to −C(Z0 /2). This observation allows us to
estimate the amplitude of the reflected pulse as follows:
Z0 ∆V
| V− |= −C (3.61)
2 Tr
where | V− | the amplitude of the reflected pulse in volts, and the other
variables have the normal definitions already established. One can see that the
rise time of the signal is very important in determining the magnitude of the
reflection. If the rise time is slow then the reflected signal may be negligible.
The other aspect of interest in this circuit is the transmitted signal to the
right hand section of the line. The normal expression for the transmission
coefficient is:
1
T (ω) = 1 + ρC (ω) = (3.62)
1 + jωC Z20
This expression shows us that the capacitor acts as a first order low pass filter
as far as the signal propagating past the capacitor is concerned. The time con-
stant of the filter is C(Z0 /2). Therefore the 10%-90%
rise time approximately
(remembering that the true rise time is Tr = Tr21 + Tr22 ):
Z0
T10-90 = 2.2C (3.63)
2
The net effect is that the rise time of the transmitted edge has been degraded
by the presence of the capacitor.
An interesting non-obvious case of single capacitive loading on a line occurs
when tracks go through a 90◦ angle. This situation is illustrated in Figure 3.12.
Ad can be seen from this diagram the effective increase of the line width as it
turns the corner causes a discontinuity in the transmission line. It effectively
adds a small capacitor to this point on the line. One way of overcoming this is
to round the corner so that the line width stays the same, but this option may
not be very easy to do depending on the layout software. Another alternative is
to chamfer the corner as shown in Figure 3.13, and although it is not obvious,
this will achieve the same result and it good for frequencies up to 10Ghz [10].
Note that 45◦ turns require no special treatment.
w
Figure 3.12: Right angle track showing origin of additional capacitance.
0.57w
0.2w
0.2w w
w
Figure 3.13: Chamfered track to match impedance around a right angle corner.
3.5 Termination of Transmission Lines 101
l cm
RS
Z0
+
CL CL RL
{
N identical capacitive loads
on the line, and we saw that it can have a significant effect on the performance
of line depending on the rise time of the signals sent down the line. The effects
when we have evenly spaced capacitors depends largely on the spacing of the
capacitors relative to the length of the edge of the signals propagating down the
line.
If the rising edge length exceeds the spacing of the loads then one can derive
a simplified approximation for the behaviour of the circuit. If on the other
hand the rising edge is of the order of or less than the spacing between the loads
then we get the situation with the single capacitor at end of the nodes where the
capacitors join the transmission line. Therefore there will be multiple reflections
bouncing between these various nodes resulting in degraded signal quality on
the transmission line.
If we consider the situation where the rising edge is much longer than the
spacing between the loads then several capacitors will be involved in determining
the behaviour of a single edge. Therefore the capacitors are effectively smeared
along the edge. This in effect means that the load capacitors effectively become
part of the line capacitance. If we doubled the number of capacitors and halved
their values and place these along the same length of line the performance of
the line will not appreciably change. Therefore the capacitors can be thought
of as continuously distributed capacitance in the form of pF/cm. Therefore the
new distributed capacitance for the transmission line is:
N CL
C = Cline + (3.64)
l
This new effective capacitance means that we will now have a new effective
characteristic impedance for the line:
L
Z0 = (3.65)
C
One can see from (3.65) that Z0 will have a lower value than for an unloaded line.
In fact it is quite easy to end up with very low characteristic impedances for the
line, which makes them very difficult to drive effectively with normal bus drivers.
The other problem that arises from this increase in effective capacitance
√ is the
delay. We know from (2.5) that the delay per unit length is LC . Hence for
102 Point-to-Point Wiring and Transmission Lines
larger C then longer the delay is for the signals propagating down a line. This
delay occurs regardless of whether we can drive the line or not. Depending on
the situation it may be crucially important. For example, if we have a number
of high speed memory chips forming the uniformly distributed load, and the
transmission lines are the address lines, then the delay will cause a skew in the
address information between the first chip on the transmission lines and the last
chip. This skew effectively lessens the access time of the last chip on the line.
For typical values of the SIMM module capacitances and the length of blocks
of SIMMs, delays of the order of 5 to 10nsec would not be unusual.
Z0 Z0 Z0
(a)
Z0 Z0
Z0 Z0
(b)
Z0 Z0
(c)
Z0
Z?
Z0
(d)
Multi-point line
(V) : t(s)
6.0
Node 5 on line
v(v_pulse.v_pulse1)
4.0
(V)
2.0
0.0
Figure 3.16: Voltage just prior to line connection with mid line multi-point
connection.
If one changes the configuration to that of (b) in Figure 3.15 then we es-
sentially have two separate transmission lines, since the voltage source effective
decouples the lines. The disadvantage of this approach is the we are using end
terminations which have high power dissipation properties.
If we adopt the approach shown in Figure 3.15 (c) we get the results shown
in Figure 3.18. As can be seen the performance is totally unsatisfactory. There
are severe oscillations at all points on the lines. The problem is that the return
reflections from the open circuited line ends are not correctly absorbed at the
intersection point of the lines. Therefore this leads to further reflections and we
end up with the complex waveforms shown. The oscillations are particularly
bad in this case due to the magnitude of the reflections that one obtains from
the open circuits at the ends of the lines.
An alternative for a series termination that we might try is that shown
in Figure 3.15 (d), where the line connection has been changed to be at the
termination resistor, and the termination resistor is changed to Z0 /2. In this
case we again get reflections from the open circuit end terminations, and under
the circumstance that the two line lengths are the same these reflections arrive
at the source termination together. The initial waveforms launched down the
two lines will be 1/2V due to the parallel loading of the two lines and the voltage
104 Point-to-Point Wiring and Transmission Lines
v(v_pulse.v_pulse1)
4.0
(V)
2.0
0.0
0.0 1n 2n 3n 4n
t(s)
Graph0
(V) : t(s)
6.0
v(v_pulse.v_pulse1)
4.0
(V)
2.0
0.0
(V) : t(s)
6.0
Line 2 end voltage
4.0
(V)
2.0
0.0
(V) : t(s)
6.0
Mid line voltage
4.0
(V)
2.0
0.0
(V) : t(s)
6.0
Line 1 end voltage
4.0
(V)
2.0
0.0
0.0 2n 4n 6n 8n 10n
t(s)
Figure 3.18: Waveform plots for a multi-point line with a single series termina-
tion and mid point line connection.
3.5 Termination of Transmission Lines 105
4.0
(V)
2.0
0.0
(V) : t(s)
6.0
Line 2 termination
4.0
(V)
2.0
0.0
(V) : t(s)
6.0
Line 1 termination
4.0
(V)
2.0
0.0
0.0 2n 4n 6n 8n 10n
t(s)
If the two lines that split off are of different lengths the situation described
above no longer applies. The reflections from the open circuit terminations will
not arrive back at the junction at the same time and there will be a number
of oscillations in the system due to this. This effect is shown in Figure 3.20.
Here we have the source termination equal to Z0 /2 as in the previous case, but
one of the lines is half the length of the other. Therefore the reflection from
this line will arrive back at the junction much sooner from the shorter line, and
hence there is a voltage difference at this point some of the return signal from
one line flows into the other. One can see that the termination signals are no
longer satisfactory. Therefore, in general, the technique of using a single source
termination for a multi-point system is not going to give good signals.
Note 3.1 It should noted that one cannot daisy chain gates off lines when one
has source terminations, since the signal at intermediate points on the line will
have a two step form. If one uses an end terminator the signal will have the
correct form as it propagates down the line.
Note 3.2 The use of end terminations of the form shown in Figure 3.15 is not
usual in digital systems. The main problem is the drive required to drive the
106 Point-to-Point Wiring and Transmission Lines
4.0
(V) 2.0
0.0
(V) : t(s)
8.0
Line 2 termination
6.0
(V)
4.0
2.0
0.0
(V) : t(s)
8.0
Line 1 termination
6.0
(V)
4.0
2.0
0.0
0.0 2n 4n 6n 8n 10n
t(s)
termination. For example, not many gates would be capable of driving a 65Ω
resistive termination to 4 Volts. In addition there is the issue of DC power
dissipation in steady state in these terminations. Generally speaking the series
termination is much more common. One can also use the split end termination
(i.e. two resistors, one connected to +5V and the other to ground, with the
parallel combination of the resistors equal to Z0 ), although these still have many
of the problems of the single termination resistor.
Therefore the impedance looking into the midpoint connection is the charac-
teristic impedance of the line. Therefore there should be no reflection at the
intersection point. It should be noted that the ends of the two lines at the right
have to be terminated in the characteristic impedance of the line so that there
are no reflections coming back to the junction point. For the reason cited above
the technique is therefore not useful for digital systems. The other problem
is that the signals are attenuated. If the signal on the left line is V, then the
signals propagating down the right lines would be 2/3V. These effects can be
seen in Figure 3.22.
3.5 Termination of Transmission Lines 107
Z0
Z0
3 Z0
Z0 3
Z0
3
Z0
2.0
0.0
(V) : t(s)
6.0
5.0 Just before split
4.0
(V)
3.0
2.0
1.0
0.0
(V) : t(s)
4.0
Line 2 termination
3.0
(V)
2.0
1.0
0.0
(V) : t(s)
4.0
Line 1 termination
3.0
(V)
2.0
1.0
0.0
0.0 2n 4n 6n 8n 10n
t(s)
Remark 3.9 The branching technique of Figure 3.21 is used a lot in communi-
cations systems to cheaply split signals from antenna. For example, the splitter
or diplexer used on home television is often based on this circuit. One needs a
strong incoming signal in order to split it in this way.
Remark 3.10 If one has PCB tracks then matching can be achieved by chang-
ing the design of the tracks. For example, if the characterisitc impedance of the
source track is Z0 then the impedance of the branches can be made to be 2Z0 .
This means that the impedance looking into the branch point from the source is
Z0 . The two branch tracks do not have terminations, and the source is source
terminated. Because the two branch lines do not have terminations there are
reflections at the ends which will double the voltage (which was 12 V due to the
source termination). These reflected waves then travel back down the branch
lines to the line junction point, where they will re-reflect and be partially trans-
mitted. If the branch lines are of the same length then the oscillations are not
too bad, but if the lines are of different lengths then the branch reflections arrive
at different times and the resultant waveforms are highly distorted.
Practical Issue 3.1 If one has to branch tracks off each other then attempt to
choose the track sizes to achieve the effect in the previous remark. In addition
make sure that the branch tracks are symmetric as far as possible.
In many practical circuit layouts one has to connect multiple ICs to a signal
trace. An example of this is where there is a global clock line on a circuit board.
In this situation it is impractical to run a separate terminated line from the
clock source to all the receiving circuits. There are several things that can be
done to make the layout feasible and to maintain the signal integrity.
Figure 3.23: Poorly designed gate daisy chain with end termination.
Figure 3.23 shows a set of gates daisy chained off a transmission line. The
small stub traces to the gate inputs are short enough that they can be considered
as lumped elements. Therefore they appear as extra capacitance in parallel
3.5 Termination of Transmission Lines 109
with the input capacitance of the gate. Consequently the edge of the signal is
progressively degraded as it propagates down the transmission line. The other
point to note about this circuit is that it is load terminated, as opposed to
source terminated. Load termination is required in order to ensure that all the
gates in the middle sections of the line receive a good quality signal without the
two stage step that is present when there is a source termination.
From
driver
{
Gate pins connected
directly to the trace
Terminating
resistor
Figure 3.24 shows the layout for a better design of a set of daisy chained
gates. The relevant design features shown in this figure are that the gate inputs
are connected directly into the track without any stub tracks. This keeps the
added capacitance at the gate points to the input capacitance of the gate, with-
out the added capacitance of the stub. Another point about the design is that
the receiving gates should be positioned the same distance apart (or as near as
one can get), the distance being significantly less that the length of an edge on
the trace. This will ensure that the gate input capacitances appear as added
transmission line capacitance, and will not lead to degraded edges, but just a
different characteristic impedance. Finally, the last gate should be positioned
before the end of the line, so that its input capacitance is seen as a part of the
line, and not a capacitance across the terminating resistor. This will prevent
reflections from a capacitance termination.
110 Point-to-Point Wiring and Transmission Lines
Chapter 4
This chapter will concentrate on issues related to the lay out of ground planes
and tracks on printed circuit boards. These issues are very important if one is
to get a printed circuit board that works with the high speed digital technology
prevalent today.
Ground and power planes in high speed digital systems perform three critical
functions:
four layer PCB – two layers for power distribution and two for signal distribution.
112 Ground Planes and other Printed Circuit Board Issues
Power planes
where r the relative dielectric constant, c the speed of light, and L0 , C0 are
the inductance and capacitance per unit length. This equation indicates that
there is a fundamental relationship between the inductance and capacitance per
unit length for a transmission line.
Other relevant expressions are those for the capacitance and inductance for
the planes:
A wl
C = r 0= r 0
h h
C w
∴ C0 = = r 0 (4.3)
l h
Using this expression together with the characteristic impedance expression one
can also calculate the inductance per unit length:
L0
Z0 = ⇒ L0 = Z02 C0
C0
2
η2 h w
∴ L0 = 0 r 0
r w h
h
= η02 0
w
h
=µ (4.4)
w
4.1 Power Planes 113
If we consider the line dimensions from the previous example we can calculate
the effective inductance and capacitance per unit length:2
25
C0 = 4.7 × 8.854 × 10−14
0.075
= 0.138nF/cm (4.5)
∴ CT = 25 × C0 = 3.5nF (4.6)
0.075
L0 = 4π × 10−9 ×
25
= 38pH/cm (4.7)
where l = 25cm.
Remark 4.1 As one can see from the above numbers the power plane has a
modest total capacitance and a very low inductance per unit length. The
combination of the capacitance and the low inductance means that there will be
very low transient voltage drops along the ground plane when a rapidly rising
current is drawn from the plane.
cos(βl) ≈ 1
and sin(βl) ≈ βl
1
Zin = + jωL0 l (4.11)
jωC
Remark 4.3 It is interesting to note that the power planes are themselves
transmission lines. Therefore they should be subject to reflections as are the
lines we have looked at previously, and this is what happens. If a pulse in in-
jected (due to an IC pulling a current from the power planes) then the voltage
and current propagate in every direction from the initiating point. When they
reach the edge of the board then there is an open circuit termination and conse-
quently a reflection would occur. Fortunately the magnitude of these reflections
are small due to the small instigating pulse, and the fact that the decoupling
capacitors also have an effect.
Load
Current
flow
Driving
gate
Load
Current
flow
Driving
gate
Figure 4.2: Approximate current flows with low and high frequency spectral
content.
116 Ground Planes and other Printed Circuit Board Issues
where:
Figure 4.3 shows the form of the distribution of the current under a trace.
One may initially think that all the current would bunch up as tightly as possible
under the trace. However the distribution of the current indicated in (4.12) is
actually a balance of two opposing forces. If the current is bunched under the
conductor then the inductance would increase as a thin wire carrying the same
current has a higher inductance than a fat wire. Therefore, this would mean
that the current would tend to widen. Opposing this is as the current widens
across the ground plane the effective loop area starts to increase, and this tends
to raise the inductance. Therefore this tends to bunch the current. The balance
of these two effects leads to (4.12).
Current density at D is
proportional to:
1 W
Trace
1+ FH IK
D
2
Ground plane
D
Figure 4.3: Distribution of current in the ground plane when the currents have
high frequency components.
Current density at D is
proportional to:
1
W 1+ FH IK
D
2
H
Trace
Ground plane
D
Figure 4.4: Two traces above a ground plane and the resultant current distri-
bution.
Notice the similarity between this expression and the current density expression
(4.12).
Because the returning current density and its associated local magnetic field
strength drop off according to (4.12) then we may suspect that the cross-coupling
will also drop off as:
K
Crosstalk = (4.14)
1 + (D/H)2
where K is related to the circuit rise time and the length of the interfering
traces.
This relationship can be verified experimentally. The main intuitive result
is that for a fixed trace spacing the cross-coupling falls off with a 1/(1/H 2 )
relationship (remember that the current density has a constant in front of it
with a 1/(1/H 2 ) variable). Therefore it is important that the traces are kept
close to the ground plane. The other important factor is the separation of the
traces. The cross-coupling falls with a 1/D2 relationship. Therefore it one
wishes to minimise the coupling then kept the traces a long way apart. Clearly,
overall it is the D/H relationship that is the important factor.
Slot in the
ground plane Return currents
for AB trace
A B
C D
Return
current for
CD trace
Figure 4.5: Current paths with a slot cut in the ground plane of a PCB.
Remark 4.4 It should be noted that the width of the slot in the ground plane
does not matter. It is the length of the slot perpendicular to the traces that counts
as this determines the degree to which the current must divert to go around the
slot.
As a trace progressively gets closer to the end of a slot then the extra induc-
tance decreases linearly with distance from the slot end. If a trace is close to a
slot but does not run over the slot then the slot presence has virtually no effect.
Remark 4.5 One can write down approximate expressions for the inductance
added by slots. These will not be presented because one should not have slots in
the ground plane at all.
Y Trace width W X
+5V
GND
An alternative to the power and ground grid design is a layout using the power
and ground fingers. The basic layout of this is shown in Figure 4.8.
This type of layout for two sided boards was prevalent in the early days of
computing (e.g. the PDP-8 computer used this, as well as most of the wire wrap
boards available 15 years ago). However, this type of layout is not really usable
in modern equipment due to the large inductances of the traces and degree of
crosstalk. The reason for this can be seen in Figure 4.8 – the return currents
have to flow around the periphery of the board. Therefore the loop area of the
current from the source driver to the source current return point is potentially
very large. This same effect means that there are magnetic fields everywhere
with this design, and such boards would not satisfy modern electro-magnetic
emission standards. This effect also means that the cross coupling between
traces will be very high.
122 Ground Planes and other Printed Circuit Board Issues
The approximate loop inductance on a power and ground finger board is:
X
L ≈ 2Y ln (4.17)
Y
where:
where L inductance, nH
X board width, cm
W trace width, cm
Y trace length, cm
Notice that making the trace width twice as large will have little effect on the
inductance.
Remark 4.7 One can probably get a board going using old logic families using
this type of board design, but one would have little hope of getting modern logic
to work with it.
Signal trace 1
Guard
trace
Signal trace 2
Driving signal
A k B
CM CM CM
LM LM LM LM
C D
to time as the initial voltage step propagates down the line. Consequently two
waves are injected into the line at each of the mutual inductances, one travel-
ling in a positive direction down the line, and the other travelling in a negative
direction down the line. The positive travelling wave (which is actually of neg-
ative polarity) is reinforced at every successive tap point since it travels in the
same direction and at the same velocity as the instigating wave. On the other
hand the negative direction travelling wave (which is of positive polarity) is not
reinforced since it travels in the opposite direction to the instigating waveform.
A new negative travelling wave occurs progressively at each of the taps down
the transmission line. Therefore we end up with a set of waves which arrive at
the source end termination in line 2 in succession, resulting in a long low pulse
here. At the load end termination of line 2 the positive travelling pulses all
arrive simultaneously resulting in a single larger pulse.
Note that the simulation is only a discrete model of an completely distributed
system, therefore the real line would look slightly different.
Remark 4.8 The positive direction travelling pulse is negative because of the
assumed polarity of the mutual coupling. We are assuming that the left hand
side of the line 2 inductors are positive.
Remark 4.9 Because line 1 is correctly terminated the mutual inductance has
little effect on its performance. The coupling back from line 2 to line 1 due to
the currents and voltage induced in line 2 is small due to the small currents and
voltages present in line 2 relative to those in line 1.
0.0
−0.2
(V) : t(s)
4.0
L1.END
(V)
2.0
0.0
(V) : t(s)
0.2
L2.END
0.0
(V)
−0.2
−0.4
(V) : t(s)
4.0
v(v_pulse.v_pulse1)
(V)
2.0
0.0
(V) : t(s)
0.2
L2.SRC
(V)
0.0
−0.2
0.0
−0.1
(V) : t(s)
3.0
v(v_pulse.v_pulse1)
2.0
(V)
1.0 L1.END
0.0
(V) : t(s)
0.1
L2.SRC
(V)
0.0
−0.1
(V) : t(s)
0.4
L2.END
0.2
(V)
0.0
−0.2
0.0 1n 2n 3n 4n 5n 6n
t(s)
0.0
−0.2
(V) : t(s)
0.2
L2.SRC
0.1
(V)
0.0
−0.1
−0.2
(V) : t(s)
4.0
L1.END
(V)
2.0
0.0
(V) : t(s)
0.1
L2.END
(V)
0.0
−0.1
(V) : t(s)
4.0
v(v_pulse.v_pulse1)
(V)
2.0
0.0
0.0 1n 2n 3n 4n 5n
t(s)
Figure 4.13: Mutual coupling waveforms with both inductive and capacitive
coupling and Tr = 210psec.
128 Ground Planes and other Printed Circuit Board Issues
Part II
Fundamental Topologies
5.1 Introduction
This course part will not attempt to cover every issue related to the design and
operation of switch mode power supplies – there is more than enough work in
this area to fill a whole course by itself. Instead, the material shall seek to em-
phasise the main types of switch mode converter structures, their fundamental
operational principles, the various areas where the different structures are useful,
and finally aspects of the design and control of the switch mode converters.
Before looking at the different structures for switch mode converters, we
should firstly define what we mean by switch mode converters.
Definition 5.1 Switch Mode Converters (SMCs) are converters which accept
a DC input and generate a DC output. Switched mode converters are usually
only operating at powers up to 10’s of kilowatts.
5.2 References
References to switch mode power supplies are often contained in texts on elec-
tronics and power electronics. There are some specialised book written on the
design of switching power supplies. Tutorial references that readers may find
useful are [4, 11–13].
One can find a lot of material in the IEEE Transactions on Industrial Elec-
tronics, and the IEEE Transactions on Power Electronics. This information
132 Fundamental Topologies
Many of the other topologies that are in the literature are combinations of these
two basic topologies.
The basic layout of a SMC system is shown in Figure 5.1 below. The input
to the converter is usually the mains. Since this is AC the first step is to convert
this to DC via a rectifier. Notice that one can also feed DC, from a battery,
directly in at the output point of the rectifier. The unregulated DC is usually
filtered with a capacitor, before feeding the DC-DC converter electronics. The
output of this stage then feeds the load.
Battery
AC
line voltage Uncontrolled Filter DC-DC
Load
(1 or 3 diode rectifier capacitor converter
phase) DC DC DC
(unregulated) (unregulated) (regulated)
Desired output
voltage
L. The capacitor C will charge up during this process. Note that there is a
transient involved in the inductor current building up and the voltage being
established on the capacitor. When the switch is opened the current through
the inductor cannot stop instantly (if it does then the voltage across the inductor
will become very large and the circuit will most probably be destroyed). The
diode in the circuit will become forward biased, allowing the current in the
inductor to continue flowing in the same direction (towards the load). During
this phase of operation the energy that was stored in the field of the inductor
during the switch on time is being transferred to the load. If the switch remains
open for a long time the inductor current gradually decreases to zero, and at
the same time the current drawn from the capacitor increases. If the switch is
closed before the inductor current decreases to zero, then the current begins to
increase again.
Remark 5.1 Note that the maximum current that can flow through the inductor
if the switch is left closed is Vd /RL .
Remark 5.2 If the inductor current goes to zero then the converter is said to
be operating in discontinuous mode. If it does not go to zero, then the converter
is operating in continuous current mode. Generally speaking, it is desirable
to operate the converter in one mode or the other, without a change of mode.
Changes in mode can result in difficulties in controlling the output voltage of
the converter. A change of mode can occur depending on load changes.
Remark 5.3 If the filter were not present in Figure 5.2 then the output voltage
would exactly mirror the input voltage – i.e. if the switch is opened an closed
then the output would be a square wave voltage. The filter has to be designed so
that the cutoff frequency is significantly below the switching frequency. If this is
the case then the filter will reject most of the AC components present at the vod ,
so that the output voltage will essentially be a DC value equal to the average
value of the voltage vod .
Remark 5.4 One of the distinguishing features of this type of circuit is that
when the switch is closed the input is connected to the output, but when the buck converter dis-
switch is open the input is disconnected from the output. tinguishing features
Another distinguishing feature of the buck converter is that the inductor is
not placed across the input voltage when the switch is closed. The inductor has a
voltage imposed across it that is usually somewhat lower than the input voltage.
This means that the inductor does not store all the energy being supplied by the
input.
Remark 5.5 If multiple output voltages are required then the buck converter as
depicted here is not the topology to use. Other converters, such as the forward
converter, that are related to the buck converter can be used.
Remark 5.6 Since the switch is at the input to the converter, then the in-
put current is discontinuous. Therefore the input filter to this circuit is more
complicated compared to other converter types.
Practical Issue 5.1 Driving the gate of a buck converter can be a problem. If
we assume that the switching element is a n-channel MOSFET (as it would be
134 Fundamental Topologies
Energy storage
inductor
Low pass filter
SW iL
id io
L
vod + -
Vd vL C RL Vo
Load
for many designs), then the gate voltage often has to be 5V, and in some cases
10V above the supply voltage. This complicates the gate drive, since one has to
fabricate the higher voltage using a transformer based gate drive circuit.
Energy storage
iL L io
+ vL -
+
Vd C Vo
SW
-
Remark 5.7 If the voltage on the capacitor is larger than the supply voltage,
the inductor will produce what ever voltage is required so that Vd + vL = Vo .
This is required in order for the current to continue to flow in the inductor.
One can see that because the polarity of vL shown in Figure 5.3 always has to
reverse for this situation, then the output voltage must always be greater than
the input voltage (except under initial start-up conditions).
Remark 5.8 The main feature of the boost converter is that current can flow
through the switch regardless of the relationship between the input and output
voltages. This usually occurs because the input to the circuit is disconnected
from the output when the switch is closed. It is this feature that one must look boost converter dis-
for when one is trying to ascertain what category a particular topology falls into. tinguishing features
When the switch is opened, the input is connected to the output because the diode
switches on.
Another distinguishing feature is that when the switch is closed the input
voltage is placed across the inductor (so that it stores all the energy being supplied
by the input), and when the switch is opened the inductor is placed in series with
the load. and this stored energy is transferred to the load.
Remark 5.9 In a boost converter the inductor fulfills an energy storage func-
tion, whereas in the buck converter the inductor forms a filtering function.
Therefore, one can view the boost converter as not having a filter capacitor.
This distinction is not very clear for the non-isolated converter, but when we
look at isolated converters in the next chapter we shall see that there is a clear
distinction.
Remark 5.10 There is a maximum power that is practical to build for convert-
ers that rely on the energy storage principle. This is especially true for low input
voltages. As we shall see in the next chapter a related converter is the flyback
converter, which operates using the same principle, and hence suffers from the
same power limitations. In order to cater for high power output with an energy
storage converter, one needs to have a very small energy storage inductor (since
E = 12 Li2 , and therefore the current contributes most significantly to the stored
energy). It turns out that for powers much above 50W when the input voltage
is low, the inductance becomes very small and is comparable with the parasitics
of the circuit. Therefore, the circuit becomes very difficult to manufacture.
it is very difficult to see the separate buck or boost converters in the single switch circuits.
136 Fundamental Topologies
In order to understand the operation of this circuit let us firstly look at a two
switch implementation. Figure 5.4 shows the conceptual circuit for this. In this
circuit both switches are either closed at the same time, or they are open at the
same time. If both the switches are closed, then the circuit takes on the classic
boost converter configuration. If the output voltage is higher than the input
voltage, current can still flow through the inductor. When both the switches
are opened, then the inductor is positioned in the circuit as in the classic buck
converter, and the current built up during the switch closed stage circulates via
the diodes through the output capacitor.
Remark 5.11 The key to the circuit of Figure 5.4 is that the switches effectively
change the circuit configuration, from a boost circuit during the energy storage
phase, to a buck circuit when energy is transferred to the load.
SW1 iL
io
L
+ vL -
Vd SW2 C Vo RL
Figure 5.5 shows a simplified circuit for a buck-boost converter circuit using
only one switch. The crucial change in this circuit is the swap of the inductor
and the switch and the reversal of the diode as compared to the boost converter
of Figure 5.3. The swapping of the inductor and the switch and reversing the
diode means that the full input voltage is applied across the inductor when the
switch is closed (as in the boost converter). This means that the inductor is
essentially a energy storage element, as in the boost converter. However, when
the switch is opened the input is no longer connected to the supply (as is the
situation in the buck converter), and therefore the constraint that the output
must be larger than the input is removed. The resultant voltage across the
capacitor is simply related to the amount of energy stored in the inductor, and
the current required by the load resistor. If one wishes to increase the output
voltage then the switch is closed for a longer period of time, and it the voltage
is to be decreased then the switch is closed for a shorter period of time.
Remark 5.12 One can see from the above explanation that the operation of this
circuit has characteristics of both the buck and the boost converter. Reiterating,
the energy storage in the inductor is from the boost converter (when the switch
is closed), and the disconnection of the input from the output when the switch
is open is the same as the buck converter.
One can therefore identify a buck–boost topology by looking for the fact that
the inductor is placed across the supply and disconnected from the load during the
5.3 Taxonomy of Switch Mode Converters 137
id SW
+
Vd vL L iL Vo
C RL
io
energy storage phase when the switch is closed, and the inductor is disconnected
from the supply and placed in the output circuit when the switch is opened.
Remark 5.13 One should note that the voltages one can obtain from the buck–
boost converter are related to the relationship between the load, the capacitor,
and the inductor.
iL iL
1 vC 2
1
+ -
+ L1 - - L2 +
C1
vL vL
1 2
Vd SW C Vo RL
io
The input current, iL1 , would be decreasing because the capacitor voltage is
greater than the input voltage. This can be deduced from the fact that:
v c1 = V d + V o (5.1)
Remark 5.15 Equation (5.1) results from the fact that the average voltage
across the inductors in the circuit must ve zero under steady state conditions –
the total volt-seconds change across an inductor must be zero over a complete
switching cycle under steady state conditions.
iL iL
1
vC 2
1
+ -
L1 L2
+ vL - - vL +
1 2
Vd C Vo RL
io
Let us consider the situation when the switch is closed. The circuit under this
condition is shown in Figure 5.8. Clearly the diode is reverse biased under this
condition, and the input inductor, L1 is storing energy with the input voltage
appearing across it. The current, iL2 is also flowing through the switch. This
current to will be increasing with the capacitor voltage driving it. Therefore,
the energy that has been stored in the capacitor is being transferred to the load.
Remark 5.16 The important point to note about the operation of the Cúk con-
verter is that the capacitor C1 is the element that is actually transferring the
5.3 Taxonomy of Switch Mode Converters 139
iL i L2
1
vC
1
+ -
L1 L2
C1
+ vL - - vL +
1 2
Vd C2 Vo RL
io
Switch is closed circuit
energy to the output (and not the inductor as in the other converters that we
have looked at). The inductors in the circuit are essentially performing a filter-
ing function on the input currents.
Remark 5.17 Examination of Figures 5.7 and 5.8 indicate that the switch sim-
ply transfers the capacitor from the input where it receives energy from the sup-
ply, to across the load where it supplies energy to the load.
Remark 5.18 The capacitor in the Cúk converter has to be able to handle high
ripple currents.
Leg A Leg B
DC machine load
Vd v 0 = v AN - v BN
Ra
+
v AN ea
DA- DB- v BN -
SWA- SWB-
There are two main switching strategies that can be adopted using the full
bridge inverter:
• Bipolar switching.
• Unipolar switching.
Bipolar switching is the name given to the switching strategy when the A+
and B− are switched together, and the B+ and A− are switched together.
Therefore the voltage applied to the load is ±Vd . There are no other voltages
that can be applied. One can deduce that it the switching is such that 50% of
the time the A+, B− is in force, and the remainder of the time the B+, A−
state in in force, then the average voltage across the load is zero. By varying
the switching around this the voltage can be varied from zero to Vd (when only
A+, B− are in force) to −Vd (when only B+, A− are in force).
Remark 5.19 The full bridge converter can only produce output voltages that
are in the range of −Vd ≤ vo ≤ Vd .
Consider Figure 5.10, which shows a switching waveform. The duty cycle of this
waveform is defined as:
ton
D= (5.2)
Ts
Considering the waveform in Figure 5.10 we can work out the average voltage
SW
Vd R v0
v0
ON OFF
Vd
V0
0 t
t on t off
Ts
produced:
Ts
1
vave = vo dt
Ts
0
ton Ts
1
= Vd dt + 0dt
Ts 0 ton
ton
= Vd
Ts
= DVd (5.3)
From (5.3) one can see that the average voltage is directly proportional to
the duty cycle of the switching.
Sawtooth waveform
v st
Vcontrol
ON OFF
Vd
ton toff
Ts
Vdesired +
v control
Amplifier +
- Comparator Switch
V0
control
-
Sawtooth
waveform
Remark 5.22 A consequence of the previous note is that over a complete cycle
of the PWM the average current supplied by the inductor must be equal to the
average current supplied to the load. If this were not the case then the capacitor
voltage would continually rise or fall over time as the circuit operated, thereby
violating the steady state assumption.
Notation 5.1 The capitalised currents and voltages in Figure 5.13 and the fol-
lowing analysis refer to the average values of the currents, and not the instan-
taneous values.
As stated above the average inductor voltage over the complete PWM in-
terval has to be zero for steady state operation. Therefore, by inspection of the
inductor voltage plot in Figure 5.13 we can say that the volt-seconds applied
must be zero.3 Therefore:
vL
Vd -Vo
A
0 t
B
-V0
iL
Ts
IL
Io
0
t
t on t off
iL iL
io io
L L
+ vL - + vL -
Vd C Vo Vd C Vo
Vo ton
= = D (duty cycle) (5.9)
Vd Ts
Remark 5.23 Keeping in mind the assumptions in the analysis, this (5.9)
means that the output voltage varies linearly with the duty cycle, given a fixed
input voltage.
Remark 5.24 One could also obtain the relationship of (5.9) by averaging the
vo voltage shown in Figure 5.10, realising that this voltage waveform is the form
of the input waveform. The output is then obtained since the average input
voltage has to be the same as the average output voltage for steady state to
exist in the circuit (else the current through the inductor would be increasing or
decreasing over a number of cycles.)
By using conservation of energy one can also calculate the ratio of the input
and output currents. Assuming that the circuit is essentially lossless, then we
can say:
Pd = Po (5.10)
This can be clearly expanded as:
Vd Id = Vo Io (5.11)
or
Io Vd 1
= = (5.12)
Id Vo D
Remark 5.25 As can be seen from (5.12) the buck converter acts the same as
an electronic transformer when in continuous current mode.
146 Fundamental Topologies
Remark 5.26 Even though the current iL is fairly smooth, the input current
id is jumping from some peak value to zero every time the switch is opened.
Depending on the source for the converter, the input may have to be filtered to
smooth out these current fluctuations.
where ILB is the minimum average inductor current, and IoB the minimum
output current value (remember the two are the same given the steady state
assumption).
Equation (5.13) can be further manipulated using the expression (5.9) to
current required eliminate V0 , and assuming that Vd is constant, giving:
for continuous
inductor current Ts Vd
ILB = IoB = (D − D2 ) (5.14)
2L
On can differentiate (5.14) to find the duty cycle for the maximum ILB for
given Vd , Ts , D, and L:
dILB Ts Vd
= (1 − 2D) (5.15)
dD 2L
1
Clearly from (5.15), the maximum value occurs at D = 2 Therefore using (5.14)
that value is:
Ts Vd
ILBmax = (5.16)
8L
Remark 5.27 Equation (5.14) defines the value of the average current required
in the inductor to just allow continuous conduction. Therefore, the maximum
value for this average current, which is the value defined in (5.16) occurs when
the duty cycle is 1/2. This means that the onset of discontinuous current oper-
ation occurs first if the duty cycle is around this value (which implies that the
output voltage is 12 Vd ), as the load current is decreased (i.e. one increases the
load resistance value so that less current can flow).
Remark 5.28 The previous remark implies that one can design the converter
so that the minimum load current is larger than ILBmax in order to ensure contin-
uous conduction (assuming that continuous conduction is the desired operation
mode). Note that one of the main design parameters is the inductance value
5.4 Basic Analysis of Switch Mode Converters 147
v L = (Vd -Vo )
iL
0 t
I LB = I oB
-Vo
t on t off
Ts
itself. Another point to note is that the input voltage is a parameter in (5.16),
so if this voltage varies over a range then this must be taken into considera-
tion. Finally, the load of the system will define the load current required, and
via the other considerations mentioned above it will define the parameters of the
converter.
There are two main cases to investigate in relation to discontinuous current
– the constant Vd case and the constant Vo case. Let us now consider each of
these.
iL Current is
peak
zero here
I L = Io
v L = (Vd -Vo ) iL
0 t
-Vo
Ts
Figure 5.15: Current waveform for a buck converter with discontinuous current.
similar to that used for (5.13). We must firstly get an expression for the peak
inductor current. It can be seen from Figure 5.15 that iLpeak can be written as:
Vo ∆1 Ts
iLpeak =
L
We are now a position to calculate the average inductor current over a period.
This is most easily carried out by calculating the area under the iL current in
Figure 5.15 for a complete control cycle and dividing by Ts . Therefore we can
write:
1
2 iLpeak (DTs + ∆1 Ts )
Io = (5.19)
Ts
1
= iL (D + ∆1 ) (5.20)
2 peak
1 Vo ∆1 Ts
= (D + ∆1 ) (5.21)
2 L
average inductor Substituting for Vo using (5.18) one can manipulate (5.21) to give:
current discontinu-
ous mode 1 Ts Vd
Io = D∆1 (5.22)
2 L
Clearly this can also be expressed in terms of the minimum load current that
results in discontinuous conduction using (5.16) to give:
Substituting (5.24) into (5.18) and rearranging we get the final expression for
the voltage ratio:
Vo D2
= (5.25)
Vd D2 + 1 Io
4 ILBmax
Remark 5.29 The most notable feature of (5.25) is that the voltage ratio is
now non-linear. In other words there is a non-linear gain through the converter. voltage ratio is now
Clearly this complicates the design of the control. Furthermore, the onset of non- non-linear
linearity with the onset of discontinuous current would make the control even
more difficult if the converter moved from continuous current to discontinuous
current operation.
Figure 5.16 is a plot of (5.25) in the discontinuous region, and (5.9) in the
continuous region.
Remark 5.30 As noted in the previous remark, the voltage ratio to duty cycle
relationship for discontinuous operation can be seen, from Figure 5.16, to be
very non-linear .
D =10
.
1 Boundary for onset of
discontinuous current D = 0.9
0.8 D = 0.8
D = 0.7
D = 0.6
Vo 0.6 DISCONTINUOUS
Vd CURRENT D = 0.5
CONTINUOUS
REGION D = 0.4
0.4 CURRENT
REGION
D = 0.3
D = 0.2
0.2
D = 01
.
D = 0.0
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Io
I LB
max
Figure 5.16: Voltage ratio of the buck converter for continuous and discontinuous
operation modes and constant Vd . NB. ILBmax = T8L s Vd
150 Fundamental Topologies
Remark 5.33 As can be seen from (5.34) the relationship between D and Vo /Vd
is again highly non-linear. As in the constant Vd case, the control for constant
Vo would be much simpler if on maintains operation in the continuous current
mode.
1
Vd
= 125
.
Vo
0.8
Vd
= 15
.
Vo
CONTINUOUS
0.6 Vd
CURRENT = 2.0
D REGION Vo
Vd
0.4 DISCONTINUOUS = 3.0
Vo
CURRENT
REGION Vd
= 4.0
Vo
0.2
Vd
= 5.0
Vo
0
0 0.2 0.4 0.6 0.8 1 1.2
Io
I LB
max
Remark 5.34 The ILBmax in Figure 5.17 is different from that in Figure 5.16.
Figure 5.17 shows the inter-relationship between the duty cycle, load cur-
rent and inverse voltage ratio for the buck converter. The non-linearity in the
discontinuous current region of operation is very evident from the figure.
Remark 5.35 Figures 5.16 and 5.17 are actually equivalent. For example, at
D = 0.5 in Figure 5.16 VVdo = 0.5 and ILB Io = 1. The corresponding
max(D=0.5)
Vd Vo Io
point in Figure 5.17 is Vo = 2 (i.e. Vd = 0.5), D = 0.5 and ILBmax(D=0) = 0.5.
152 Fundamental Topologies
The latter can be seen from (5.27) and (5.16) as follows. From (5.16):
Ts Vd Ts V o Vo
ILBmax(D=0.5) = = (using Vd = ) (5.35)
8L D8L D
Ts V o
= (for D = 0.5) (5.36)
4L
1
= ILBmax(D=0) (5.37)
2
In the analysis thus-far we have assumed that the capacitor is large enough
that the voltage at the output does not change substantially. This was an
approximation that made the analysis simpler, but in reality is not true. In
many applications that ripple at the output is important – for example, in
power supply applications many circuits cannot tolerate significant ripple.
voltage ripple In order to get a feel for the voltage ripple we shall assume that the current
is continuous. A further simplification is that the impedance of the capacitor is
very much lower than the load resistance, and therefore we can assume that the
ac component of the current ripple all flows into the capacitor, and the average
current over a switching interval flows into the resistor. The following analysis
is with reference to Figure 5.18.
Remark 5.36 One can immediately see from Figure 5.18 that we are assuming
that the ripple is small enough to be insignificant compared to the voltage across
the inductor – hence the inductor voltages are drawn as piecewise constant.
Remark 5.37 One could also carry out a complete circuit analysis for the buck
converter and get very precise voltage ripple waveforms. The equations for this
are straight forward, but just a little messy.
vL ∆t
∆IL = (5.39)
L
vL
Ts
Vd - vo
0
t
-vo
iL DI L
2
DQ
I L = Io
Ts
0 2
t
vo
Vo DVo
0
t
Substituting this expression into (5.38) we can write the following expression
for the voltage ripple:
Ts Vo
∆Vo = (1 − D)Ts (5.41)
8C L
∆Vo 1 Ts2 (1 − D)
∴ = (5.42)
Vo 8 LC
This expression can be further manipulated into a form that highlights the
filtering requirements of the LC combination. Realising that:
1
fc = √ (5.43)
2π LC
where fs = 1/Ts .
Remark 5.38 Equation (5.44) emphasises that fact that making the filter pole
of the LC filter circuit much smaller than the frequency of the PWM results in
a lower output voltage ripple.
Remark 5.39 Note that (5.44) indicates that the ripple is independent of the
average inductor current (in continuous conduction mode). Therefore, keeping
in mind the assumptions made in the analysis, the load on the inverter does
not influence the amount of ripple. The most relevant of these assumptions in
relation to this issue is that the capacitor impedance is much lower than that of
the load.
5.4.3.4 Simulation
One can set up a computer simulation of the buck converter circuit. The partic-
ular simulator used for this exercise is the Saber by Analogy. The circuit set
up in the simulator is shown in Figure 5.19. The switching device is modelled
by a switch which has a very high off resistance, and a very low on resistance.
The diodes in the circuit are essentially ideal, in that they have a zero turn on
voltage.
If the load is set at 100Ω, the switching duty cycle to 0.5, and the switching
frequency to 100kHz, then the plot of Figure 5.20 results. Note that this low
value of load resistance ensures that the current is continuous in the inductor.
The plots shows the initial startup transient (that was missing from the steady
state analysis that we have carried out above). Once the transient has died
away then the output voltage settles to the 5 Volt level that is predicted from
the theory. The inductor current settles to the load current, which is Io =
5/100 = 0.05 Amp. Notice that the capacitor current is essentially zero. If
one magnifies the graph it can be seen that the capacitor is absorbing the ac
currents resulting from the high frequency switching.
5.4 Basic Analysis of Switch Mode Converters 155
prbit_l4 prbit_l4
BIT BIT
STREAM STREAM
50e-3
sw1_l4
10 pwld pwld
v_dc
100e-6 40000
(A) : t(s)
0.2
Capacitor cur
(A)
0.0
-0.2
(A) : t(s)
0.4
Inductor cur
0.2
(A)
0.0
-0.2
(V) : t(s)
10.0
v_o
8.0
6.0
(V)
4.0
2.0
0.0
0.0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225
t(s)
Figure 5.20: Waveforms for a buck converter with D = 0.5, RL = 100, and
continuous inductor current.
156 Fundamental Topologies
Remark 5.40 One can also simulate the performance of the buck converter if
there is discontinuous current flow in the inductor. However, the simulation
time required for the system to go into steady state is very long due to a problem
with the initial transient. This phenomena can be seen in Figure 5.21 which
shows the currents for a 50% duty cycle and a load resistance of 40kΩ. Notice
that we get an initial LC transient which leaves the capacitor with a charge of
approximately 9 Volts (i.e. about twice the applied average voltage of 5 Volt).
Once this voltage has appeared on the capacitor it can only dissipate via the load
resistor. Therefore the time for the voltage to decay to the steady state value is
of the order of 4 to 5 seconds.
Remark 5.41 The slow transient that is evident in Figure 5.21 would not occur
in a practical discontinuous mode buck converter. It occurs in the example case
because the converter control is open loop. In a practical converter the duty
cycle is varied depending on the error between the output voltage and the desired
output voltage, so as to force the output voltage to the desired.
(A) : t(s)
0.2
Capacitor cur
(A)
0.0
(0.11243, 167.57u)
-0.2
(A) : t(s)
0.2
Inductor cur
(A)
0.0
(0.11243, 70.099u)
-0.2
(V) : t(s)
10.0
v_o
8.0
(0.11243, 8.8035)
6.0
(V)
4.0
2.0
0.0
0.0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225
t(s)
Figure 5.21: Initial startup waveforms for a buck converter with D = 0.5,
RL = 40kΩ, and discontinuous inductor current.
Rearranging this gives the voltage ratio of the converter: boost converter
voltage ratio
Vo Ts 1
= = (5.46)
Vd toff 1−D
Assuming a lossless circuit we can say that Pd = Po , and hence:
Vd Id = Vo Io (5.47)
which can be rearranged to give the current ratio of the converter: boost current ratio
Io
= (1 − D) (5.48)
Id
vL
Vd
A
0 t
B
Vd -Vo
iL
Ts
IL
0
t
t on t off
iL iL
io io
L L
+ vL - + vL -
Vd C Vo Vd C Vo
Remark 5.42 Equation (5.46) indicates that the voltage ratio goes to infinity
if D = 1. This arises from the fact that the steady state assumption means via
(5.45) that the output voltage becomes increasingly large as D → 1.
158 Fundamental Topologies
Remark 5.43 Equation (5.46) indicates that the voltage ratio is not linear for
a boost converter. A plot of the voltage ratio is shown in Figure 5.23. Note the
very large increase in the voltage ratio as D → 1. In reality this increase does not
occur. The analysis that lead to (5.46) involved ideal components. However, if
one includes resistance in the inductors and capacitors, and accounts for the very
poor switch utilisation under large duty cycles, then as D → 1, then Vo /Vd → 0,
and not ∞.
100
90
80
70
60
Vo
50
Vd
40
30
20
10
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
D (Duty Cycle)
Equation (5.51) can be further manipulated by realising that the inductor cur-
rent and the input current in this converter are the same (i.e. id = iL ). Therefore
using (5.48) we can say that Io = (1 − D)IL , and hence: output current
continuous current
Ts Vo boundary
IoB = D(1 − D)2 (5.52)
2L
iL
peak
I LB
0 t
Vd -Vo
t on t off
Ts
If we consider that the output voltage of the boost converter is kept constant,
then one can differentiate (5.51) and equate to zero to get the value of D = 0.5
for the maximum value of inductor current at the edge of continuous conduction.
This value of current is: maximum inductor
Ts Vo continuous current
ILBmax = (5.53)
8L boundary
Similarly, one can differentiate (5.52) and equate to zero to get the maximum
value of IoB at D = 1/3. The value of IoB is: maximum output
continuous current
2 Ts Vo Ts Vo boundary
IoBmax = = 0.074 (5.54)
27 L L
Both ILB and IoB can be expresses as follows in terms of their maximum
values:
I LB
max
1
0.9
I LB
0.8
0.7
I oB = 0.59I LB
max max
0.6
I
0.5
I LB
max
0.4 I oB
0.3
0.2
0.1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
1 D
3
Figure 5.25: Plot of the normalised continuous current boundary for the boost
converter (Vo constant).
5.4 Basic Analysis of Switch Mode Converters 161
Remark 5.44 Figure 5.25 can be interpreted in the following way. If the cur-
rent in the inductor is less than ILB then the converter will begin to operate
with discontinuous inductor current. This translates to the output current be-
ing less than IoB , since the inductor current is not the output current for this
type of converter. Notice that the largest value of the continuous output current
boundary occurs at D = 0.33, which does not correspond to the point where the
largest value of the continuous inductor current boundary occurs. This is due to
the fact that the inductor current does not linearly relate to the output current.
Remark 5.45 Figure indicates that for continuous current flow in the inductor,
either keep the inductor current above ILB , or the output current above IoB . If
the output is above IoB , then IL is above ILB , and vice-versa.
iL Current is
peak
zero here
IL
v L = Vd iL
0 t
Vd -Vo
Ts
Figure 5.26: Current waveforms for the boost converter with discontinuous cur-
rent.
The integral of the voltage over one control interval must be equal to zero for
the circuit to be in steady state. Therefore we can write the following equation: discontinuous volt-
age ratio
Vd DTs + (Vd − Vo )∆1 Ts = 0 (5.57)
Vo ∆1 + D
∴ = (5.58)
Vd ∆1
162 Fundamental Topologies
Again using the fact that the converter is assumed to be lossless, then we can
say Pd = Po , and hence the current ratio under discontinuous operation is: discontinuous cur-
Io ∆1 rent ratio
= (5.59)
Id ∆1 + D
If we consider Figure 5.26, and using the fact that the current waveform can
be broken down into a number of triangles, we can calculate the average input
current. The peak current is:
Vd DTs
iLpeak = (5.60)
L
discontinuous aver- and hence the average input current can be deduced to be:
age input current Vd DTs
Id = (D + ∆1 ) (5.61)
2L
discontinuous aver- Using (5.59) one can write the average output current expression as:
age output current
Ts Vd
Io = D∆1 (5.62)
2L
We can use (5.58), (5.62) and (5.54) to get an expression for the duty cycle in
terms of the voltage ratio and the output current. From (5.54) we can write:
Ts 27
= IoBmax (5.63)
L 2Vo
and from (5.58) one can write:
D
∆1 = (5.64)
Vo
Vd −1
Substituting both of these into (5.62) and manipulating one can get the expres-
discontinuous duty sion:
cycle 4 Vo Vo Io
D= −1 (5.65)
27 Vd Vd IoBmax
Using (5.65) we can develop a plot of D versus Io /IoBmax for various Vo /Vd .
The normal operating mode would be that Vo is constant, and Vd is varying.
The development of this plot is slightly complicated due to the fact that the
Io /IoBmax for discontinuous current is a function of the duty cycle. Using (5.56)
and (5.65) it is possible to get the following expression for the limit on the duty
cycle for discontinuous conduction, for a given value of Vd /Vo :
2
2 − 1 (1− 1 ) ±
1
2 − 1 (1−
1
1 −4
x x x x)
Dlim = (5.66)
2
where x = VVdo . The negative of the two solutions gives a value of D in the valid
range of 0 → 1. This sets the limit on the D values, and therefore a limit on
the Io /IoBmax range via (5.56). The characteristics of the boost converter with
a constant Vo are shown in Figure 5.27.
Remark 5.46 One can see from Figure 5.27 that the duty cycle has a highly
non-linear relationship to the output current in the discontinuous region of oper-
ation. Once outside this region the duty cycle is constant for a particular voltage
ratio output.
5.4 Basic Analysis of Switch Mode Converters 163
1 Vd
= 0.1
Vo
0.9
Vd
0.8 = 0.25
Vo
0.7 CONTINUOUS
Vd
0.3 = 0.75
Vo
0.2 Vd
= 0.9
Vo
0.1
0
0 0.2 0.4 0.6 0.8 1 1.2
Io
I oB
max
Figure 5.27: Duty cycle versus normalised output current for the boost converter
with constant Vo .
164 Fundamental Topologies
5.4.4.3 Simulation
To complete this section on the boost converter we shall construct a simulation
of the circuit shown in Figure 5.28. The circuit simulated has the switch output
switch closed, therefore the load resistance is approximately 100Ω.
The voltage output of the circuit, inductor current, load current, and en-
ergy stored in the output capacitor and with a 50% duty cycle is shown in
Figure 5.29. Notice that the output voltage is 2Vd , as one would predict from
(5.46). After the initial startup transient the energy in the capacitor settles
to a dc value, indicating that the circuit is now in steady state. The inductor
current is essentially constant, which means that the current being pulled from
the supply is very close to constant.
The effect of applying several different duty cycles when there is continuous
conduction is shown in Figure 5.30. Again the simulation output conforms
almost exactly to the predicted values of the output using (5.46).
prbit_l4
BIT
STREAM prbit_l4
BIT
STREAM
pwld 100
v_o
50e-3
sw1_l4
sw1_l4
v_dc 10 100e-6 40000
(J) : t(s)
0.04
Cap energy
(J)
0.02
0.0
(A) : t(s)
0.4
I_o
(A)
0.2
0.0
(A) : t(s)
0.8
Inductor cur
0.6
(A)
0.4
0.2
0.0
(V) : t(s)
40.0
v_o
(V)
20.0
0.0
0.0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22
t(s)
Figure 5.29: Simulated waveforms for a boost converter with D = 0.5 and
continuous current.
(V) : t(s)
60.0
v_o;D=0.5
v_o;D=0.8
50.0
v_o;D=0.2
40.0
(V)
30.0
20.0
10.0
0.0
0.0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225
t(s)
Equation (5.67) can easily be shown to hold for the single switch version of
the converter as in Figure 5.5. The situation with discontinuous current is more
complex, and cannot be considered to be a cascade of the individual converters
under this condition.
Vd
ON
0
t
OFF
Vd -VC = -Vo
1
vL
2
VC -Vo
1
ON
0 t
OFF
-Vo
iL
1
IL
1
0
t
iL
2
IL
2
0
t
(1 - D )Ts DTs
(= t on ) (= t off )
Under the constant VC1 and steady state operation assumptions, the integral
of the voltages across the inductors must be zero. Therefore we can write:
and
Vo D
= (5.73)
Vd 1−D
As with the previous converter analysis, if we assume that the converter is
lossless, then we can develop the current ratio: Cúk current ratio
Io 1−D
= (5.74)
Id D
Remark 5.47 Equations (5.73) and (5.74) are the same as those for the buck-
boost converter.
One can calculate the current and voltage ratios using an alternate technique
based on the charge transferred by the capacitor. This technique is illuminating
in that it emphasises the fact that it is the capacitor that is storing the energy
that is being transferred from the source to the load. It shall be assumed that
the inductors, L1 and L2 , are large enough that the ripple in the currents can
be ignored – i.e. iL1 = IL1 and iL2 − IL2 . If the circuit is in steady state then
the total charge delivered to the capacitor over a complete control interval is
zero. This can be expressed mathematically as follows:
Using the lossless argument once again (Po = Pd ), then one gets:
Vo D
= (5.77)
Vd 1−D
Remark 5.48 The assumption stated above essentially means that one of the
switches in a leg is switched on at a particular instant of time. As we shall see
later, if both switches are open in a leg, then the output voltage is no longer a
function of the switch states, but depends on the direction of the load current
from the leg.
The alternative switching position for Leg A is SWA+ off and SWA− on. In
this case a positive current flows through DA− and a negative current through
SWA− . Hence in both cases the Leg A load connection is connected to the nega-
tive of the supply, which is also the reference point for the voltage measurements.
Therefore:
vAN = 0 (for SWA− on and SWA+ off) (5.79)
Remark 5.49 Expressions (5.78) and (5.79) indicate that the output voltage
is dependent only on the status of the switches, and not on the direction of the
current.
Given Remark 5.49 then the output voltage of Leg A averaged over a complete
switching cycle Ts , depends only on the input voltage Vd and the duty ratio of
SWA+ . Therefore the average Leg A voltage is:
Vd ton + 0 · toff
VAN = = Vd · duty cycle of SWA+ (5.80)
Ts
independent of io .
Given VAN and VBN , then we can calculate the output voltage for the con-
verter as follows:
Vo = VAN − VBN (5.82)
Equation (5.82) is a general expression for the output voltage.
It was mentioned in Section 5.3.5 that there are two main strategies for
arranging the switching in full bridge converters. We shall now investigate
these strategies in detail.
v tri
V$tri
v control
A t
t1 t1 Ts / 2
Ts
v AN
Vd
10 01 10 01 10
B t
v BN
Vd
10 01 10 01 10
C t
vo = v AN - v BN
Vd
Vo
D 10 01 10 01 10 t
-Vd
I o + ve
io
Io
E SWA + D DA + SWA +
t
A-
SWB - D DB - SWB -
B+
SWA-
I o - ve SWB +
io
F t
-I o
SWA + SWA- DA + SWA +
SWB - SWB + DB - SWB -
DA-
DB +
Figure 5.32: Waveforms for a full bridge converter with a bipolar switching
strategy.
170 Fundamental Topologies
voltage reference point. Therefore, for a particular leg voltage one has to simply
find the scaling factor for the control voltage or the triangular wave.
From Figure 5.32A we can see that:
1
vtri = V̂tri Ts t (5.83)
4
At the switching time t1 one can see that vtri = vcontrol . Substituting this into
the above expression we can write:
vcontrol Ts
t1 = (5.84)
V̂tri 4
Again referring to Figure 5.32A we can see that the total on time for Leg A of
the inverter is:
1
ton = 2t1 + Ts (5.85)
2
We can now use (5.2) to give the duty cycle for the SWA+ and SWB− switch
Leg A duty cycle pair:
ton 1 vcontrol
D1 = = 1+ (5.86)
Ts 2 V̂tri
Leg B duty cycle The duty cycle for the SWB+ − SWA− leg (i.e. leg B) is therefore:
D2 = (1 − D1 ) (5.87)
Remark 5.50 Equation 5.89 indicates that the output voltage is linear with
respect to the control voltage. This makes the control of the converter fairly
simple.
Remark 5.51 From Figure 5.32 it can be seen that the voltage across the load
is bipolar in nature, hence the name of this switching strategy. It should also be
noted that the fact that the voltage is going from positive to negative will result
in higher ripple in the output current, as compared to any strategy that keeps
the voltage unipolar.
Remark 5.52 From (5.88) it can be seen that as the duty cycle D1 is varied
from 0 to 1 the output voltage varies from −Vd to Vd . This variation is indepen-
dent of the direction of the current, although different switching components are
responsible for the conduction of the current depending on the current direction.
This can be seen from Figure 5.32E and F, where the various conduction devices
are shown.
5.4 Basic Analysis of Switch Mode Converters 171
v tri
V$tri
v control
A t
t1 t1 t1 t1 t1
-v control
Ts
v AN
Vd
10 00 10 11 10 00 10 11
B t
v BN
Vd
10 00 10 11 10 00 10 11
C t
vo = v AN - v BN 2t 1 2t 1
Vd
Vo
10 00 10 11 10 00 10 11
D t
-Vd
I o + ve
DA + SWA +
D SWB - io
B-
Io
E SWA +
t
SWB -
SWA-
DA- DB -
I o - ve SWB -
SWA-
DB - io
F t
-I o SWA + DA +
SWB - DB -
DA-
DA + SWB -
DB -
Figure 5.33: Waveforms for a full bridge converter with a unipolar switching
strategy.
5.4 Basic Analysis of Switch Mode Converters 173
Vd
Vo = (2D1 − 1)Vd = vcontrol (5.95)
V̂tri
Remark 5.54 Because of the effectively higher switching frequency of the unipo-
lar strategy, it is the preferred method of switching for these types of converters.
Let us now consider the switch utilisation of the generic converter types that
we have considered in this chapter.
5.4.8.1.1 Buck Converter The peak voltage across the switch is:
VT = Vd (5.97)
This can be written in terms of the output voltage using (5.9) allowing the peak
switch voltage to be written as:
Vo
VT = (5.98)
D
Examination of Figure 5.2 reveals that the peak current through the switch must
be the same as the average load current, since when the switch is closed the two
currents have to be the same (via the no inductor current ripple assumption).
Therefore:
IT = Io (5.99)
Using these two expressions for VT and IT we can write the expression for the
switch rating power:
Vo Io
PT = VT IT = (5.100)
D
buck converter Therefore:
Po Vo Io
switch utilisation Us = = Vo Io = D (5.101)
PT D
5.4.8.1.2 Boost Converter A similar analysis for the boost converter can
also be carried out. Again the basic equations for the voltage ratio, (5.46), and
the current ratio, (5.48) can be used.
The key to getting the switch utilisation in this case is to realise that the
average input current id and the inductor current iL are the same. Since we are
assuming that the inductor is large enough that there can be little ripple in the
inductor current, then the switch current must also equal the inductor current.
The same assumption also means that we can replace the instantaneous currents
with their average values (since they will be the same). Therefore id = Id and
iL = IL . We can therefore write:
IT = Id (5.102)
Using (5.48) we can relate the Id and Io , therefore we have:
Io
IT = Id = (5.103)
1−D
From Figure 5.3 one can see that the peak voltage across the transistor is
the output voltage – i.e.:
VT = Vo (5.104)
allowing the switch peak power to be written as:
Vo Io
PT = VT IT = (5.105)
1−D
boost converter and the switch utilisation as:
switch utilisation Po Vo Io
Us = = =1−D (5.106)
PT Vo Io
1−D
5.4 Basic Analysis of Switch Mode Converters 175
ID
iD = (5.108)
D
Input
current
iD
ID
t
DTs (1 - D )Ts
Figure 5.34: The input current into a buck-boost converter with a large input
inductance.
The maximum voltage across the switch (from Figure 5.5) can be seen to
be:
VT = Vd + Vo (5.110)
176 Fundamental Topologies
1−D Vo
VT = Vo + Vo = (5.111)
D D
Using (5.109) and (5.111) we can now write the peak switch power:
1
PT = VT IT = Vo Io (5.112)
D(1 − D)
The Cúk converter has the same switch utilisation as the buck-boost con-
verter.
Remark 5.56 The division of the single switch utilisation is a technique for
saying that the converter is using more silicon than other converters. However,
it should be noted that each individual switch has to satisfy the peak power prior
to being divided by four.
From Figure 5.9 it is obvious that the peak voltage across a switch is:
VT = Vd (5.114)
IT = Io (5.115)
PT = VT IT = Vd Io (5.116)
We need to get the output power. Since we have expressed the peak switch
power in terms of Vd we need to get the output power in terms of this as well.
This can be achieved by using (5.89) in conjunction with (5.86) which allows us
to write:
vcontrol = V̂tri (2D1 − 1) (5.117)
and hence:
Vo = Vd (2D1 − 1) (5.118)
and therefore the output power is:
The best way to get an overall comparison of the switch utilisation for the
various converters is to plot the switch utilisation versus duty cycle for them.
This plot is shown in Figure 5.35.
Remark 5.57 One can see from Figure 5.35 that the buck-boost converter, the
Cúk and the full bridge converter do not have good switch utilisation as compared
to the buck or the boost converter. Therefore, where possible it is better to use
these converters, since a lower cost switch can be used for a given application.
0.9
Boost Buck
0.8
0.7
0.6
Po
Buck-boost
PT 0.5
and Cuk
0.4 Full bridge
0.3
0.2
0.1
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
D
Figure 5.35: Plot of switch utilisation for the common converter types.
Remark 5.58 If both higher and lower voltages than the supply are required
then one has to use either the buck-boost or the Cúk converters. A significant
advantage of the Cúk converter is that the front end of the converter looks like
that of the conventional boost converter. Therefore it shares the property of this
inverter that the input current is reasonable constant, and hence the filtering of
the input is significantly simplified as compared to the buck-boost converter where
178 Fundamental Topologies
the input (and output) currents are highly discontinuous. Similarly the output
current of this converter can also be kept almost constant. A disadvantage of the
Cúk converter is that the capacitor has to have a high ripple current capacity.
Remark 5.59 The full bridge converter should only be used if four quadrant
operation is required.
Remark 5.60 One other advantage of using synchronous rectifiers is that one
can make sure that there is continuous conduction under all load conditions.
This occurs because the current can flow in either direction through the inductor
with a series MOSFET as opposed to a diode.
Synchronous
+V +V rectifier
(a) (b)
SW Lr Lf
Io
+
Vd Cr D Cf RL
-
Cr
Dr
SW Lr Lf
Io
+
Vd D Cf RL
-
iL
D1 L
+ vL -
N1 N2 D2 C RL Vo
Vd
C SW Vd
SW
t
Switch voltage
6.1 Introduction
In the previous chapter we looked at some fundamental topologies for switch
mode converters. In this chapter we shall build on this basic information by
considering some topologies that are used for commonly available switch mode
power supplies (SMPSs). Towards the end of the chapter we shall consider some
aspects of the control of these power supplies.
When the switch in the buck converter is opened then the input is discon-
nected from the output. In the forward converter this occurs due to the fact
that the voltage across the transformer reverses (because of the trapped flux in
the transformer), and the diode D1 is reversed biased and disconnects the load
from the transformer secondary.
Remark 6.1 The above-mentioned trapped flux in the magnetising inductance
of the transformer is a new problem that does not exist in the conventional
buck converter. If one were to operate the forward converter as described in the
paragraph above then the switch would be destroyed by the very high voltages
created as the flux in the magnetising flux attempts to maintain the current
through the open switch.
iL
D1 L
+ vL -
N1 N2 D2 C RL Vo
Vd
SW
practical forward Figure 6.2 shows a practical forward converter circuit. In this circuit we in-
converter troduce a third winding to transfer the energy trapped in the magnetising in-
ductance back to the supply. This winding plays no part when the switch is
turned on, but when the switch is turned off and the voltage across the mag-
netising inductance reverses then, due to the turn direction of the third winding,
diode D3 turns on and current flows back into the supply. This limits the rate
at which the flux collapses in the magnetising inductance, and therefore the
voltage induced by this collapse is controlled.
The operation of the circuit can be better understood by referring to the
equivalent circuit in Figure 6.3. This circuit is based on using the concept of
the ideal transformer that does not require any mmf to operate.1 Ignoring the
leakage inductances, the flux is stored in the Lm inductance. When the switch
is closed current builds up in this inductance, and at the same time current,
i1 flows into the transformer. The voltage v1 appears across the magnetising
inductance, and this is reflected via the transformer voltage ratio to winding 2
1 The transformer has a magnetic structure with infinite permeability and consequently the
coupling between the windings is one. This also implies that the primary winding has infinite
inductance.
6.2 Isolated Converter Topologies 185
iL
D1 L
N3 + vL -
N1 N2 D2 C RL Vo
Vd
D3
SW
Ideal transformer
i3
Ll1 i2 Ll 2 iL
i1 D1 L
N3
+ vL -
Lm im v 1 N N2 D2 RL Vo
1 C
Vd
D3
v sw SW
Remark 6.2 In order to minimise the leakage inductance the primary and
ternary winding are often bifilar wound – i.e. they are both wound on the same
arm of the transformer. The secondary may not be wound like this as large
voltage isolation between the primary and secondary is often very important.
Remark 6.3 In order to catch any voltage spikes associated with the leakages
one may need some “snubbers” across the switch.
Remark 6.4 The wire used for the ternary winding can be much smaller gauge
than the secondary winding as it only has to carry the magnetising current of
the transformer.
Now let us consider the operation of this forward converter in a little more
detail. Assuming for the moment that we are dealing with the ideal forward
converter as depicted in Figure 6.1, and assuming that the transformer is ideal.
If the switch is turned on, then there will be current flowing through the trans-
former primary, and hence the secondary. Since the voltage ratio of a trans-
former is:
v2 N2
= (6.1)
v1 N1
then we can deduce that:
N2
vL = Vd − Vo for 0 < t < ton (6.2)
N1
circuit. The trapped energy in the filter inductor causes the diode D2 to turn
on, allowing current to circulate. In this case the inductor voltage is:
vL = −Vo for ton < t < Ts (6.3)
which is negative, resulting in a decreasing current in the filter inductor.
If one integrates the inductor voltage over one complete period and equate
to zero one gets: forward converter
Vo N2 voltage ratio
= D (6.4)
Vd N1
Remark 6.5 One can see from (6.4) that the voltage ratio is the same, in
principle, as that for the buck converter. However, whilst a buck converter
can only produce voltages less than the input voltage, the forward converter can
produce voltages that are greater than the input voltage with an appropriate turns
ratio for the transformer.
As we have previously noted, in a practical forward converter one must ac-
count for the energy trapped in the magnetising inductance. Let us now consider
how this requirement alters the operational range of the converter output volt-
ages. The following discussion is with reference to Figures 6.3 and 6.4. When
v1
Vd
N1 tm
- Vd
N3
t on t off
Ts
isw
i1 im
i1 = im
iL
Remark 6.6 Equation (6.11) indicates that the maximum duty cycle is 0.5 if
N1 = N3 (a common choice in many designs).
SW1
Vd N1 N2 Vo
SW2
D1 L
C RL Vo
N1 N2
N1 N2
Vd
D2
SW1 SW2
i.e. it does not require any mmf to magnetise it. The magnetising current is
flowing through the magnetising inductance to produce the flux that is present
in any “real” transformer.
When SW1 is opened then we have the situation shown in Figure 6.8. On
the primary side of the transformer there are two main effects to consider.
The current shown in Figure 6.7 flowing through the leakage inductance of the
primary (Ll ) wishes to continue flowing. Therefore a voltage is developed across
the leakage in an effort to achieve this. This voltage appears in conjunction with
the supply voltage across SW1 – this is voltage vLl +Vd in Figure 6.8. A snubber
is often required across the transistors to cope with this voltage spike.
Ideal transformer
Vd
N2
Ll iL D1 L
N1
N2 iL
i L + im N2
N1 im Lm Vd Vd C RL Vo
N1 N2 N
1
N1 N2 N2
V
SW1 N1 d
D2
Diode is open
circuit.
Figure 6.7: Currents flowing in the push-pull forward converter with SW1 closed.
The second salient point on the primary side of the circuit is that the current
flowing through the magnetising inductance cannot be changed instantaneously.
Therefore a voltage would normally develop across the magnetising inductance
in an effort to maintain this current. This voltage has a polarity with the
positive on non-dotted terminal of the top half of the transformer. However,
this is coupled by the ideal transformer to the secondary. This would produce
a positive voltage on the non-dotted terminals of the secondary. Consequently
the diode D2 would become forward biased. Diode D1 also remains forward
biased as well, meaning that the (constant) iL current splits between D1 and
D2 . This then provides a path for the magnetising current to flow. If this circuit
was a normal push-pull inverter circuit then the diode across SW2 would turn
on and clamp the voltage across the top half of the winding to Vd . However,
the presence of the full wave rectifier circuit on the secondary side of the circuit
changes this “normal” scenario.
One point that is not obvious in Figure 6.8 is why does the current iL split
between the two secondary windings? When D2 becomes forward biased why
doesn’t D1 become reverse biased? The answer to these questions is that the
constant load inductor current prevents this from happening. If D1 attempts
192 Switch Mode Power Supplies
Ideal transformer
Vd
Ll im D1 L
+ vL iL N1 iL
l
- im
im Lm 2 N2 C RL Vo
N1 N2
iL
+
N1 N2 i N1
L
+ im
SW1 2 N2
v L +Vd
l
D2
Both diodes
short circuit
Figure 6.8: Currents flowing in the push-pull forward converter with SW1 and
SW2 open.
to turn off, then the load current would immediately be diverted into the lower
half of the secondary. This would mean that a voltage would be induced in
this part of the winding (since a rate of change of flux in the core would result)
such that diode D2 would turn off, and D1 would turn on. Therefore the stable
situation is that shown in Figure 6.8. Note that due to the dots on the secondary,
the iL /2 current in each half of the windings would produce fluxes that cancel
each other. Therefore the only component of flux producing current is the
magnetising component reflected into the secondary which circulates around the
loop comprising the two diodes and the transformer secondaries. Another way
of reasoning this is to realise that when SW1 is opened the reflected iL current
must become zero. Consequently the effective iL current through the secondary
of the transformer must also be zero (else we cannot have zero reflected iL on
the primary side). Given that iL is held constant by the filter inductor, the
only way that this can be achieved is if there is net zero flux produced by the
secondary winding due to iL . This is achieved by D1 and D2 both being on,
since this results in flux cancellation in the secondary winding.
There is an alternative way of reasoning the splitting of the inductor current
between the two secondary windings. This technique is simple, and can be
applied to very complex coupled winding situations. For the moment consider
the transformer to be ideal – i.e. the magnetising inductance is infinite. With
SW1 closed all the current flowing in the primary is reflected into the secondary.
In terms of mmf, an ideal transformer does not require any mmf to set up the
flux in the core. Therefore we have:
N1 i1 + N2 iL = 0 (6.12)
Remark 6.7 One potential problem with the push-pull converter is that the
switches are subject to maximum voltages of 2Vd . For low voltage applications
this is of little consequence, but for mains line applications with 240VAC this
means that the devices will be subject to minimum voltages of 700V. Therefore,
1000V MOSFETs are required to ensure that there is sufficient over voltage
capacity.
Remark 6.8 One of the potential problems with the push-pull circuit is that
small differences in the timing of the duty cycles of the two switches can lead to
offsets in the flux of the transformer. These timing differences can occur because
of differences between the turn-on times of the transistors, or differences in the
speeds of the firing circuits. Consider Figure 6.9 which shows a typical BH curve
for a ferro-magnetic material. As the ideal push-pull circuit operates it normally
moves from B1 to B2 via the hysteresis loop shown. If the “on” transistor is
driving the flux density to B2 , and its on-time is a little less than the other
transistor, then the flux density may not quite get to B2 , but instead only gets
to B2a . Therefore, when the other device turns on it will drive the flux density
to a value a little higher than B1 , B1a . This process will continue, and the
maximum flux density B1a will creep up higher on the BH characteristic. If the
process continues then the core will saturate at the higher flux densities and the
magnetising inductance of the core will become very small and excessive currents
will flow through the transistor that is on when this occurs. This often results
in transistor failure. Current mode control is often used to fix this problem.
MOSFET transistors also help, as they have a positive temperature coefficient,
and as they heat up more of the voltage is dropped across the device, thereby
robbing volt seconds from the magnetising inductance. The resistance of the
primary also helps via a similar mechanism.
Practical Issue 6.1 One very nice feature of the push-pull converter is that
both of the transistors are referenced to the same ground rail. This simplifies
the drive circuits for transistors as compared to other topologies where one has
transistors floating at different voltage levels.
194 Switch Mode Power Supplies
Loop with B
flux imbalance
Normal B1a
operation B1
loop
B 2a
B2 B1 = B 2
Vo
N1 N2 Vo
Vd Vd
SW
ered constant. We shall look in some detail at the variation of the flux in the
core, since it is the flux that stores the energy that is transferred to the load.
One can calculate the flux in an inductor by using Faraday’s Law:
N dφ
vL = (6.14)
dt
1 t
∴ φ(t) = vL (τ )dτ + φ(0) (6.15)
N 0
In the case when the switch is closed, as shown in Figure 6.11, there is a constant
voltage of Vd applied across the magnetising inductance, Lm . The secondary side
of the circuit may as well not be there, since the diode in the secondary effectively
disconnects the load from the primary. The load current Io is supported by
the capacitor. It is therefore important that the capacitor be large enough to
support the current and voltage appropriately during the switch “on” period.
Equation (6.15) can therefore be written as:
Vd
φ(t) = φ(0) + t for 0 < t < ton (6.16)
N1
and clearly the peak flux in the magnetising inductance at the end of the “on”
period is: flyback peak flux
Vd
φ̂ = φ(0) + ton (6.17)
N1
At the end of the time ton the switch is opened. Because the current flowing
in the magnetising inductance cannot change instantaneously, or alternatively
the total mmf in the transformer cannot change instantaneously, then a voltage
is induced on the secondary (the polarity determined by the dot convention), in
such a manner as to turn on the diode in the secondary. The circuit configuration
then changes to that shown in Figure 6.12. As can be seen from the figure a
voltage of Vo is produced across the secondary so that the diode turns on. The
voltage NN2 Vo is produced across the primary, with a polarity that will cause
1
iD = 0 Io
im Lm v1 N 1 N2 C RL Vo
Vd
N2 N2
v1 = Vd
N1 N1
SW
iD Io
im Lm N1 N 2 Vo C RL Vo
Vd
N1
v1 = Vo
N2
SW open
During the “off” stage of operation, the flux in the transformer core will
decrease from the peak value calculated in (6.17). Therefore the time evolution
of the flux during this time is again given by applying Faraday’s Law:
N1
N2 Vo
φ(t) = φ̂ − (t − ton ) (6.18)
N1
Vo
∴ φ(t) = φ̂ − (t − ton ) for ton < t < Ts (6.19)
N2
From (6.19) one can deduce, using (6.19) and (6.17), that the flux at the end of
the control interval: flyback flux at Ts
Vo
φ(Ts ) = φ̂ − (Ts − ton ) (6.20)
N2
Vd Vo
= φ(0) + ton − (Ts − ton ) (6.21)
N1 N2
We are again assuming that the system is in steady state, therefore the flux at
the beginning and end of a control interval must be the same. This means that:
Vd Vo
φ(0) + ton − (Ts − ton ) = φ(0) (6.23)
N1 N2
Vd Vo
∴ ton = (Ts − ton ) (6.24)
N1 N2
Rearranging this, and using (5.2) we can write: flyback voltage ratio
Vo N2 D
= (6.25)
Vd N1 1 − D
Remark 6.9 The voltage ratio in (6.25) is identical to the voltage ratio calcu-
lated for the buck-boost converter, as shown in (5.67).
The currents flowing in the circuit under the switch “on” and “off” conditions
are shown in Figure 6.13
Let us calculate the currents flowing in the Flyback converter. This analysis
basically follows the same procedure as the calculation of the magnetising flux.
Assume that the current at the beginning of a control interval has an initial
value of im (0). Therefore during the ton period the magnetising and switch
current is:
Vd
im (t) = im (0) + t for 0 < t < ton (6.26)
Lm
As with the flux, the peak magnetising current at the end of the “on” period is: peak magnetising
and switch current
Vd
îm = im (0) + ton (6.27)
Lm
Remark 6.10 Note that îm is also the peak current flowing through the switch.
198 Switch Mode Power Supplies
v1
Vd
0
t
N1
- Vo
N2
t on t off
Ts
f
f$
f(0)
iD
N2
im
N1
Io
Figure 6.13: The voltage, current and flux in the ideal Flyback Converter.
6.2 Isolated Converter Topologies 199
During the “off” period the switch current is obviously zero. During this time
the voltage across the magnetising inductance is of a polarity so that the current
decreases. The current during this period is:
N1
N2 Vo
im (t) = îm − (t − ton ) (6.28)
Lm
The current in the diode during this period is simply a scaled version of the
inductor current (by the transformer turns ratio). i.e.: flyback diode cur-
N1
rent
N1 N1 N2 Vo
iD (t) = im (t) = îm − (t − ton ) (6.29)
N2 N2 Lm
Using the equations that we have derived it is now possible to get the peak
magnetising current in terms of the load current and voltage and the duty
cycle. This is an important equation for this type of converter, since the peak
magnetising current needs to be known so that saturation of the core can be
avoided, and the switches can be sized. The first step is to work out the average
expression for the diode current, which is also equal to the average load current
(in steady state).
Taking the average of (6.29) and rearranging we can get the expression for
the peak current in terms of the average load current and the output voltage: peak switch current
N1
N2 Io 1 V o N2
îm = + (1 − D)Ts (6.30)
N1 (1 − D) 2 Lm
The peak voltage across the switch can be seen to be the supply voltage plus
the voltage produced by the transformer:
N1
vsw = Vd + Vo (6.31)
N2
Vd
vsw = (6.32)
(1 − D)
One of the main motivations for the use of SMPSs is their low weight and
volume. Therefore it is essential that the magnetic material is well utilised to
achieve these objectives.
Consider Figure 6.14 which shows a typical BH curve for a magnetic material.
The flux density Bm is the maximum flux density that can be achieved when
the material is saturated. The flux density Br1 is the remnant flux density when
the core is not being subject to an mmf.
B
Original magnetic
material (no air gap)
Bm
Br 1
Br 2
H
Magnetic material
with air gap
Figure 6.15 shows the excitation waveforms for a forward converter with
a feedback winding such that N1 = N3 (Figure 6.15(a)), and a full bridge
converter (Figure 6.15(b)) with the same primary turns. The voltage v1 is the
voltage across the primary winding. We shall assume that both converters are
operating with D = 0.5. ∆Bmax is the excursion of the flux density from the
average value of the flux density.
Note 6.2 It should be noted that the use of a full bridge converter in this mode
is entirely artifical. Under a duty cycle of 0.5 the average output voltage of this
converter is zero. The output could be used to drive a transformer connected
to a rectifier to get a different output voltage. If a modulation strategy using
zero voltage application is used then control of the DC output voltage could be
obtained.
The reason for the artifical D = 0.5 restriction is that this will force the flux
in the core (under appropriate start up conditions) to be bidirectional.
Remark 6.11 A better converter to use for this example is the push-pull con-
verter. This converter can perform all the functions of the full bridge if a DC
output is required, only involves two switches, and can be made to operate with
symmetric bidirectional flux in the core of the transformer (with modified firing
of the switches using a combination of current control and zero voltage applica-
tion).
Let us consider the expression for the maximum deviation of the flux density
away from the average value. We know from Faraday’s Law, (6.14), and the
6.2 Isolated Converter Topologies 201
v1 v1
Vd Vd
0 0
t t
t on t off t on t off
-Vd -Vd
DB DB
(DB )max
(DB )max
0 0
t t
1
Ts (= )
fs
1
Ts (= )
fs
(a) (b)
Figure 6.15: Core excitation waveforms. (a) forward converter. (b) full bridge
converter.
202 Switch Mode Power Supplies
relationship φ = BAc , where Ac the area of the core, that flux density can
be written as: ton
1
B= v1 dτ + B(0) (6.33)
N1 Ac 0
We are interested in the total change in B from whatever initial condition there
is. We shall call this ∆B. This allows us to ignore the initial condition B(0)
in the following evaluation.2 Assuming that D = 0.5 (which implies that ton =
Ts /2), and v = Vd then we can write:
T2s
1
∆B = Vd dτ (6.34)
N1 Ac 0
Vd Ts Vd
= = (6.35)
2N1 Ac 2N1 Ac fs
This value corresponds to the peak value of the flux in Figure 6.15(a). To
evaluate the average value we calculate the area under the ∆B curve and divide
by the time (since in Figure 6.15(a) the ∆B waveform is triangular). Therefore
using (6.35) the expression for ∆Bave is:
Vd Ts
2N1 Ac fs 2
∆Bave = (6.36)
Ts
Vd
= for D = 0.5 (6.37)
4N1 Ac fs
We can now find ∆Bmax , the maximum deviation of the flux from the average
flux, by subtracting (6.37) from (6.35) to give:
Vd
∆Bmax = for D = 0.5 (6.38)
4N1 Ac fs
Maximum flux ex- which is valid for both converters.
cursion. A little earlier we mentioned that we had ignored the initial value of the flux
density, but in the footnote we noted that this would be important. Referring
to Figure 6.14, one can see that when there is no excitation of the core that
the remnant flux density is Br . Therefore this point on the BH characteristic
is the starting point for any unidirectional flux excursion – i.e it is the initial
condition B(0) in (6.33). Therefore, using the definitions in Figure 6.14 the
forward converter flux excursion ∆Bmax becomes:
1
∆Bmax = (Bm − Br ) (6.39)
2
i.e. the flux excursion is limited by the remnant flux density in the core. Because
the flux is starting off with the Br offset, then the flux cannot undergo large
flux excursions.
In the case of the full bridge converter, the flux undergoes symmetric flux
density excursions about the zero flux density point in Figure 6.14.3 Therefore
2 Note the the initial condition is very important when it comes to evaluating the magnetic
excursions. Note that it is not intrinsic in the design of these converters that this would
happen.
6.2 Isolated Converter Topologies 203
∆Bmax = Bm (6.40)
What are the implications of these differences in the maximum flux density
that can be achieved with these converters? These can be gleaned by considering
(6.38) in the light of the above comments. Rearranging (6.38) we get:
Vd
Ac = (6.41)
4N1 (∆B)max fs
We can see from this expression that if ∆Bmax is large then Ac can be smaller.
Therefore, given the same applied voltages, duty cycle and switching frequency,
and for the same number of turns on the primary, the full bridge converter will
have a significantly smaller core for the magnetics as compared to the forward
converter.
Remark 6.12 Equation (6.41) assumes that fs is the same and N1 is the same
under the condition of smaller core cross-sectional area. However, as can be seen
from (7.23) in the following chapter, reproduced here for convenience:
µN12 Ac
L= (6.42)
lc
where lc is the magnetic path length of the core, the inductance of the core is
much less. This should also be obvious from the definition of inductance:
λ N1 BAc
L= = (6.43)
i i
If Ac is smaller, then for the same current i the B will be the same (via Amperes
Law), and therefore λ will be smaller.
Therefore implicit in (6.41) is the fact that the current is allowed to increase
when we have the smaller core area, since the same voltage is applied by the
converter across the winding for the same time, but the inductance is less.
Remark 6.13 As can be gleened from Remark 6.12 there is a trade-off for
the reduced size magnetics under the condition specified – for the same power
output we have a larger magnetising current, therefore higher losses, and larger
switching devices.
Remark 6.14 The fact that one does not have to demagnetise the core in the
push-pull converter means, without considering the maximum flux density issue,
one can produce more power from the same magnetic core. The effective maxi-
mum duty cycle is 1, whereas for the forward converter it is 0.5 (depending on
the relative turns ratio of the ternary winding).
Remark 6.16 One can see from (6.39) that the maximum excursion of the flux
in the forward converter is limited by the remnant flux in the core. Therefore
204 Switch Mode Power Supplies
one way to utilise the magnetics better in these types of converters is to reduce
the remanence. This can be achieved by putting an air gap in the core. This
to a large degree linearises the core operation, and also dramatically lowers the
remnant flux density. This effect is shown diagrammatically by the dashed BH
characteristic in Figure 6.14.
Under the condition of identical duty cycle, identical turns in the primary
winding and identical core area (i.e. the magnetising inductance of both cores
is the same), then flux in the cores is:
Forward converter:
For the push-pull converter, assuming appropriate control (i.e. current con-
trol), then:
Bave = 0 (6.47)
∴ Bmax = 0 + ∆Bmax = ∆Bmax (6.48)
Therefore the push-pull converter has less than half the peak flux density in the
core. This would means that the core losses in this converter would be lower
than the the forward converter (see below on core losses).
The other issue that can limit the utilisation of magnetic cores in switching
power supplies are core losses. The general expression for the core loss per unit
volume or weight is of the form:
b
Core Loss density = kfsa [(∆B)max ] (6.49)
concepts involved will be presented. There are many references on issues related
to the control of switching supplies, both in books and in several of the IEEE
Transactions, namely Power Electronics, Industrial Electronics, and Industry
Applications. Some of the books on these issues are [4, 12, 13].
Before looking at the control issues, we shall consider some broader topolog-
ical and practical issues of switching supplies. Consider Figure 6.16 which is a
block diagram of a typical switching power supply (from [4]).
Isolation
barrier
DC-DC power convertion
Rectifier HF Rectifier
and Power and
Mains filter Switches filter
Transformer
Supply
EMI DC Vo
AC
filter
HF
Signal
Transformer
Small
DC
Mains
Transformer
Rectifier
and
filter
Feedback circuitry Vo -ref
As can be seen from Figure 6.16 we have looked at the detail of the dc-dc
conversion section of the power supply in the first part of this chapter. The lower
half of the diagram is related to sensing of the feedback signals and the control
circuitry. The important point to note here is that the feedback signals have
to be isolated from the input if we are to have an isolated power supply. This
complicates the design of the supply considerably. The circuit of Figure 6.16
is a conceptual diagram of one way of designing the isolated feedback. In this
configuration the control circuitry and PWM generation is on the output side
of the isolation. The other alternative is to have this circuity on the supply side
of the isolation, and only the output voltage is feedback in an isolated fashion. feedback isolation
The relative merits of the control circuitry on the supply side and the output
side are not clear cut. Having the control circuitry on the output side (as in
Figure 6.16) has the advantage that one is transmitting pulsed signals (basically
firing pulses) across the isolation. This would also allow one to use an opto-
coupler instead of a signal transformer. On the negative side the base drive
circuitry is a little more complicated.
If the PWM and control circuitry is on the supply side then the base drive
206 Switch Mode Power Supplies
circuitry is usually a little simpler compared to the output side circuitry. On the
negative side, getting the output voltage and/or current in an isolated fashion
can be difficult. One technique is to use a voltage-to-frequency converter on
the output side, and a frequency-to-voltage converter on the supply side. Some
power supplies attempt to use opto-couplers in a linear mode of operation.
However, opto-couplers are an inherently non-linear device, and this is difficult
to do. To complicate the issue even further they are subject to temperature
variations.
One rather nice and simple technique of getting isolated feedback variables
with the control on the supply side is the circuit shown in Figure 6.17 which was
proposed in [13]. This circuit uses a small forward converter to transfer the ana-
logue voltage value of the output voltage across the isolation barrier. The BJT
is connected to the output of the main power converter, and is turned off and on
by the pulsating voltage here. This then operates a low power forward converter
that transfers the main converter output voltage via the transformer to main
converter primary reference. The small transformer would have a turns ratio so
that the output voltage is higher than the main converter output voltage. By
doing this any voltage drop across the rectifying Schottky diode is insignificant.
One crucial aspect of the performance of this circuit is that the duty cycle of the
main converter (which is used to control the small feedback forward converter)
does not affect the output voltage. This is achieved because the output circuit
is a peak detector, and the precise duty cycle does not affect the peak detected.
The peak is related to the output voltage of the main converter. The forward
feedback converter output voltage is then resistive divided to give a voltage that
is appropriate for the error amplifier. It is claimed that this circuit is capable
of giving an accuracy of 2% and has a bandwidth that is controlled by the RC
time constant of the capacitor/resistive divider network at the output of the
feedback circuit.
6.3.1 Start-Up
Another interesting practical aspect of a SMPS is how to start it up. The
dilemma takes the form of a chicken or egg argument – one needs power to start
the switching, and one needs switching to get power. The solution to this prob-
lem could take the form of that shown in Figure 6.16, where we have a separate
power transformer for the control logic. Power is therefore immediately available
for the PWM and feedback circuitry when the main power is applied. However,
in many situations this would be considered to be an expensive solution.
Another much lower cost solution is to use a control logic power winding, a
resistor and a capacitor [13]. This is suitable for converters where the control
logic is referenced to the primary. A circuit for this is shown in Figure 6.18.
Initially the transformer section of the circuit is inoperative. When power is
applied to the power supply the unregulated DC supply comes on-line. Conse-
quently the electrolytic capacitor in Figure 6.18 will charge up. The zener diode
is to limit the voltage to a value safe for the PWM generator IC. The PWM
generator now has enough voltage to operate.
Unfortunately many PWM generator ICs only have a small hysteresis band
of operation around the nominal voltage of operation. For example, the UC3825
PWM generator IC by Unitrode Semiconductor Products (now owned by
Texas Instruments ) operates with voltages from 9 Volts to a maximum of
6.3 Introduction to Control Techniques for Switching Power Supplies 207
Isolation
Main converter
barrier
output
Vo
P S
R1 S
v feedback R2
P
P
Feedback circuitry
Forward
converter
Unregulated
DC supply
Initial
charging
resistor
Vcc
+ PWM
Generator
Chip
Power winding
when running
Figure 6.18: Example of a simple bootstrap power circuit for a PWM generator
chip.
12 Volt and the gate threshold of the MOSFET to be 2 Volt. Therefore when
the voltage on the capacitor reaches approximately 14 Volt, zener both Z2 and
the MOSFET will be on. Consequently the PNP will turn on, and the 14 Volt
on the capacitor will appear on the Vcc pin of the PWM IC. The capacitor
will then begin to discharge. The PWM IC will continue to operate until the
capacitor voltage falls below its minimum operating voltage, which in the case
of a UC3825 is 9 Volt. Therefore, the circuit has created a voltage hysteresis
for 14 − 9 = 5 Volt.
Remark 6.17 The increased hysteresis created by the circuit shown on Fig-
ure 6.19 means that the capacitor can be a smaller size and still be able to keep
the PWM IC running long enough to allow the auxiliary winding to start to
supply the power to the PWM IC.
Remark 6.18 The charging resistor shown in Figures 6.18 and 6.19 is con-
stantly connected on the circuit. Therefore, even when the switch mode supply
is running, it will still dissipate power. However, this resistor can be made quite
large so that the power dissipated can be made small – the charging time of the
capacitor is not that important (within reason). The resistor is no longer really
supplying the current in the turn on phase, as it was with the previous circuit.
Alternatively one can use auxiliary circuitry to switch the resistor out, thereby
allowing a smaller resistor to be used.
6.3 Introduction to Control Techniques for Switching Power Supplies 209
Unregulated
DC supply
Initial
charging Hysteresis circuit
resistor
Vcc
+ PWM
Z1 Z2 RB RG
1 Generator
Chip
Power winding RG
when running 2
voltage to the chip itself, as well as from the Ilim/SD input (i.e. pin 9). The
later is activated by external circuitry to detect over voltage/under voltage to
the power circuit.
BLOCK DIAGRAM
U DG-92030-2
3/97
Figure 6.20: Block diagram of the Unitrode high speed PWM generator.
constant current Constant current limiting, as the name implies, is a form of current limit
limit where the current can only go to a particular value and then it will not increase
any more, regardless of the load. Therefore, even under short circuit conditions
the current will not increase appreciably above this limit value. This concept is
shown in a V0 I0 diagram in Figure 6.21. One point to note about this diagram
is that the voltage at the output of the converter can be appreciable under this
condition, depending on the impedance of the load.
Remark 6.19 The constant current limit may not be satisfactory in many ap-
plications, since the limit current may, over time, result in the thermal rating of
the inductor or transformer windings being exceeded. Therefore, if such a limit
is to be used, then one must ensure that the windings and power devices can
support the limit current indefinitely.
foldback current A slightly different limit is the foldback current limit. This limit is motivated
limit by the desire of reducing the currents flowing in abnormal short circuit or near
short circuit conditions. The operation of this current limit philosophy is shown
6.3 Introduction to Control Techniques for Switching Power Supplies 211
Vo
Load lines
Vo, rated
RL = R1
Vo1
RL = R2
Vo2
Io
I o, rated I limit
in Figure 6.22. In this case when the current reaches a limit value of Io, limit
then the current limit drops with the output voltage. Therefore under short
circuit conditions the current is reduced to a much lower value than in the
previous case. The power that is being supplied to the external circuit under
this condition is not nearly as high as in the constant current limit situation.
Remark 6.20 The foldback current limit does not solve the overheating problem
mentioned in the previous remark. If the circuit is operating at Io, limit then the
problem is the same as in the constant current limit case.
Vo
Load lines
Vo, rated
RL = R1
RL = R2
Vo1
Vo2 Io
I o, foldback I o,rated I o,limit
Most PWM ICs implement a two stage current limit. The current through
the switch is fed through a sense resistor, and the fed into the current limit pin
of the PWM IC. If the voltage on this pin reaches a certain value the switch
turn on pulse is turned off until the next control cycle. Therefore the current
limiting is carried out on a switching interval basis. If the voltage goes higher
and reaches a second limit, then the controller stops switching and restarts in
soft start mode. The power supply can then oscillate in this mode until the
short or the fault is rectified.
Current limiting is actually a little more complicated than has been made
out so far. Consider the situation when one has a converter with a transformer
and multiple output windings. If the current sensing is set up on the primary,
then the current limit has to be set for the current pulled under full load from
all the windings. However, if all the secondaries, except one, are unloaded, then
if there is a short on this winding the full current of the inverter can go through
this winding before there is a trip. This situation could result in the destruction
of this winding, or destruction of the rectifier components on this winding.
There is no easy way out of this problem. Probably the most economical
solution is to sense the current limit of each winding individually, and then take
the output of these limit circuits and “OR” them together. This forms the trip
signal to the PWM chip.
Figure 6.23 shows a conceptual diagram of a SMPS system from a control per-
spective (as opposed to an implementation perspective). The compensating
amplifier is shown with generic feedback components Z1 and Z2 . These com-
ponents can contain reactive circuit elements, which allow a variety of different
transfer functions to be set up in the feedback loop.
Compensating amplifier
Zf
Vd
Zi
- vc d Power stage vo
PWM
and output
+ Controller
filter
Vo,ref
Figure 6.23: Conceptual diagram of a control system for a switch mode power
supply.
6.3 Introduction to Control Techniques for Switching Power Supplies 213
v~ (s )
T1 (s ) = ~c
vc (s )
~
d (s ) v~ (s )
Tm (s ) = ~ Tp (s ) = ~c
vc (s ) d (s )
v~o,ref (s )+ ~
v~err (s ) Compensating v~c (s ) PWM d (s ) Power stage v~o (s )
S error and output
- amplifier controller
filter
Whilst switching power supplies seem to be very simple circuits, their oper-
ation from a control viewpoint is more complex than one might initially expect.
Consider, for example, the flyback and boost converter. Because these two con-
verters store energy in the magnetic field of an inductor before transferring it to
the load they exhibit an effect caused by having a right half plane zero in their
transfer function. Such systems are known as non-minimum phase systems. For
the non-control literate reader, a right half plane pole corresponds to a response
that tends to go in the wrong direction to correct a disturbance. non-minimum
Consider the following example of a right half plane zero effect. If we have a phase
flyback converter, and there is a sudden decrease in the output voltage due to
an increased output load on the converter. The natural reaction of the control
system is to increase the duty cycle, D, so that more energy is transferred to
the load to restore the voltage. However, due to the above-mentioned energy
storage operation principle of this converter, the initial increase in the duty
cycle can result in a further decrease in the output voltage. This is due to the
fact that increasing D instantaneously delays the next delivery of energy from
the magnetic field to the load, as compared to what would have happened if
there had been no change in D. One can see that if the feedback is very high
bandwidth then this will result in a further increase in D, and the process will
repeat. We effectively have positive feedback. Of course the process will stop
when we get to the limit of the duty cycle (this is a non-linear effect that is not
accounted for in our linear explanation). The presence of a right half plane zero
214 Switch Mode Power Supplies
H (s )
G(s )
vo,ref + vo,err Voltage loop vc Power stages and vo
S feedback
Comparator
and latch output filters
compensator iL
-
iL
vo
Figure 6.25: Block diagram of a nested loop control system for a switch mode
power supply.
iL vc
Di L / 2
IL
Di L / 2
t
t on
t off
Switch
turns Switch Switch
on turns turns
off on
to handle this. If the controller is not specially designed, the controller will
respond to driving the inductor current to zero, and it will then stay there.
There is also a problem of very high switching frequencies at low current values,
this corresponding to a very small hysteresis band.
Constant “off” time control controls the peak current in the inductor. In this
strategy the control voltage specifies the maximum or peak current. When this
peak current is reached the switch is opened for a fixed period of time. It is then
closed again and the process repeats. This situation is depicted in Figure 6.27.
This control strategy also suffers from the problem that the switching frequency
constant “off ” time is dependent on the load and the converter parameters.
control The constant-frequency with turn-on at clock time control is the control
constant frequency strategy most commonly used. This is due to the fact that the switching fre-
with turn-on clock quency is user definable in the strategy. One is effectively trading off the ripple
time control control achievable with tolerance band control for the constant switching fre-
quency. This allows one to control more accurately the losses in the switching
devices, and makes the design of the output filter much simpler. Figure 6.28
shows the waveforms that occur with this control. The switch is closed at a
time determined by a clock signal. The switch remains on until the current
limit is reached, and then it turns off until the beginning of the next control
period. The process then repeats. The fact that the switch only turns on at the
beginning of a clock pulse means that the frequency is fixed by the clock period
(which of course is user definable).
There is a problem with straight current mode control that we have not
mentioned in the discussion thus-far. If the converter duty cycle exceeds 50%
the converter output will possibly oscillate at a subharmonic of the switching
subharmonics frequency – specifically at half the switching frequency. This occurs because
the current control loop works by turning off a switch when the current reaches
a particular value. It is possible if the duty cycle is larger than 50% that the
current will not return to the value at the beginning of the control interval.
6.3 Introduction to Control Techniques for Switching Power Supplies 217
vc
iL
I$L
t
t on t on
Switch
t off t off
turns Switch
on turns
off
Switch
turns Constant t off
on
Therefore in the next control interval the current will reach the desired value
sooner (since it is starting off with an offset). Therefore the switch will turn off
sooner than it otherwise would, and consequently the “off” time will be longer.
Therefore at the end of this interval the current may be lower than the desired
value. This would result in the control deciding to turn the switch on longer,
since we are now starting from a negative offset compared with the correct
value if this phenomena were not occurring. One can see that the period of the
oscillation caused by this jitter in the duty cycle results in a frequency that is
half the switching frequency.
In addition to the subharmonic oscillation problem, one also has a form of
open loop instability with current mode control [14]. The following discussion open loop instability
is with reference to Figures 6.29(a), (b) and (c). Consider Figure 6.29(a) shows
the effect of a perturbation of the inductor current (dashed line) away from the
nominal current (the solid line). Notice that the perturbation dies away in this
case. The effective duty cycle changes due to the way that current mode control
works.
Figure 6.29(b) shows a similar situation, but in this case the duty cycle is
larger than 0.5. One can see that instead of the error between the nominal
inductor current and the perturbed version getting less, it actually increases
with each successive control interval. Therefore, there is effectively positive
feedback in this case.
vc
iL
I$L
t
t on t on
t off t off
Ts Ts
Clock Clock Clock
Constant period
between clock
pulses
Figure 6.28: Waveforms for constant frequency with turn-on at clock time con-
trol.
6.3 Introduction to Control Techniques for Switching Power Supplies 219
iL
Ve
m2
m1
Di 0
Di L
t
(a) Duty cycle < 0.5
D
Ve
m2
m1
Di 0 Di L
t
D (b) Duty cycle > 0.5
Compensated voltage
reference
Ve
-m
m2
m1
Di 0
t
D (c) Duty cycle > 0.5, slope compensation
Figure 6.29: Open loop instability of current mode control. (a) stability with
duty cycle < 0.5; (b) instability with duty cycle > 0.5; (c) stability with duty
cycle > 0.5 and slope compensation.
220 Switch Mode Power Supplies
form, or alternatively subtracting a sawtooth from the voltage error signal fed
to the current mode controller comparator.
Figure 6.29 shows the effect of slope compensation. In this case the sawtooth
waveform is subtracted from the error voltage, Ve coming from the voltage error
amplifier. This effectively forms a new reference for the current control section of
the loop. In this case, even though the duty cycle is larger than 0.5 the perturbed
current returns to the nominal current (as was the case for D < 0.5). The
added ramp has a constant value, and therefore the sensitivity of the feedback
to variations in the current measurement becomes less. To understand how this
works one can look at the extreme case when the current in the load is very low
and the ramp is added to the current measurement. In this situation the control
voltage from the error amplifier is being compared to the slope compensation
voltage, and hence the circuit is essentially operating in the normal triangular
wave comparison mode of voltage control. Therefore, the addition of the slope
compensation brings in some features of voltage control into the current mode
loop, and under the situation of low currents it effectively behaves as voltage
control (and therefore would have the dynamics of voltage control).
Let us consider this situation in a little more detail. One can see from
Figure 6.30 that the current perturbation error at the beginning of a control
interval, ∆i0 , is related to the current perturbation error at the end of the next
control interval, ∆i1 , as follows:
m2
∆i1 = −∆i0 (6.50)
m1
Remark 6.21 Equation (6.50) shows that if |m2 | > |m1 | then |∆i1 | > |∆i0 |
– i.e. the error has increased after one control interval. This situation would
continue.
This situation correlates to D > 0.5, since for the circuit to be in steady
state, i at the beginning of the interval, must be equal to the value at the end.
This implies that |m2 | > |m1 |. Therefore the two conditions are synonymous.
m2
m1
Di 0
Di1
Di 0 -Di1
x= x=
m1 m2
Figure 6.30: Geometrical relationship of the current waveform slopes when there
is a current perturbation.
Remark 6.22 Equation 6.54 shows that the slope of the ramp that must be
added to the current or subtracted from the voltage error must be greater than
half the magnitude of the down slope of the inductor current.
1T 2T 3T 4T 5T
Ve
-m = m 2
Dio m2
m1
Introduction to Practical
Design of Switch Mode
Power Supplies
7.1 Introduction
In this chapter we shall briefly look at the most important aspects of the physical
component design of a switch mode power supply (SMPS). The approach taken
is a very practical one, with some theory where appropriate.
The design of a switch mode power supply, like most electronics design, is
complicated because of the large number of design trade-offs that are available.
This fact means that this presentation is far from exhaustive, nevertheless the
salient issues in making design choices will be emphasised. The design of SMPSs
is complicated even further by the fact that virtually all SMPS’s use magnetics
in their design. Consequently much of this chapter will be concerned with the
design of these magnetics.
The first section of this chapter will consider issues related to the selection
of the electronic components of a SMPS. The second section of the chapter will
look in some detail at the design of SMPS magnetics. Much of the material in
this chapter is closely based on [13].
7.2.1 Resistors
The resistor is probably the most ubiquitous of all electronic components. Con-
sequently most electronic designers don’t pay a lot of attention to details other
than its value and power rating.
7.2.1.1 Values
There is a practical maximum value for a resistor that is used on a PCB. This
practical limit occurs for several reasons:
• Large resistor values are not commonly available (although they can be
obtained for specialised applications).
• If a very large value of resistor is used, then the resistance across the PCB
between the resistor legs may be comparable or less than the resistor value.
Therefore the resistor is ineffective.
• Using large resistor values makes the circuit very susceptible to electri-
cal noise. A large value of resistance means that very small capacitively
coupled currents can result in large coupled voltages.
Remark 7.1 Don’t use large values of resistance in your designs if at all possi-
ble. Even values of 220kΩ can cause significant noise pickup problems, especially
in switching applications which are inherently noisy in any case.
resistance wire wound resistors are called Rheostats. These are most commonly
shunt used in laboratories for experiments, rather than in commercial products.
Another common type of resistor used for current sensing applications is the
current shunt. This resistor type usually has a very low, but precisely known
value. One can detect the voltage across the resistor, and then use Ohm’s Law
to deduce the current through the shunt. The shunt itself is made of metals
that have a very low temperature coefficient. A low cost shunt can be created
using a PCB track itself. This should only be considered where cost is the
primary consideration, since the accuracy of such a shunt is not very good. It
should be noted that shunts provide a non-isolated measurement of current.
In many applications this is all right, but in other applications where isolation
is important then additional measures must be used to gain isolation of the
measurement. Table 7.1 summarises these comments.
7.2.1.3 Tolerance
One important attribute of a resistor is its accuracy. Many years ago the “garden
variety” resistor had a tolerance of 5%, and the exotic resistors had a tolerance
of 1%. These days the default tolerance of resistors is 1%, and at slightly higher
price one can have resistors with 0.1% tolerance.
to 100s of volts, and at the top end of this range resistor voltage rating can be
important.
Most modern metal film resistors have a very small temperature coefficient of
the order of 50–250ppm/◦ C. Wire wound resistors however, depending on the
material they are made from, can exhibit substantial changes of resistance with
temperature. This is especially a problem with these resistors, since by defini-
tion they will undergo large temperature changes. Shunt resistors, as mentioned
in Section 7.2.1.2, are purpose designed to exhibit very low temperature coeffi-
cients. They also usually have a very low value so that power dissipation is low
in the resistor, and hence temperature rise is kept to a minimum.
All resistors have a maximum power rating. However, a resistor should not be
operated at its maximum power rating, since it is severely stressing the compo-
half power opera- nent. This severe stress usually results in a high failure rate of components.
tion In order to ensure high reliability of resistors it is recommended that a re-
sistor, at worst, is operated at half its nameplate power rating. It is probably
better to be even more conservative than this and operate the resistor at ap-
proximately 1/3rd of its power rating.
Practical Issue 7.1 Select resistor power ratings so that they are operating at
approximately 1/3rd of the device specified power rating.
pulsed power
The above comments are implicitly for continuous power dissipation. How-
ever, one can modify them in relation to pulses of power, especially for wire
wound resistors. Manufacturers of these resistances will sometimes give a table
of pulsed powers for pulses of less than 100msec.
Practical Issue 7.2 Power ratings for non-wire wound resistors should be strictly
adhered to. It is alright to have power pulses up to the maximum rating of the
resistor for short durations (say less than 100msec) providing the repetition rate
is not too high.
Rheostat
A Rheostat is a variable power resistor, as opposed to a Potentiometer which
is a variable signal level resistor. Rheostats usually consist of a wire wound
resistor that has a sliding contact. The power rating for the device is for the
whole resistor. Therefore if the sliding contact is halfway along the resistor,
so that only half the resistor is being used, then the power rating is half the
nameplate value (so that the maximum temperature of each of the wire turns
is the same as for the full resistor). One must be particularly careful with using
these resistors on a voltage source, as it is easy to move the slide around so that
the maximum power rating of the active section of the Rheostat will be exceeded.
One can put a current meter in the circuit to make sure that the current rating
of the device is not exceeded as adjustments are made, or alternatively another
resistor can be put in series with the Rheostat to prevent overload.
7.2 Component Selection 227
7.2.1.8 Shunts
Whilst a shunt is a resistor, it is not used for the normal application of the
resistor, which is to somehow limit current flow. With a shunt one wishes to
impede the current flow as little as possible.
A shunt is generally constructed of a near zero coefficient metal such as
manganin, attached to heavy duty terminal blocks made of brass. Shunts come
in a variety of sizes, ranging from very low current shunts, up to shunts that
can handle thousands of amps. Typically a shunt is designed to produce either
50mV or 100mV at its rated current. Shunts are generally used if one wishes to
measure low frequency or DC currents. In AC applications, current transformers
are often used instead since they offer isolation.
Remark 7.2 It should be noted that the use of shunts in high power Power
Electronic applications is not very common these days. For example, it is not
common for shunts to be used to measure the currents in inverter systems. In-
stead Hall Effect transducers are used, since they have good frequency response
and offer isolation.
Consider a 100A shunt with a 100mV output. This means that the resistance
of the shunt is 100mV / 100A = 1mΩ. In addition to the resistance of the shunt
there is a parasitic inductance. For a 1in shunt, this inductance is of the order
of 10–20nH. If we assume 20nH, then we have an AC model for the shunt as
shown in Figure 7.1. Obviously the impedance of this circuit is Rshunt +jωLshunt
which is frequency dependent. Clearly there is a zero in the impedance frequency
response, and hence above a certain frequency the voltage across the shunt will
increase due to the effect of the inductance.
Rshunt Lshunt
Remark 7.3 One way to raise the frequency at which the impedance zero occurs
with the shunt is to raise the resistance of the shunt. However, in high current
applications this is not feasible.
An alternative strategy is to lower the inductance of the shunt by making it
from stacked layers of metal, instead of a single piece. There are practical limits
on how far this can be taken.
Lshunt
Ccomp Rshunt = (7.3)
Rshunt
20nH
Ccomp = = 20, 000µF (7.5)
(1mΩ)2
7.2.2 Capacitors
Just as there are different types of resistors, there are different types of capaci-
tors. In any design it is usually not possible to use just one type of capacitor –
the correct capacitor technology must be used for the application.
7.2 Component Selection 229
Electrolytic This is one of the most common types of capacitors used for
large capacitance. There are a variety of choices available, with the most
common being the aluminium electrolytics. These capacitors can have
very large values – well into the millifarad range, and many hundreds
of volts. Note that these capacitors are physically very large. There
are also tantalum electrolytic capacitors, which are available in solid and
wet varieties. These capacitors tend to have maximum sizes that are
smaller than those attainable in the aluminium electrolytic variety, but
they have better high frequency performance. A distinguishing feature of
all electrolytic capacitors is that they have a polarity.
Ceramic These are the flat, disc like capacitors that home hobbyists would
be familar with. They are used for timing and bypass purposes. They
are available in values from a few picofarads to 1µF. New in this range
of capacitors are the multilayer ceramic (MLC) variety, which have very
low effective series resistance and larger maximum values (several hundred
microfarads) as compared to the older ceramics.
Plastic These capacitors can withstand very high dv/dt across them, particu-
larly the polypropylene variety. They are used in circuits such as quasi-
resonant SMPSs. Another variety, Polystyrene, are more specialised, and
are used where very low leakage is required, such as in sample-hold appli-
cations.
Aluminium Electrolytic Used when large capacitance needed. Low frequencies. Bulky.
Tantalum Electrolytic Use for moderate capacitances. Medium frequencies. Less bulk.
Ceramic Timing and bypass applications.
Multilayer ceramic High frequency bypass, low leakage applications.
Plastic Use for high dv/dt applications. Low leakage current applications.
important quantity. Therefore, one can adjust the resistor to get the desired
result.
Practical Issue 7.4 Just as large resistor values should be avoided, one should
also avoid the use of capacitor values less than approximately 22pF. The reason
for this is that capacitance exists between any parallel plates, and consequently
parasitic capacitances on a PCB can swamp out the designed low values of ca-
pacitance.
7.2.2.3 Tolerance
The tolerances on capacitors are usualy very poor – typically ±20%. Electrolytic
capacitors can have even worse tolerances than this. The other variable to
consider is the temperature range that the capacitor will operate over. The
capacitance value can vary substantially with temperature, e.g. some types of
capacitors can loose 80% of their capacitance at -40◦ C.
Remark 7.4 The ESR resistive can have a very important effect on the voltage
ripple from a capacitor. For example, if one is pulling 1 Amp of ripple current at
100kHz from a capacitor, and the ESR is 100mΩ, then there is 100mV of ripple
introduced by the voltage drop across this internal resistance. Therefore, if one
requires 50mV of ripple maximum, then one would need at least two capacitors
in parallel, and we have not even taken into account the amount of capacitance
required to supply the charge to the load. The situation in relation to the ESR
could be even worse if the capacitor has to operate over a wide temperature
range.
7.2.2.5 Aging
Aging of capacitors, especially in relation to electrolytics, can be very impor-
tant. Electrolytic capacitors may have a life time figure associated with a certain
temperature of operation. Values could be 1000 hours, 2000 hours, or even bet-
ter 5000 hours. When a capacitor approaches its design age the capacitance
decreases, and the capacitor will be out of specification. In the worst circum-
stances the capacitor may fail.
Fortunately, for every 10◦ C drop in temperature, a capacitors life doubles.
For example, is a capacitor is rated at 2000 hours at 85◦ C, then if it is operated
at an average temperature of 25◦ C, then it will last 2000 × 26 = 128, 000 hours,
or 16 years.
7.2 Component Selection 231
Remark 7.5 The use of the average temperature the capacitor is subjected in
the above calculation is important.
Remark 7.6 Depending on the application the ripple current or the dv/dt rat-
ing may be important. Ripple current tends to be the appropriate measure when
the capacitor is being used in an application where the voltage across the capaci-
tor is relatively constant. dv/dt is relevant with the voltage across the capacitor
undergoes large and rapid transients.
7.2.3 Diodes
There are two main types of diodes used in SMPS circuits – normal restifier
diodes, and Schottky diodes. We shall see in Section 8.2.1 that there are special
PN junction diodes required for very high powered applications, but we shall
not be considering these here.
advantage if the Schottky diode, as compared to the PN diode, is that the for-
ward voltage drop is much lower – approximately 0.2V for the Schottky, and
0.6V for the PN diode.
There are a few caveats associated with Schottky diodes – they can only
operate at fairly low voltages, up to about 100V; the higher voltage Schottky
diodes tend to have a forward voltage that is approaching a PN diode; the
internal space charge capacitance of a high voltage Schottky diode can be high,
thus resulting in reverse current when the capacitance is charging as the diode
is reverse biased.
7.2.3.2 PN diodes
These are the conventional diodes. They are available in many different types,
from “slow” rectifer diodes, to ultrafast signal diodes. The latter are more akin
to the diodes used in SMPS circuits. The ultrafast refers to the reverse recovery
characteristics of the diode. The fast diodes have the ability to get the stored
minority charge out of the diode very rapidly when the device is reverse biased.
Whilst the stored charge is disappearing the diode is able to conduct current in
reverse recovery the reverse direction. This phenomenon is known as reverse recovery.
v v
+ - - +
i i
Reverse recovery can have a variety of effects from poor converter efficiency,
7.2 Component Selection 233
Forward current
Reverse recovery
current
Figure 7.4: Reverse recovery in a boost converter circuit.
MOSFET. Even with these devices a Schottky diode is placed in parallel with
the MOSFET to take the instantaneous currents that need a path when the
MOSFET is not on during the forward bias period. The body of a MOSFET
has a parasitic diode around the device, but this diode is very slow. A Schottky
diode in parallel with the device prevents the internal diode from being used.
Remark 7.8 Ultrafast diodes themselves generate a lot of EMI. This occurs
because an ultrafast diode still has reverse recovery current, the ultrafast bit
being that it only last for a short period of time. However, as the diode rapidly
decreases the reverse current, it generates a very rapid rate of change of current,
and consequent EMI.
device is connected to the positive supply rail of a system, then the device can
be turned on by simply connecting the gate to ground.
Remark 7.9 One could consider the p-channel MOSFET to be a device that
turns on with an active low signal, whereas the n-channel device requires an
active high signal.
Remark 7.10 The n-channel device is more commonly used because the resis-
tance of these devices is less for the same size die. Consequently the cost for a
given current rating is less.
poorly known parameter, and if convergence does not occur then one is probably dissipating
too much power.
236 Introduction to Practical Design of Switch Mode Power Supplies
unit time, then the more average power will be dissipated in the device.
In order to roughly calculate the losses due to switching one can assume
that as the device turns off or on that the voltage rises or falls as a linear
function of time. Whilst this is happening the current through the device
is more or less constant. Therefore the expression for the power dissipa-
tion for one on-off event would be the average voltage times the current –
i.e. P = Ipk Vpk ts /2, where ts is the time for the on-off switching event.
Therefore the total power dissipated over a one second interval (i.e. the to-
tal energy dissipated in the device per second) is the energy dissipated per
switching event multiplied by the number of switching events per second
– i.e. P = Ipk Vpk ts fs /2
Remark 7.11 By calculating the conduction and switching losses, and using
the thermal resistance of the MOSFET package one can come up with an esti-
mate of the temperature rise of the device. This estimate is a good measure of
whether the device is going to run hot or cool.
You should always put a resistor in series with the gate of a MOSFET. This is
required because the gate capacitance in series with the gate lead inductance
forms a high Q series LC resonant circuit. These circuits can oscillate at fre-
quencies in the 100s of MHz range. They result in excessive heating of the
MOSFET and the emission of copious EMI radiation from the circuit. The
inclusion of the gate resistor provides the necessary damping to lower the Q of
the resonant circuit so that any oscillations are damped out quickly.
Practical Issue 7.6 If you have two MOSFETs in parallel you should put an
individual resistor in series with each of the gates. If a single resistor is shared
between two gates then oscillations can occur between the two MOSFET gates.
Some designers decide to make the gate-source voltage very high in order to get
the gate voltage past the threshold voltage of the MOSFET in the minimum
time. If the gate-source voltage exceeds approximately 20 volt, then the MOS-
FET is likely to be damaged. To turn a device on the most important thing is
to have a very low impedance gate drive so that the current can be sourced to
charge up the gate capacitance.
7.2.6.1 Offsets
There are two main types of offsets in Op Amps:
2. Input Offset Current. The input impedance of a real Op Amp is not infin-
ity. Therefore current will flow into the terminals. Due to manufacturing
tolerances, the current in the + and − terminals can be different. The
input offset current is very small in absolute terms – usually of the order
of nAmp.
Considering the small values for the offset voltage and current one migh be
tempted to say; “What is the problem?”. The problem with the offsets is due
to the fact that an Op Amp has a very high open loop gain, which is usually
greater than 106 . Therefore, if one has, say a 2mV offset voltage at the input,
then the output would be 2 × 10−3 × 106 = 2 × 103 . Most Op Amps operate
on a power supply of 12 to 15 volt. Therefore the offset voltage would result in
the output of the Op Amp being saturated to the supply rail.
The immediate retort to the above paragraph is that Op Amps are never
operated in open loop, but have feedback around them that lowers the effect
gain. However, even with feedback, the gain can still be quite high, resulting in
significant output offset voltage. Similar arguments can be mounted with offset
current when there are resistances in series with the inputs.
+
LM2902
-
100k
9.09k 10k
2mV between the + and − terminals. The gain of the amplifier is 10 in this
case, making the output with a zero input voltage equal to ±2mV ×10 = ±0.02
volt. In many applications this may not be a problem. However, if the gain was
1000 then the output offset would be 2 volt, which is clearly unacceptable.
Remark 7.12 Note that the output offset due to input offset voltage is not a
direct function of the resistors used, but is related to the gain of the amplifier.
7.2.6.1.2 Input Offset Current The following discussion is also with re-
spect to Figure 7.5. In this case we shall assume that the offset voltage is zero.
Because the inputs to a real Op Amp take slightly different currents, then the
voltage at each of the input pins can be slightly different due to the differeing
voltage drops across the resistors. For example, in the case of the LM2902, the
difference between the input currents can be as much as 5nA. Therefore the volt-
age difference between the two terminals can be 9.09 × 103 × 5 × 10−9 = 45µV.
This voltage, in turn, is amplified by the gain of the amplifier to give 450µV
output voltage. As with the offset voltage case, in many applications this is not
serious, but if the gain is high, or very high precision is required, then the effect
of the input current offset may cause significant output voltage offset.
Remark 7.13 The effects of input current offset occur simultaneously with in-
put voltage offset, therefore the output offsets have to be added together.
Remark 7.14 Input current offset will become more pronounced if larger resis-
tance values are used.
Remark 7.15 More expensive amplifiers are laser trimmed internally in order
to lower the input offset current.
7.2.6.1.3 Input Bias Current The input bias current is the current that
flows into the input terminals even if there is no input offset current effect.
The input bias current can cause offset problems if the resistances in the input
terminal leads are mismatched. In the case of Figure 7.5 we have been careful
to choose the resistors so that the effective resistance through which the bias
currents flow is the same. However, if there is a mismatch in the resistance
values due to resistor tolerances, or alternatively due to other external circuit
considerations, then there will be different voltage drops across the input circuit
resistors. This results in the generation of different voltages on the input pins
to the Op Amp.
As a specific example, if we assume that the resistor to ground from the
non-inverting terminal is 19.09kΩ, and the input bias current for the LM2902 is
90nA, then the difference in the resistance seen by the two bias currents is 10kΩ.
Consequently the bias current offset voltage is V = 90nA×10kΩ = 900µV. This
voltage in turn is amplified by the amplifier gain of 10, giving an output offset
of 9mV.
Remark 7.16 Clearly, one should try and get the resistance in series with the
Op Amp inputs to be the same values to eliminate the effect of bias currents on
the output.
7.2 Component Selection 239
Summary 7.1 Given the above discussion, we can develop and expression for
the output offset:
V = [Vos + Ios R + Ib ∆R]Acl (7.8)
where Vos the input offset voltage, Ios the input offset current, Ib the
input bias current, R the average value of the input resistors, ∆R the
difference between the values of the resistors, and Acl the closed loop gain of
the amplifier.
Remark 7.17 One can see from (7.8) that in order to minimise the output
offset one must:
• Keep the resistor values as small as feasible to minimise the effect of the
Ios current.
• Make sure the input resistor values are closely matched so that ∆R ≈ 0 .
• Choose an amplifier with a very small Vos . Note that a low Vos Op Amp
often has a lower gain-bandwidth product.
10MW
10kW
-
10kW
resistor could be choosen so that the feedback resistor would be less than or equal to 1MΩ.
240 Introduction to Practical Design of Switch Mode Power Supplies
R2 R4
R3
R1
vin -
vo
+
R1
Let us consider the specific example of a gain of 1000. If we assume that the
input resistance of the circuit has to be 10kΩ, then this makes R1 = 10kΩ.
Let us then choose R3 = 1kΩ, which will result in a significant voltage division
effect through the feedback network without having the other resistor values
too large. We still have two other resistor values to choose – R2 and R4 . Let
us arbitrary choose R2 = 100kΩ. The denominator of (7.9) now has a value of
10MΩ, which means that the numerator must have a value of 1010 Ω to achieve
the required 1000 gain. The only unknown now is R4 . Substituting the known
values into the numerator expression of (7.9), and equating to 1010 , one can
calculate that R4 = 98kΩ. Therefore, to summarise, the resistor values are:
R1 = 10kΩ, R2 = 100kΩ, R3 = 1kΩ, and R4 = 98kΩ. We have achieved the
required gain from the circuit without having to resort to any resistor values
greater than 100kΩ. This would reduce the noise pick of this amplifier circuit
considerably.
Remark 7.18 A similar feddback resistor arrangement can be used for in-
verting amplifiers. However, in this case one is not constrained by the input
impedance requirement, and therefore one has more freedom to choose the resis-
tors in the conventional non-inverting feedback amplifier.
7.2 Component Selection 241
Gain (dB)
Aol
Gain bandwidth
product
Acl
0 log f
fol-3db fcl-3db funity
Phase shift is related to the frequency response of the amplifier circuit shown
in Figure 7.8. It is well known from control theory that at the -3dB point
242 Introduction to Practical Design of Switch Mode Power Supplies
of a single pole frequency response the phase shift from input to output is
−45◦ . At approxmately a decade above this the phase shift has converged
to approximatley −90◦ . In an Op Amp circuit the situation is often more
complicated than this due to the effects of internal compensation within the Op
Amp itself. This can result in even more phase shift due to the introduction of
more poles in the higher frequency areas of the frequency response.
The only way to accurately determine the phase shift characteristics of an
Op Amp is to actually meaure them over the frequency range of interest. It
is not always true that amplifier with higher gain-bandwidth product will have
less phase shift.
7.2.7 Comparators
A comparator is a special type of Op Amp specialised for comparison applica-
tions. In relation to voltage and current offsets the same principles apply to the
comparator.
7.2.7.1 Hysteresis
Almost always whenever a comparator is being used it should incorporate hys-
teresis in the input. This is to prevent false triggering and potential oscillation
7.2 Component Selection 243
of the device.
Vref
-
vo
vin +
R1
R2
Figure 7.9: Comparator with hysteresis.
Vref + 0.01V
vin = (7.12)
0.99
Therefore the input voltage, vin , has to be greater than the reference approx-
imately by 0.01V (it is actually a little more than this). At this input the
comparator would switch so that the output voltage would become +V . We
can then repeat (7.12) for this case and get:
Vref − 0.01V
vin = (7.13)
0.99
As we can see the input voltage has to be less than the reference voltage, again by
approximately 0.01V for the comparator to reach the switching state. Therefore
we have implemented classic hysteresis by the process, with the hysteresis band
being approximately 0.01V around the nominal reference voltage.
244 Introduction to Practical Design of Switch Mode Power Supplies
Comparators that have a single supply rail often don’t pull the output right
down to the dround rail when the output should be zero. This can have a
dramatic effect if the device is driving a BJT or a logic gate. For example, some
comparators are only guaranteed to have a low output of approximately 0.6-0.7
V when sinking 6mA of current.
Practical Issue 7.7 If the comparator output does not pull to near zero at the
current level the output will be operating at, then the output voltage under the
low condition must be accounted for when calculating the resistors for hysteresis.
+V
+V
10kW
F = H · dl (7.14)
where boldfacing means that the quantity is a vector, and F the mmf in
Ampere-turns, H the magnetic field intensity vector in Ampere-turns/metre,
and dl an incremental path length vector. The direction of the H vector is
the same as the direction of the flux vector in a isotropic medium. The direction
of the magnetic flux density vector, B, can be determined by other techniques,
but is defined for practical purposes by the right hand rule.
Let us consider the application of (7.14) to a single strand of wire. We know
apriori that the F value in this case is I, the current being carried in the wire.
Since the H and dl vectors are coincident around a circular path of integration
(since the H vector is in the same direction as the B vector), and the total path
length is 2πr, then one can conclude that:
I
H= (7.15)
2πr
Remark 7.20 Equation (7.15) implies that the magnetic field intensity can be
defined as:
mmf F NI
H= = = (7.16)
l l l
The relationship between Ampere’s Law and the magnetic field intensity is
defined by the follwoing:
B = µr µ0 H = µH (7.17)
1
F = B · dl (7.18)
µ
B(t)
v(t) Area A
Figure 7.11: A loop of wire enclosing an area of time varying flux density.
we have a loop of wire, and orthogonal to the surface of the loop there is a time
varying flux density, B(t).3 A voltage, v(t) is generated between the ends of
the wire under this circumstance. Faraday’s Law tells us the magnitude of the
voltage under this condition:
dλ dφ dB
v(t) = =N = NA (7.19)
dt dt dt
where λ the flux linkage, φ the flux, and N the number of turns of the
coil.
7.3.1.3 Inductance
We know from Ampere’s Law that a wire produces magnetic field intensity, and
consequently magnetic flux density. The inductance of a coil is a number that
tells us something about how well the physical configuration of the coil produces
flux density. For example, if a coil has more turns on it then it would have more
inductance, if a coil has a large area then its inductance is larger, and it a coil
is wrapped around a high permeable core material then its inductance will be
higher. In all these situations, a higher inductance indicates that the coil is
better at producing flux.
The fundamental definition of inductance is:
dλ
L= (7.20)
di
3 If the magnetic flux density vector is not orthogonal to the surface area, then it is the
In the case of linear magnetic materials (i.e. the flux density varies linearly with
the current through the coil) this expression can simply be written as:
λ
L= (7.21)
I
Remark 7.21 A verbal definition of inductance is that it is the flux linkage
produced though the coil per unit current flowing through the coil.
Equation (7.21) can be used to develop the expression for the inductance in
terms of the physical parameters of a coil. From (7.21) one can write:
Nφ N AB
L= = (7.22)
I I
NI
Since B = µH = µ
l
µN 2 A
∴L= (7.23)
l
where l the length of the magnetic path.
Remark 7.23 One can see from (7.23) that the inductance is defined entirely
in terms of the physical characteristics of the coil. Note that the inductance is
related to the square of the coil turns.
Remark 7.24 In the case of a high permeability material as the coil the length
of the magnetic path is easy to determine in (7.23).
One can develop Faraday’s Law in terms of inductance using the flux form
of Faraday’s Law and (7.22). From (7.22) one can write:
N AB = Li (7.24)
where the lower case i indicates that the current is changing. Substituting this
into (7.19) one can easily see that:
dLi di
v= = L for L constant (7.25)
dt dt
which is the familiar voltage relationship from circuits.
Remark 7.25 Note that the L constant is not correct when the core material
in a ferro-magnetic material which saturates.
In magnetic circuits three terms beginning with the letter R are often used –
Reactance, Remanence and Reluctance. We shall briefly review these (most
electrical engineering students should already know what they are).
Bm
Br
F = Rφ (7.31)
Remark 7.28 Notice that the reluctance defined in (7.30) obeys the same in-
tuition as resistance of wires. For example, if one doubles the cross-section of
the core (i.e. doubling A) then the reluctance drops, just as resistance would if
a wire diameter is doubled. Similarly, if the length of the core is increased then
the reluctance increases. A similar effect also occurs with resistance.
N1 turns N 2 turns
Core
Figure 7.13: Circuit symbol for a transformer.
The dots on the ends of the coils indicate the way that the wire is wound on
the core. If current is injected into the lead at the dotted end of the primary
winding, then the flux produced in the core will have the same direction as
that produced by the secondary winding if current is injected into its dotted
terminal. From a voltage viewpoint, if a positive voltage appears on the dot-
ted terminal of one of the windings, then a positive voltage will appear on the
dotted terminal of the other winding.
An ideal transformer is a transformer that has a core material of infinite
permeability. This means that no mmf is required to set up a flux in the core,
since the reluctance of the core is zero (regardless of its length or area). The
infinite permeability has the implications that there will be no leakage flux in
the transformer – i.e. all the flux produced by the primary winding will link to
the secondary winding.
We can calculate some of the basic properties of ideal transformers by apply-
ing Faraday’s Law using the properties mentioned in the previous paragraphs.
Consider the voltage on the primary side of the transformer:
dB1
v1 = N1 A1 (7.32)
dt
Similarly for the secondary we can write:
dB2
v2 = N2 A2 (7.33)
dt
Since both windings are wound on the same transformer core, then A1 = A2 .
Furthermore, since there is no leakage of flux density from the primary to the
secondary (and vice-versa), then B1 = B2 . Consequently we can write:
dB1 dB2 v1 v2
= = = (7.34)
dt dt N1 N2
Remark 7.29 Notice that the implication of (7.34) is that the volts/turn of the
transformer are constant for both the primary and the secondary.
7.3 Introduction to Magnetics Design 251
Since the ideal transformer requires not mmf to establish flux in the core,
we can write:
N1 i1 + N2 i2 = 0 (7.35)
which implies:
i1 i2
=− (7.36)
N2 N1
Remark 7.30 Equation (7.36) could also be deduced using conservation of en-
ergy together with (7.34):
v1 i1 + v2 i2 = 0 (7.37)
Using (7.34) one can write:
N1
v2 i1 + v2 i2 = 0
N2
N1
∴ i1 = −i2
N2
i1 i2
or =− (7.38)
N2 N1
Remark 7.31 The negative sign in (7.38) indicates that the secondary current
direction is opposite to the primary current direction.
Remark 7.32 The implications of (7.34) and (7.38) are that if the voltage is
stepped up between the primary and the secondary then the current steps down
(and vice-versa).
Ideal transformer
Magnetising
inductance
Lm
Ll
Leakage inductance
This flux will be in such a direction in the core that it will tend to cancel
the magnetising flux. However, the flux in the primary is fixed by the applied
voltage and its frequency (via Faraday’s Law), therefore this cancellation of flux
will result in more current being drawn from the primary circuit to compensate
for the cancelled flux. This is effectively the load current on the secondary being
reflected back into the primary circuit. These arguments lead to the diagram of
Figure 7.14. Notice that the magnetising inductance effectively shunts current
away from the ideal transformer. Therefore the magnetising current is “wasted”
in the sense that it does not contribute to the output current.4 Similarly, the
leakage inductance will support voltage across it, and this voltage does not
appear across the primary of the ideal transformer, and will therefore not be
transformed to the secondary.
7.3.3.2 Saturation
Saturation is a phenonmena in ferro-magnetic cores which causes the perme-
ability of the core to change from the normal high value to a value near the
permeability of air as the flux density in the core increases. Another way of
stating this is that when the core saturates an increase in the current in the
winding around the core results in only a very slight increase in the flux density
in the core.
Saturation is usually a phenonmena that one is wishing to avoid, since the
incremental inductance of the core decreases dramatically as the core saturates.
4 The magnetising current is usually large so that the magnetising current is only a few
Material Consideration
If the core inductance is restricting current flow in the circuit, then this decrease
in inductance could result in a catastrophic increase in the current.
There are two types of saturation associated with cores – hard saturation,
and soft saturation. Hard saturation refers to a rapid saturation – i.e. a small
increase in the flux density results in a very rapid change in the permeability.
Ferrites and steel laminations fall into this category. Soft saturation is where
there is not a clearly defined saturation flux density, but instead the permeability
changes gradually with increased flux density. MPP cores display this saturation
characteristic.
Remark 7.33 A core is said to be saturated if the current flow in the winding
of the core has reduced its permeability to 20% of its permeability at very low
currents.
ph = kh ω B̂ n (7.40)
Remark 7.34 Notice from (7.39) that the Eddy current loss is dependent in a
squared sense on the applied frequency, whereas hysteresis loss in only linearly
dependent on the frequency. Theefore it is very important to have a high resis-
tivity for the core material in high frequency applications. The bonded type core
materials such as ferrite, MPP, and iron powder to designed to achieve this.
7.3 Introduction to Magnetics Design 255
V
B̂ = (7.41)
N Aω
where V the amplitude of the sinusoidal voltage source, and ω its frequency.
N and A are the turns of the coil and area of the core respectively.
Remark 7.35 One can immediately see from (7.41) that if B̂ is to be made
smaller, then N or A must be made bigger.
Consider the situation where the power loss in the core of our magnetic
structure is less than the total copper losses. Based on (7.39) and (7.40) we can
see that we must increase the peak flux density experienced by the core, given
that the excitation frequency is fixed, and the core dimensions are fixed. From
Remark 7.35 one can deduce that this means that the number of turns wound
onto the core must be decreased. This will result in a lower inductance for the
core, and hence for a fixed supply voltage, a larger peak current. Therefore,
even though the wire resistance would have dropped, the higher rms current
into the core will result in higher copper losses.
Remark 7.36 The core losses equal to copper losses equality for minimum
overall losses applies equally well to electrical machines as to inductors and
transformers.
Remark 7.37 Core losses equal to copper losses equality for minimum losses is
analogous to the maximum power transfer theorem in circuit theory. You may
recall that this theorem says that the load resistance should be equal to the source
resistance for the maximum power to be transferred to the load from the source.
Therefore, in this case one has the same losses in the source resistance and the
load resistance.5
Assuming that one has a transformer type of structure, consider the following
scenario. The power loss in the magnetics is less than that in the copper.
Therefore, we wish to increase the power loss in the core and reduce the losses
in the copper. The power losses in the core can be increased if the number of
turns on the primary winding are decreased. This can be seen if we assume that
5 In the case of maximum power transfer one is trying to maximise the power. In electri-
v(t) = V sin ωt
1
∴ B(t) = v sin ωt dt (from Faraday’s Law)
NA
V
= cos ωt
N Aω
V
⇒ B̂ = (7.42)
N Aω
which is the same as the expression mentioned in (7.41).
Remark 7.38 Equation (7.42) shows that the peak flux density in the core is
increased if the number of turns in the coil are lowered.
If the number of turns in the primary coil are lowered, then the length of the
copper wire is lowered, and hence the wire resistance. If the turns in the primary
is lowered, then the turns of the secondary are lowered to maintain the same
turns ratio. If we maintain the same amount of copper under this condition, then
we can increase the diameter of the wire, this again decreasing the resistance of
the primary and secondary windings. These two effects mean that the overall
losses of the secondary will be reduced, since maintaining the same turns ratio
meaning that the secondary current would not change.6 One can mount a
similar argument if the losses in the core are larger than the copper losses. In
this case the turns on the primary are increased.
To help keep the primary and secondary winding losses approximately the
same one should allocate similar area to the primary and secondary windings.
If the secondary has more turns, it must have proportionately smaller wire.
If there are multiple secondaries, allocate their winding area by output power
(higher getting more winding area).
If one is designing an inductor, then the magnetic losses can be traded off
against the copper losses by adjusting the cross-section of the core. For example,
if the magnetic losses are low, then they can be increased by decreasing the core
cross-section and therefore increasing the flux density. The total losses in the
core are related to the losses per unit volume, and of course the volume of
the core. If the cross-sectional area is decreased then the core volume drops
in proportion to the decrease. The flux density increases in proportion to the
decreased area. However, the total losses will increase since the losses per unit
volume are related to the peak flux density squared.
Example 7.1 Assume that the core cross-section of the typical transformer core
has been halved. This will mean that the volume of the core has been halved. The
result of the area increase, assuming that the mmf is the same and the core is
not saturated, is that the peak flux density will double. The Eddy current losses
per unit volume in the core are proportional to B̂ 2 , therefore the losses per unit
volume increase by 4. The total losses would therefore by 1/2 × 4 = 2 times
those before the change in core area.
6 Note that in this discussion we are assuming that the losses in the primary due to the
magnetising current can be neglected. The losses due to this component of the current actually
increase with the reduction in the number of turns of the primary.
7.3 Introduction to Magnetics Design 257
Parameter Specification
Inductance 35µH
DC current 2 Amp
Max power dissipation 300mW
Operation frequency 250kHz
Average voltage 10V
From Table 7.4 we need to calculate a few other values that will aid in the
selection of a core material. We know from the maximum power dissipation
specification that:
Remark 7.41 The implication of (7.44) is that the permeability of the mag-
netic material should be fairly low to prevent the magnetic system from saturat-
ing. The other alternative is that a high permeability core be used with an air
gap.
Figure 7.16: Initial permeability with respect to frequency for 2P iron powder
Ferroxcube material (from [3]).
7.3 Introduction to Magnetics Design 259
3C range of cores – these cores have much higher initial µi compared to the
2P range. Since the inductance that we desire is not very high then we can
afford to use a low permeability material. Another advantage of this is that one
would not have to consider introducing a air gap to prevent core saturation.
Figure 7.16 shows the initial permeability for a selection of different 2P iron
powder materials with respect to frequency of operation. Notice that the relative
permeability of the 2P90 material ia approximately 90 over the frequency range
of interest. Another important, and related figure, is Figure 7.17, which shows
the incremental permeability of the material versus magnetic field strength. The
incremental permeability is the permeability of the material for small variations
of the magnetic field strength on a DC bias field. This is precisely the situation
that occurs in a filter inductor of the type we are designing.
Given that we have decide to use a 2P type material from Ferroxcube, we
firstly have to make an estimate of the number of turns required to obtain the
desired inductance. An important parameter supplied by the core manufacturers
is the AL value. This value is the inductance per turn for a particular core.
Therefore, if we assume the initial value of permeability then we can come up
with a first estimate of the number of turns required.
Another important value that we have not considered as yet is the size of the
core we are to use – for any given material there are a number of different core
sizes. Factors that influence the core size are the wire diameter and number of
turns required,7 and the maximum flux density that is allowed in the core.
7 The combination of the wire size influence the core size to the extent that the core must
A few notes on key parameters that appear in the data sheets and selection
guides for magnetics would be opportune at this juncture. The following dis-
cussion is based on the parameters described in [3]. Note that we will not
describe all the parameters in these sheets, but will concentrate on those that
are most useful for the job at hand.
1 ∆B
µi = (7.45)
µ0 ∆H
where ∆H → 0.
where:
This expression is only valid for relatively small air gaps. For larger air gaps
fringing effects will raise the value of µe above that calculated by the above
expression.
Nφ N2 µ0 N 2
L= = = " l (7.51)
I Re 1
µe A
If the driving waveform is a square wave with a peak of V volts, then the peak
flux density is given by: peak flux with
πV square wave excita-
B̂ = (7.53)
2N ωAe tion
Similarly the peak magnetic field intensity can be worked out using the effective
length: peak magnetic field
NI intensity
Ĥ = (7.54)
le
Remark 7.42 The above calculations assume that Ae is uniform throughout the
material. However, in many magnetic structures this is not the case. Therefore
the peak flux density is calculated using the minimum cross-section area Amin .
Most cores are designed so that Ae ≈ Amin so that there is no significant increase
of flux density due to the physical core design.
7.3.5.1.6 Inductance Factor The inductance factor for a core is the in-
ductance of a single turn coil for the particular core. This is related to the
8 All the measurements are assumed to be in MKS units.
9 Note that we are using the expression N I = φRe from magnetic equivalent circuits [16].
262 Introduction to Practical Design of Switch Mode Power Supplies
magnetic properties of the core – i.e. namely the permeability. The definition
of the inductance factor can be simply obtained from (7.51):
1 µ0 µe 4π × 10−7 µe
AL = = " l = " l Henry (7.55)
Re A A
1256.7µe
AL = " l nH (7.56)
A
Now that we have reviewed some of the key parameters that are required
to understand magnetics data sheets we can now return to the design of the
inductor.
The material was previously chosen to be Ferroxcube 2P. The next step is
to choose a core type and size. We shall use a toroidal or ring core. One can see
from the table in Figure 7.18 that this is a favourable choice for this application.
Many manufacturers provide tables to aid in the selection of a particular
core. These tables not only allow a first guess at the core selection material,
7.3 Introduction to Magnetics Design 263
but also suggest a specific core. This then gives one an initial core size to base a
design on.10 This initial core selection for cores that have a DC current through
the windings is often based on a graph that uses the energy stored in the core –
i.e. 12 LI 2 . The L and I terms in this expression are both related to the size of
the core, L via the core length and area, and the current by size of the area to
put the windings in. Figure 7.19 shows the core size data and AL parameters
for Ferroxcube iron powder 2P cores. Unfortunately the Ferroxcube selection
guide does not have such a table for the iron powder cores.
We shall select an initial core from the table in Figure 7.19 and then calculate
the number of turns required. We shall use this, together with the specification
on the power dissipation to work out the amount of area required in the centre
of the core for the winding. Depending on the result of this we may have to
select another core. One other criteria for the selection of the core that was not
previously mentioned was that one would generally want the core to be as small
as possible, since this usually correlates to minimum cost.
Let us arbitrarily choose core TN17/9.8/4.4 2P90 from Figure 7.19. As can
be seen from this figure AL = 42, therefore using (7.58) one can get:
35 × 10−6
N= = 28.9 turns (7.59)
42 × 10−9
This has to be rounded up to an integer number of turns, so let’s make it 29
turns.
The next thing to consider is the amount of wire required for this. The
turns have to be wound around the toroid, so that the copper passes through
its centre. The size of the centre of the toroid places a limit on the number of
turns for any gauge of wire used. Taking into consideration the difficulties of
winding the core, as well as the amount of space taken by wire insulation, the
typical winding fill factor is 45–50% – i.e. only 45–50% of the available space
for the winding can practicably be used.
To select the wire we need to consider the amount of current that it has to
conduct, and the amount of power that will be dissipated in its resistance. The
skin effect should not be that important in this case since the high frequency AC
currents are relatively small compared to the DC current flow. A first selection
of the wire can be made from a wire table. We shall use the table printed
in [13], which is itself a reprint of a table produced by Magnetics Inc. in their
literature.11 One candidate size is AWG18 wire, which nominally has a current
capacity of 2.17 Amp. The resistance of the wire per metre is 0.02096Ω/m, and
its wire area (including insulation) is 9.83 × 10−3 cm2 , or 9.83 × 10−7 m2 .
Referring to Figure 7.19 we can work out the length that the wire has to go
around the core (approximately) as 19.5mm or 0.0195m. However, this value
doesn’t take into account the fill factor which effectively extends the length of
each turn. An approximate expression for the length of a turn for a toroidal
core is [13]:
lt = D + 2H (7.60)
where D and H are as defined in Figure 7.19. Using (7.60) the length of a turn
is 0.0181 + 2 × 0.0053 = 0.0287m.
10 Often this initial selection may prove to be inadequate in some detail. The designer may
have to choose a larger or smaller core dependent on the nature of the inadequacy.
11 The Magnetics Inc Web site, http://www.mag-inc.com, has a free program that can be
Figure 7.19: Core data for toroidal cores using powdered iron (from [3]).
7.3 Introduction to Magnetics Design 265
Using the number of turns calculated in (7.59) we can calculate the resistance
as 29×0.0287×0.02096 = 0.01744Ω. Therefore the power loss in the windings is
approximately I 2 R = 4 × 0.01744 = 70mW. This is well within the specification
of less than 300mW total power loss, and leaves 230mW for the core losses.
The other issue to examine is whether the wire can be wound on the core
– i.e. will it fit in the hole in the centre. The total wire area, including the
insulation, is 29 × 9.83 × 10−7 = 2.85 × 10−5 m2 . The total area available in the
centre of the core is πd2 /4 = 6.65 × 10−5 m2 . A fill factor is 0.5, therefore the
area available for the wire is 0.5 × 6.65 × 10−5 = 3.325 × 10−5 m2 . Therefore it
is possible to wind the wire on the core.
Remark 7.43 One must also take into account the thickness of the wire. If wire
is too thick then there will be trouble bending it around the core. In addition,
the act of bending it around the core may also fracture the core, since ferrite
and iron powder materials are very brittle.
We now need to check the core flux density. This can easily be done using
(7.51) and the Ae value from Figure 7.19 to give:
LI 35 × 10−6 × 2
B= = = 152mT (7.61)
N Ae 29 × 15.8 × 10−6
Remark 7.44 The maximum flux density is not related to the losses in this
situation, since it is primarily a constant flux density which does not cause
losses. However, there is a ripple in the voltage across the inductor, that results
in a ripple in the inductor current, and consequently an AC component sitting
on top of the DC flux density. It is this component of the flux that is relevant
to the loss calculations.
Remark 7.45 The DC flux density is important because of the effect that it
has on the permeability of the material.
Figure 7.21: Losses in 2P material with respect to flux density and frequency
(from [3]).
Pv = aB x (7.62)
where a and x are unknowns to be found. Since we have two unknowns then
we need two independent equations to find them.12
Considering Figure 7.21 we can write the following two expressions by ex-
amining the 200kHz curve:
which can be solved to give x = 2.0829. We can then subsitute this into either
(7.63) or (7.64) to give a = 2.766×109 . The resultant equation can be multiplied
12 Even using this technique it is difficult to get accurate results since it is hard to read off
by 250/200 = 1.25 to account for the fact that it has been derived for a frequency
of 200kHz (this is a crude extrapolation). Therefore the resultant expression for
the losses is:
3
Pv = (3.4575 × 109 )B 2.089 W/m (7.67)
at a frequency of 250kHz.13
We are now in a position to calculate the losses. However, before doing this
we must calculate the AC component of the flux density in the material (as
noted earlier). Recall from (7.44) that the current ripple through the inductor
is 0.381 Amp. Therefore the AC magnetic field intensity is:
N IAC 29 × 0.381
ĤAC = = = 274.85A/m (7.68)
le 0.0402
Assuming that the core relative permeability stays at 90 then we can work out
the peak to peak flux density as a result of the ripple current:
We can now work out the losses by using the B̂ value from (7.69) in (7.67) to give
Pv = 2.439e6W/m . For the volume of material in the core (Ve = 635×10−9 m3 )
3
the loss is Pv Ve = 1.54W. This power dissipation is outside the specification for
the inductor by a factor of 5 times. Therefore we must go back to the drawing
board with this design.14
In order to lower the losses in the core we need to go to a larger core size.
Let us try the TN24/15/7.5 core. We shall quickly go through the same design
process as carried out above. In this case the AL = 61nH, and consequently:
35 × 10−6
N= = 23.95 turns (7.70)
61 × 10−9
Therefore we will make the turns equal to 24.
Given the turns we can now work out the maximum AC flux density variation
as:
LIAC (35 × 10−6 )(0.381)
BAC = = = 0.0169 Tesla (7.71)
N Ae (24)(32.8 × 10−6 )
Substituting this into (7.67) gives Pv = 690, 162 W/m3 . Therefore the total
power dissipation is PT = Pv Ve = 690, 162 × 1895 × 10−9 = 1.3 Watts. This is
less than in the previous case, but is still approximately 4 times the specification.
One might suspect that we will have trouble satisfying the specification from
the small change in the losses for the change in the core. Indeed, if one chooses
the largest core in Figure 7.19, TN33/20/11, we will still have trouble satisfying
the specification. If this is carried out the core losses are of the order of 0.7
Watts, which is still twice the specification.
The question is now what can we do. If we are to stick with the frequency
of operation we need to find a core material with lower core losses. However,
13 This expression is only going to give a ball park figure for the losses. To get accurate
core. However, the resultant losses found in [13] are approximately 1/10th those found above.
The Lenk analysis uses a complex mix of units, so I am assuming that there has been an error
in one of the units conversions. I have been unable to find an error in the design calculations
above.
268 Introduction to Practical Design of Switch Mode Power Supplies
if the frequency of operation is part of the design mix then we can make this
lower. This will also have the effect of increasing the ripple in the current, so
the inductance value would have to be varied to allow this specification to be
satisfied.
Let us briefly consider a drop in the frequency to 100kHz. If we want the
same ripple of 0.38 Amp in the 2 Amp DC current then the inductance value
can be found to be 87µH using (7.44). The turns can nw be found to be 32
turns using (7.58) and the value for AL = 87nH (for the TN33/20/11 core).
Therefore BAC = 0.012 Tesla using (7.71) with the new values. Reading off the
approximate value for the losses per m3 from Figure 7.21 we can see that it is
approximately Pv = 70W/m3 . The core volume is 5200 × 10−9 m3 , and hence
the total core losses are PT = Pv Ve = 0.364 Watts. This is still outside the
original specification in relation to the losses, but it is much closer than those
calculated previously. A further improvement can be made in relation to the
losses by lowering the frequency further, but the number of turns required to
achieve the higher inductances mean that check would have to be made to see
if there is enough winding area.
Remark 7.46 The fundamental problem with the above design is that the ma-
terial chosen has too high a power dissipation per unit volume. The specification
is much easier to satisfy if a lower loss material is chosen. For example, the
2P material we chosen has a lose of approximatley 200kW/m3 at 10mT flux
density. The 3C material by the same manufacturer has losses so low (of the
order of 1 rightarrow 2 kW/m3 ) that the manufacturer has not plotted them
below approximately 10mT. Therefore the specification would have been satisfied
if this, or a similar low loss material had been chosen at the outset. For exam-
ple, in [13] the same design is carried out using MPP material manufactured by
Magnetics Inc.. This material has a loss of 18.2kW/m3 at 10mT flux density.
In this design the core losses turn out to be 140mW.
Remark 7.47 The frequency of operation of this inductor would mean that
Litz wire should probably be used. This would change the wire area calculations
above. The skin effect at 250kHz needs to be considered. In fact if the frequency
is above 50kHz the skin effect must be considered.
7.3.5.3.1 Turns Ratio = 1:1 This would imply that when 48VDC is ap-
plied across the primary there is 48VDC across the secondary (ignoring the
leakage inductance of the transformer). The problem with this voltage is that
one cannot obtain Schottky diodes above about 45 volt with a low forward volt-
age drop. One would require a diode with a voltage rating significant higher
than 48 volt, therefore the forward voltage drop will be high.
Remark 7.48 For high current outputs forward voltage drop is important. The
loss is Vf Io , and this is being dissipated in the rectifer diode, or the free-wheeling
diode. One can use synchronous rectifiers to overcome this problem, but this
requires a significant increase in the complexity of the circuit due to their drive
and control requirements.
For the diode loss reason given above the choice of a 1:1 turns ratio is not a
good one.
7.3.5.3.2 Turns Ratio = 2:1 The primary has twice the turns of the sec-
ondary, meaning that there is 24VDC on the secondary. This means that the
duty cycle of the converter is approximately Vout /Vsec = 0.21. The current
through the primary of the transformer (assuming that there is a constant 20
Amp current in the load) is 0.5 × 20 = 10 Amp. This quite a bit of cur-
rent for a MOSFET switch. The losses in the MOSFET are approximately
102 × RDSon × 0.2. These losses may result in an expensive MOSFET, or alter-
natively a large heat sink.
7.3.5.3.3 Turns Ratio = 3:1 In this case the secondary voltage is 16 volt
and the primary current is approximately 7 Amp. The duty cycle is 0.31.
Therefore the losses are 72 × RDSon × 0.31, which is substantially lower than
in the previous case.
7.3.5.3.4 Turns Ratio = 4:1 The secondary voltage in this case is 48V DC/4 =
12V DC. Therefore the duty cycle is Vout /Vsec = 5/12 = 0.42. This duty cycle
is very close to the limit cycle of many of the popular PWM ICs (which are
limited to duty cycles of 0.45). If there is any variation in the input voltage,
and if the diode drops are accounted for, then it is possible for this limit to be
hit.
The conclusion of the above turns ratio scenarios is that a turns ratio of 3:1
is probably the best one to choose.
The remainder of the design of the forward transformer involves the choice
of the core material and the magnetising current. The magnetising current is
important, since this current does not contribute to the load current, but does
contribute to the losses in the converter. The magnetising inductance is also
important from the point of view of losses in the core. Fortunately, lowering the
magnetising current involves increasing the primary turns (whilst maintaining
the 3:1 turns ratio), which in turn also lowers the flux density in the core (for
a fixed input voltage). There is a limit to how far this can be taken, since the
more turns requires more copper in both the primary and secondary. Hence this
impacts on the size of the transformer.
270 Introduction to Practical Design of Switch Mode Power Supplies
The general rule in relation to wire gauge is simple – don’t select wire that is
too thick or too thin.
Practical Issue 7.8 It is best to limit the wire gauges to a maximum of #20
(i.e. 7.91 × 10−7 m2 ) and an minimum of approximately #38 (i.e. 0.132 ×
10−7 m2 ). For wire gauges thcker than #20 some machine cannot wind the
cores, and above #18 there is a risk of fracturing the core as the wire is wound
around it.
Wire gauges thinner that #38 can still be machine wound, but it is difficult
to build prototype cores with wire this thin – it is as thin as a human hair.
Therefore it is best to use #38 wire even if you can get away with thinner wire.
Another aspect of wire gauge to consider is that one should try and limit
the number of different wire gauges being used. This will allow some volume-
of-purchase economies to be obtained.
If you are winding different wires onto a magnetic structure, and these are
layered on top of each other, then try and keep the wire gauges close together.
This helps prevent the thinner wire from finding its way into the crevices of the
thick wire – the different windings do not form nice layers. When this happens
it can effect the leakage and coupling of the magnetic circuit.
Practical Issue 7.9 Try to keep the wire gauges in a magnetic structure within
10 of each other.
If a toroid is going to be machine wound then the only limit on the windings is
the size of the winding area and the size of the wire. However, if one is to hand
wind these cores there is a practical limit set on a human’s ability to concentrate
and count.
Practical Issue 7.10 Hand winding a toroidal core is a real pain. If one is
going to wind a prototype one by hand it is best the keep the number of turns
below approximately 200. It is very easy to forget the number of turns on the
core (even for this number).
7.3 Introduction to Magnetics Design 271
Practical Issue 7.11 Adding tape insulation layers should be avoided if possi-
ble. The tape takes up a lot of area, and even more importantly it usually must
be put on by hand.
Remark 7.49 In many cases it may be better to go to thicker and higher class
wire insulation instead of using tape. It is less labour intensive and can lead to
a more compact design.
Primary
winding
Primary
winding
Bobbin
Figure 7.22: Winding interleaving for high-dielectric isolation and good primary
to secondary coupling.
7.3.6.7 Potting
Potting is the process of filling up a volume surrounding a magnetic structure
with a thermally conductiove compound for the purpose of improving heat re-
moval by providing a better thermal path. It also strengthens the structure,
and prevents the incursion of environment factors that may affect the life of
the magnetic structure. The potting can also be utilised to provide mechanical
mounting points for the structure.
There can be some problems with potting – it makes the unit heavier, the
shrinkage of the potting mix as it cures can result in changes to air gaps in
gapped cores, and some magnetic materials (e.g. MPP) are strain sensitive,
and their permeability can change as the potting shrinks.
Insulation layer
Creepage distance (4mm)
Insulating tape
Core
Secondary
Primary
Line Commutated
Converters and High Power
Inverters
Chapter 8
8.1 Introduction
• Electric vehicle propulsion systems. These systems are one of the very
high profile applications of modern power electronics. They incorporate
innovative electrical machines coupled with inverter, computer and bat-
tery/generator technologies.
• Power system static VAR compensators. These are power electronic de-
vices that are able to supply the VARs required for inductive loads on
power systems. They are commonly used to improve power factor and to
aid in the stability of the power system.
8.2 Review of Power Semiconductor Devices 279
• Active filters. Modern power electronic devices on the power supply grid
can generate harmonics into the grid supply. These can cause problems
with other devices connected onto the grid. An active filter is another
power electronic device that is capable of cancelling out the harmonics
produced by these other devices.
The above examples are only a selection of the industrial and residential
applications of power electronics. This technology is not always obvious to the
user, but is being incorporated into a larger variety of products. Therefore an
understanding of at least the basics of the technology is essential for the modern
electrical engineer.
8.2.1 Diodes
Figure 8.2 shows the basic conceptual diagram for a diode. This diagram is
valid for a general purpose diode, but power diodes have a different structure in
order to improve the voltage blocking capability of the device and at the same
time keep the on-state resistance as low as possible.
280 Introduction to High Power Converter Technology
The iv characteristics of conventional and power diodes are much the same,
and a generic diagram is shown in Figure 8.1. Note the offset voltage of ap-
proximately 1 volt. It is this voltage that leads to the majority of the power
dissipation. Also note the slope on the characteristic as the voltage across the
device increases above 1 volt – this represents the effects of the bulk resistance
of the device. Whilst the 1 volt offset is virtually intrinsic in the operation of the
diode, the bulk resistance contribution to the power losses can be minimised by
changing the doping of the semiconductor materials. The breakdown voltage,
vBD , is a very important parameter in power diodes. Much of the design of
these diodes is related to improving vBD .
iD
v BD
vD
» 1V
Figure 8.3 shows the conceptual structure of a power diode. Note that the
main difference between this structure and that of Figure 8.2 is that there is
a n− region interleaved between the normal p+ and n+ regions. This region
is known as the drift region, and under reverse bias is the region where the
depletion region lies.
At first the presence of the n− region in the device would seem to be a
little silly, since it must add to the bulk resistance of the device. Under certain
circumstances this is indeed true, but by careful control of the doping profiles
this effect can be minimised. This region is in the device to improve the voltage
blocking capability. We shall not look at the equations that prove this, but
heuristically the reason is that if one supports a voltage over a longer distance,
then the volts per metre must be smaller than if the voltage is supported over
a shorter distance. Therefore, when the device is in reverse bias, the depletion
region almost exists entirely in the n− region1 , and consequently the electric
field in the semiconductor material is lowered because of its length.
As mentioned previously the problem with having the n− region would ap-
pear to be that the bulk resistance of the diode would appear to increase. This
1 The depletion region supports the reverse voltage.
8.2 Review of Power Semiconductor Devices 281
Anode Cathode
Anode Cathode
p+ n+
Anode Cathode
Anode Cathode
p+ n- n+
Wd
Drift Region
+ vD - Forward bias
iD } voltage and
current
directions
is true depending on how the diode is designed. There are two forms of structure
in Figure 8.3:
1. The non-punch through diode.
2. The punch through diode.
non-punch through The non-punch through diode refers to a diode where the depletion region lies
diode entirely in the n− region under reverse bias. Therefore the depletion region does
not punch through the n− region. Other the other hand the punch through diode
has a the n− region a little narrower and more lightly doped. This structural
change has two effects:
1. The same length n− region can support a larger reverse voltage.
2. The bulk resistance of the device is lower than that of a non-punch through
diode.
punch through
diode We shall not concentrate on the former effect, suffice to say that his is
achieved by keeping the peak electric field intensity lower in the device [4]. The
lower bulk resistance is achieved because of a conductivity modulation effect,
this occurring because there is injection of carriers into the n− material not only
from the p+ material, but also from the n+ material during forward bias. These
extra carriers create in the n− region lower the bulk resistance of the region in
forward bias.
The other important property of diodes, and especially power diodes, is
reverse recovery the reverse recovery. This refers to an effect when the diode can conduct a
reverse current for a small period of time under reverse bias, after it has been
forward biased. This effect is due to stored minority carriers that accumulate
in the device under forward bias conditions. These carriers must be removed
before the device can block voltage, and it is the removal of these carriers that
constitutes the reverse recovery current.
Figure 8.4 shows a typical reverse recovery characteristic of a diode. Initially
the diode is forward biased and carries a forward current (i.e. anode to cathode).
However as the current goes to zero it continues to flow in the reverse direction
through the diode as the charge is removed from the device. Eventually all the
minority carriers are removed, and the current then starts to decrease as the
reverse voltage rises across the device. During this phase the depletion regions
are being established. Eventually all the charge has been removed and the diode
then stops conducting and it supports the full reverse voltage. The shaded area
represents the total stored charge removed from the device.
Remark 8.1 Charge storage and the associated reverse recovery has important
practical consequences in power electronic circuits.
Alterations can be made to the semiconductor additives in power diodes
in order to minimise the reverse recovery time. These diodes are known as
fast recovery fast recovery diodes. The recovery time of a normal diode can be 4 to 6µsecs,
whereas a fast recovery power diode can have a recovery time of 1 to 2µsecs.
Unfortunately fast recovery diodes have a relatively large forward voltage drop
(≈ 1.5 volt).
The other main type of diode that is used in power electronic applications is
the Schottky diode. Because this diode uses a metal-semiconductor junction as
8.2 Review of Power Semiconductor Devices 283
iD
Diode begins to
t rr support reverse
voltage
t
Qrr
the basis for the diode it does not have a charge storage problem. Furthermore,
the forward turn-on voltage of the device is much lower than a conventional
diode – of the order of 0.2 to 0.3 volt. One is tempted to ask the question “why
aren’t Schottky diodes used everywhere in power electronics?”. The answer
to this is that the Schottky diode cannot support large reverse voltages, and
therefore is only suitable for low voltage applications (up to approximately 100
volt).
8.2.2 Thyristors
The thyristor, or silicon controlled rectifier (SCR) is essentially a controlled
turn-on diode in terms of its external characteristics. They are the oldest of the
semiconductor power electronic switches (invented in 1957 at General Electric
research labs), but nevertheless, because of their characteristics, they will have
continuing application in power electronics. They also have the highest power
rating out of all the power electronic devices.
Figure 8.5 is a conceptual diagram of a thyristor’s structure and its circuit
symbol. Notice that the device is a three terminal structure, with the addition
of a gate terminal. This diagram also shows that the device is a three junction
structure, consisting of what appears to be two diodes in series. It should be
noted that this linear semiconductor diagram is not really representative of how
the device is physically laid out in silicon.
To understand how the device works one can develop the approximate model
284 Introduction to High Power Converter Technology
Anode Cathode
Gate
iA J1 J2 J3
iK
- +
p1 (n ) p2 (n )
n1 n2
Anode Cathode
Gate iG
for the device shown in Figure 8.6. This diagram shows that the thyristor
consists of a feedback structure consisting of a PNP and an NPN transistor.
From ones knowledge of the behaviour of the transistor one can see that if a
current is fed into the gate (terminal G) then transistor Q2 will turn on. This
will result in the PNP transistor, Q1 turning on. Because the collector of Q1
is connected to the base of Q2, the current from Q1 forms the base current for
Q2. If the current gain around the loop of the two transistors is greater than
one then the initial turn gate current can be removed and the device will remain
on.
Anode
iA , iE 1
J1
i B1 Q1
J2 iC 1
iC 2 iG
Q2
iB 2 Gate
J3
Cathode iK iE 2
Under blocking conditions one wants the gain around the loop consisting
of the two transistors to be less than one. This corresponds to α1 + α2 being
small (which means that the transistor current gain product β1 β2 < 1), where
α1,2 = iC1,2 /iE1,2 , . This is the normal state of the transistor.
The thyristor is turned on by changing the effective α’s for the two transis-
tors. This is achieved by changing the depletion region across the J2 junction,
8.2 Review of Power Semiconductor Devices 285
which effective modulates the width of the bases of the two transistors. There-
fore as a larger positive voltage is applied at the anode with respect to the
cathode, the depletion region grows. Eventually the α’s will get to a point
where the leakage currents across the junctions are enough to supply a current
which will begin the regenerative process. This will cause the thyristor to turn
on without any gate current. The voltage that has to be applied across the
device to cause this to happen is known as the forward break over voltage. forward break over
If a gate current is applied it is possible to cause the device to enter the voltage
positive feedback region prior to the forward break over voltage. The gate
current causes carriers to be injected across J3 and diffuse to the depletion
region at J2 . Here they are swept by the electric field of the depletion region
into n1 . The result is that the depletion region at J2 widens to account for the
minority carriers injected. This is due to the fact that more donor atoms have
to be uncovered to account for the electrons injected from p2 . The net result
is that the effective bases of the two transistors narrow, and consequently the
α’s increase. Once these reach the critical value then the positive feedback will
again occur and the device will latch on. The main point to note is that the
gate current has achieved this at a lower voltage than the break over voltage. If
the gate current is higher, then the lower the forward voltage can be when the
device will latch on.
The above discussion is captured in the iv characteristic of a generic thyristor
shown in Figure 8.6. There are several points to note about this characteristic.
If the gate current is zero, and a forward voltage is applied, then if the voltage
reaches the level of vBO the thyristor begins to conduct. This is known as the
break-over voltage. Once the device begins to conduct, the voltage across the
device falls to a low level dependent on where the load line crosses the forward
characteristic.
Similarly if the thyristor is reverse to a level of vRW M , the maximum reverse
working voltage, then the device will begin to conduct (as will a diode if reverse
breakdown occurs). The vRW M voltage usually has about the same magnitude
as the vBO voltage (by design).
The most interesting aspect of the thyristor characteristic is the fact that
the effective vBO voltage can be lowered by the application of a gate current.
It is this fact that makes the thyristor behave as a switch. Once the device has
“broken over” the device enters a negative resistance region prior to entering the
forward on-state region. For the device to enter the forward on-state condition
a minimum current, iH , must be flowing through the device. This is known
as the holding current. If this current cannot be sustained then the device will holding current
re-enter the forward blocking state.
Remark 8.2 Thyristors are still the device of choice for very high power ap-
plications. They are capable of withstanding very high voltages (of the order of
6-7kV) and can conduct currents in the range of 2-3kA.
Remark 8.3 Another important characteristic of the thyristor is that the gate
current does not have to be maintained after the current through the device
reaches the holding current. However, on the downside, the gate current cannot
be used to turn the device off. The device can only be turned off if the external
circuit conditions allow the current in the device to fall below the holding current.
286 Introduction to High Power Converter Technology
iA
Forward on-state
Increasing iG
iG = 0
iH
v RWM i BO
vH v BO v AK
Forward blocking
state
There are two external aspects of the transient performance of these devices
that are practically very important – the turn-on and turn-off limitations.
Figure 8.8 shows a typical turn-on transient for a thyristor. There are several
points that can be made about this diagram. After the gate pulse is applied
there is a delay before the thyristor turns on (td ). This is due to the time that
it takes the minority carriers to build up in the p2 material shown in Figure 8.5.
After td the device starts to enter positive feedback and begins to turn on. The
current in the device builds up with a slope of diA /dt, this being determined by
the voltage and the external circuit inductance. Notice that during this period
the voltage across the device is starting to fall quite rapidly, but there is still
a substantial voltage across the device. Consequently there can be substantial
power dissipation in the device during this phase. After the rise time period has
finished there is a further period of voltage drop across the device known as the
spreading time, ts . This is the time required for the current density to become
even across the device cross-section.
The diA /dt time is important, since if a maximum value is exceeded the
device can be damaged. This damage occurs because there is uneven current
distribution in the thyristor during turn on, and if the current is increasing too
quickly hot spots may develop in the device (because there is not enough time
for the current to spread adequately over the cross-section of the device).
8.2 Review of Power Semiconductor Devices 287
iG
t
iA
di A
IA dt
t
v AK
t
td tr ts
iA
t rr
di R
dt
t1 t2 t3
t
irr
4
irr
v AK
dv F
dt
v REV
where β2 = α2 /(1 − α2 ). Using (8.1), (8.2) and (8.3) one can develop that
following expression:
iA
iG > (8.4)
βt off
where the parameter βt off is the turn off gain given by:
α2
βt off = (8.5)
α1 + α2 − 1
Remark 8.5 From (8.4) one can see that the βt off value should be as large as
possible to keep the iG value as small as possible. This implies that α2 → 1
and α1 should be small. Therefore the semiconductor regions in the GTO are
designed to achieve this objective.
• The circuit symbol for the GTO (as compared to that of the thyristor).
• The Ls on inductor and associated parallel resistor and diode form a turn-
on snubber3 circuit.
turn-off snubber Remark 8.6 The use of a turn-off snubber with the GTO is absolutely essen-
tial. If the device is turned on prior to all the internal stored charge being
dissipated, then there is a very poor distribution of the turn-on current, result-
ing in local heating and possible destruction of the device. This occurs because
of the particular internal construction of the GTO. The presence of the turn-off
snubber prevents the “automatic” re-turn-on of the device when the voltage rises
across it too quickly.
3 A snubber circuit is an auxiliary circuit that is designed to protect the main switching
Load current
D fw iL
Turn-on snubber
Rs_on Parasitic
Ls_on inductance
+
Vd Cd D s_on Ls
D s_off Rs_off
GTO
+
C s_off
Turn-off snubber
iG t w1
“Backporch” current
iGT
0 t
iA
td
0 t
v AK
0 t
vGK
0 t
The other point to note in Figure 8.11 is the effect of the series inductance
Ls on on the anode current during turn-on. Notice that diA /dt is limited by
4 This unwanted turn-off condition could also damage the device due to uneven distribution
this inductance so that the current is distribute evenly across the device, and
the voltage across the device is shared with the inductor during turn-on. This
inductor also stops the otherwise large reverse recovery currents in the circuit.
The reverse recovery actually results in the current overshoot represented by
the overshoot during turn-on.
iG
iGT
0 t
iA t4 t tail
io
0 t
v AK
t2
t1
dv dv Vd
<
dt dt max
0 t
vGK Inductive spike due to parasitic L in
the snubber circuit.
0 t
t3 vGG-
turn-off failure
Remark 8.8 If the anode current becomes too large there is the possibility that under short circuit
the gate current may not be able to turn the device off (there is a limit to the conditions
magnitude of the gate current, determined by the semiconductor properties of
the device). This is a particular problem under short circuit conditions, since
this is an abnormal condition that would not be designed for.
Remark 8.10 One problem with the crowbar protection technique is that the
presence of a fuse in the dc link introduces inductance in this part of the circuit.
This can result in significant over-voltages when the main GTO is turned off.
Fuse
Load
Remark 8.11 There are several variants to the classical GTO that are be-
ing championed by different manufacturers. For example, Asea-Brown-Boveri
(ABB) has the IGCT - the Integrated Gate Commutated Thyristor. This is es-
sentially a modified GTO with tightly coupled gate drive circuitry built onto a
card with the GTO power device. It is a high power device – 4.5kV and 3kA. The
onboard GTO has low conduction losses and does not require a turn-off snubber.
The better gating allows higher switching frequencies as compared to standard
GTOs (of the order of 1000Hz). Rockwell/Allen-Bradley have a similar device
called the SGCT – the Symmetrical Gate Commutated Thyristor.
296 Introduction to High Power Converter Technology
• The result of the injection of minority carriers in the device is that it can
carry much larger currents as compared to the MOSFET, since the current
is carried in more than the channel of the device.
• The injection of carriers into the device means that the on-state losses for
this device are lower than those of a comparable power MOSFET.
The n+ layer between the p+ drain layer and the n− drift region is not
essential for the operation of the device. As with the diode considered earlier,
one can have punch-through and non-punch-through IGBTs. The n+ layer is
required for the punch-through devices to prevent the J2 space charge region
from going all the way to the p+ drain region. The presence of the n+ layer can
significantly improve the operation of the IGBT.
Remark 8.13 In Figure 8.14 there is a parasitic SCR shown. This is an unde-
sirable feature of the structure, and design efforts must be made to ensure that
the loop gain of the SCR is not greater than one so it does not turn on.
The circuit symbol for the IGBT appears in Figure 8.15(c) and (d). Note that
the symbol in (c) is very nearly the same as that for the n-channel MOSFET,
except that there is an arrow on the drain connection indicating the direction of
the current due to the injection of carriers here. Figure 8.15(d) shows a symbol
that is emphasising the similarity of IGBT with the NPN bipolar transistor.
Source Gate
SiO2 SiO2
+ +
Body
n n region
J1 p
J2
Drain drift
Ls
-
region
n
J1
Buffer
n+ layer
p+
Injecting
layer
Parasitic
SCR
Drain
Figure 8.16(a) shows the current flows in the device when it is turned on.
When the gate voltage exceeds the threshold voltage an inversion layer forms
beneath the gate of the IGBT. This channel shorts the n+ to the n− layer, as
occurs in the MOSFET. The current flow through this channel also results in
holes being injected from the p+ region into the n− region. These holes move
across the n− drift region via drift and diffusion via a number of paths. These
carriers reach the p body region (not necessarily where the channel is) and then
are swept through to the source via recombination at the source metallisation.
The junction of the n− region and the p region is called the collector region,
since is operates the same as the collector region in a thick PNP transistor.
The connection between the layers and parasitic transistors is shown in Fig-
ure 8.16(b). Notice that the injection layer, denoted as the p+ layer, acts as an
emitter in a BJT transistor, emitting or injecting holes into the n− base region
of the device.
As current flow through the IGBT there are voltage drops in the device due
to the bulk resistance of the semiconductor materials used. These are shown in
Figure 8.16 as dashed resistors. These resistance values are important for two
different reasons; (i) if the resistances are too high then the device will dissipate
more power; and (ii) if the voltage drops are too high in the resistances then
parasitic thyristor in the IGBT may turn on.
Figure 8.17(a) and (b) shown an equivalent circuit for the IGBT. Figure 8.17(b)
is more complete, showing the parasitic thyristor, and the body spreading re-
sistance. If the body spreading resistance is too high then the current gain of
the thyristor may become greater than one, and consequently the thyristor will
turn on. Once this happens then the device no longer behaves as an IGBT, and
power must be remove across the device to turn it off. Needless to say, much
design effort has gone into ensuring that the parasitic IGBT does not turn on.
298 Introduction to High Power Converter Technology
iD
Increasing vGS
v RM
v DS
v DS
brk
(a)
» 0.7 V
iD
Drain
Drain
Gate Gate
Source
vGS Source
vGS th
(c) (d)
(b)
Figure 8.15: The IGBT voltage and current transfer characteristics and circuit
symbol: (a) output characteristic; (b) transfer characteristic; (c) and (d) n-
channel IGBT circuit symbols.
8.2 Review of Power Semiconductor Devices 299
circuit of the type shown in Figure 8.10, except that the main power device has been replaced
by the IGBT and there are no snubbers.
7 R is the gate resistor that is included in the circuit to limit the gate currents to reasonable
G
levels.
300 Introduction to High Power Converter Technology
The major difference between the IGBT turn-off and the power MOSFET
turn-off is observed in the drain current waveform which has two distinct time
intervals. During the tf i1 time the MOSFET is turning off. The second time
interval tf i2 is due to the stored charge in the n− region of the device. Since
the MOSFET is off there is no way that these carriers can be swept out of
the device by a negative drain current. Consequently these carriers diminish
by recombination. The punch-through IGBT attempts to minimise this effect
by having a small carrier lifetime in the n+ region. This results in an electron
concentration gradient from the n− region to the n+ region, thereby sweeping
the electrons from the device.8 The non-punch-through IGBT attempts to min-
imise the tail off current by redesigning the IGBT so that the majority of the
current is carried by the MOSFET. This minimises the stored charge.
At the time of writing these notes IGBTs are in a rapid state of development.
Currently the most advanced devices are capable of withstanding approximately
6kV, and can conduct several thousand amperes. The turn-off times for these
devices are of the order of 1µsec of less. For medium power systems IGBTs are
currently the device of choice.
Source Gate
Channel
i
SiO2 SiO2
- + + -
n n
p
Drift region
resistance
n-
n+ Minority
+ + + + p +
+ + + +
} carrier
injection
i
Lateral body
spreading
Drain
resistance
(a)
Source Gate
i
SiO2 SiO2
+ +
n n
p
} Collector
region
n-
n+ Minority
p + } carrier
injection
Drain
(b)
Gate Gate
Source
Source Body region
spreading
resistance
(a) (b)
Figure 8.17: Equivalent circuits for the IGBT: (a) approximate equivalent circuit
for normal operating conditions; (b) more complete equivalent circuit showing
the parasitic thyristor.
304 Introduction to High Power Converter Technology
vGS / vGG
vGG
vGS
t
0
td(on)
iD
Io
t
t ri
v DS
Vd
v DS (on)
t
t fv1 t fv 2
C gd
Rg
v DS
vGS
vGG
Definitions C gs
vGS / vGG
vGG
vGG
vGS ,I vGS
o
vGS(th)
t
0
iD
Io
td(off) t fi 2 } MOSFET
current
BJT
} t
current
0
t rv t fi1
v DS
Vd
t
0
Anode
A
Gate
G
OFF-FET
K
ON-FET
Cathode
Figure 8.20: Schematic and circuit symbol for the P-MCT.
306 Introduction to High Power Converter Technology
Chapter 9
Line Frequency
Uncontrolled Rectifiers
9.1 Introduction
The power input into most power electronic devices is derived from 50/60Hz ac
sine wave supplies provided by the electricity authorities. This supply generally
is converted into a dc supply before being used or converted into another form.
The traditional and simplest way of achieving the ac–dc conversion is via an
uncontrolled rectifier based on diodes. Such rectifiers only allow power to flow
from the ac to the dc side. The vast majority of power electronic applications
currently use such rectifiers to do the ac–dc conversion, although this situa-
tion may change in the future due to mains harmonic requirements (which are
difficult to meet using conventional rectifiers).
This chapter shall look at the basic operation single phase and three phase
uncontrolled rectifiers. Some analysis will be carried out (based on the as-
sumption of ideal diodes) to ascertain the harmonic performance of the various
rectifiers. Before doing this there is some concepts that we will need to intro-
duce.
One of the characteristics of diode rectifier circuits is that the produce non-
sinusoidal currents in the ac mains. Therefore consideration of non-sinusoidal
waveforms is relevant to carrying out analysis of these types of circuits. Much
of the analysis is carried out assuming that the circuits are in steady state,
and then calculating the Fourier components in the current (and in some cases
the voltage) waveforms. We shall therefore quickly review Fourier analysis as
applicable to power electronic waveforms.
308 Line Frequency Uncontrolled Rectifiers
Consider Figure 9.1 which shows the voltage and current waveforms in a situ-
ation where a power electronic device is connected to the grid supply [4]. The
current waveform shows significant distortion.2 The voltage on the other hand
is shown without distortion, since it usually does not display the same amount
of distortion as the current. This is the case because the voltage distortion arises
from the current causing a voltage drop across the line impedances.3
vs
v, i
is
is1
i dis
0
wt
f1
2 The distortion in this current waveform is typical of that one would expect from a diode
where:
is1 the fundamental line current
isn the harmonic components of the line current
We can write (9.12) in an expanded form as follows:
∞
!
√ √
is (t) = 2Is1 sin(ω1 t − φ1 ) + 2Isn sin(ωn t − φn ) (9.13)
n=1
where:
φ1 the phase angle of the fundamental (9.14)
Is , Isn rms value of the relevant harmonic (9.15)
The rms value of the current can be calculated using the general expression
noted in footnote 1. If expression (9.12) is substituted into this, the cross-
product terms all integrate to zero due to the orthogonality property of cos and
sin functions. The rms current therefore becomes:
#
$ !∞
$ 2
%
Is = Is1 + 2
Isn (9.16)
n=1
v = V cos ωt (9.22)
i = I cos(ωt + θ) (9.23)
P = vi (9.24)
= [V cos ωt][I cos(ωt + θ)] (9.25)
= V I cos ωt[cos ωt cos θ − sin ωt sin θ] (9.26)
= V I cos2 ωt cos θ − V I cos ωt sin ωt sin θ (9.27)
1
Using cos2 ωt = [1 + cos 2ωt] one can write (9.28)
2
V I cos θ
P = [1 + cos 2ωt] − V I sin θ cos ωt sin ωt (9.29)
2
Using the trig relation:
1
cos ωt sin ωt = sin 2ωt
2
we can modify the last term of (9.29) as follows:
V I cos θ VI
P = [1 + cos 2ωt] − sin 2ωt sin θ (9.30)
2 2
VI VI VI
= cos θ + cos θ cos 2ωt − sin θ sin 2ωt (9.31)
2 2 2
Using cos(x + y) = cos x cos y − sin x sin y, this can be written as
V I cos θ VI
P = + cos(2ωt + θ) (9.32)
2 2
Average Real power Oscillatory component
The oscillatory power component represents the power flowing into and out of
the storage element of the particular circuit.4 The average real power component
essentially causes an offset in this oscillation component so that there is an
average value of power over a complete cycle.
The other way of representing the power expression for sinusoidal steady
state systems is in the form of the complex power: complex power
4 As we shall later this component consists of two different parts, one belonging to the real
−
→ →−
− →
S =V I∗ (9.33)
where ‘∗’ represents the complex conjugate, and the −
→
x means that x is a phasor.
Let us assume that:
→
−
V = Vrms ejα (9.34)
→
−
I = Irms ejβ (9.35)
where Irms and Vrms represent the current and voltage RMS values.
Substituting (9.35) and (9.34) into (9.33) we can write:
→
−
S = Vrms Irms cos θ + jVrms Irms sin θ (9.36)
where θ = α − β.5
Equation (9.36) is broken up into two components:
P = Vrms Irms cos θ (9.37)
Q = Vrms Irms sin θ (9.38)
One can see the vector relationship of these components in Figure 9.2. Notice
that the use of the complex conjugate in the complex power expression means
that the angle used is effectively the angle of the voltage phasor with respect to
the current, despite the fact that the convention is that the currents phase is
measured relative to the voltage.6
Imag
P = VI cosq
r
I
V cosq
r
V
q =a -b
a
Real
V sinq
Q = VI sinq
The correspondence between (9.37) and the average real power component
of (9.32) is easy to see. However, the correspondence between (9.38) and the
5 The angle θ is the angle from the current vector to the voltage vector.
→ −
− →−→
is possible to define complex power as S = I V ∗ . In this case the angle is the current
6 It
with respect to the voltage in the power expression. The meaning of the sign of the complex
power changes with this definition.
9.2 Some Mathematical Preliminaries 313
where V and I are the peak values of the voltage and current.
We can see from this expression that the real power actually oscillates (with
the oscillation being unipolar), and has an average value of (V I/2) cos θ. The
reactive power component on the other hand does not have an offset term and its
average value is zero. The amplitude of this term is equal to the Q term in the
complex power expression. Therefore the reactive power component corresponds
to power that is flowing into the circuit and out again per half cycle of the
fundamental voltage (or current). These components are shown in Figure 9.3
for a phase angle of 30◦ . This plot is of the normalised power, the normalisation
factor being Vrms Irms . Notice the reactive power component has no average dc
component.
Real power
1.5 Total power
Average power
Normalised power
-0.5
0 1 2 3 4 5 6 7
q [rad]
Figure 9.3: Diagram of the normalised single phase power components with a
30◦ phase angle – the power is normalised by dividing by Vrms Irms .
Remark 9.2 With an inductive load the current lags the voltage (or the voltage
leads the current). Therefore in the complex power expression the angle θ is
314 Line Frequency Uncontrolled Rectifiers
2π 2π
1
cos(θ) cos(nθ) dθ = [cos((n + 1)θ) + cos((1 − n)θ)] dθ (9.47)
0 0 2
2π 2π
1
= cos(n + 1)θ dθ + cos(1 − n)θ dθ (9.48)
2 o 0
2π 2π
1 sin(n + 1)θ sin(1 − n)θ
= + (9.49)
2 n+1 0 1−n 0
1 sin(n + 1)2π sin0 sin(1 − n)2π sin 0
= − + −
2 n+1 n+1 1−n 1−n
(9.50)
=0 (9.51)
Note that if n = 1, then (9.47) becomes:
2π 2π
cos(θ) cos(θ) dθ = cos2 θ (9.52)
0 0
2π
1
= [cos 2θ + cos 0] dθ (9.53)
2
0
2π
1 sin 2θ 2π
= + [θ]0 (9.54)
2 2 0
= 2π (9.55)
Remark 9.5 Remark 9.4 above shows that the product terms involving different
frequencies integrate over the fundamental frequency to zero, whereas terms at
the same frequency integrate to give a non-zero term.
Substituting in (9.11) for vs and (9.13) for is , and noting from Remark 9.4
that the the integral of the cross-product terms are zero, we can write:
T1 √ √
1
P = 2Vs sin ω1 t · 2Is1 sin(ω1 t − φ1 )dt = Vs Is1 cos φ1 (9.56)
T1 0
316 Line Frequency Uncontrolled Rectifiers
Remark 9.6 Equation (9.56) shows that the harmonic currents DO NOT con-
tribute to the average (real) power drawn from the source. Therefore, one can
consider that the harmonics contribute to the reactive power drawn from the
source. This is the basis for the generalisation of the concept of power factor.
We can generalise the power factor expression by realising that the apparent
power is simply:
S = Vs Is (9.57)
where Vs and Is are the true rms values of the voltage and the current (i.e. the
rms value of a non-sinusoidal current). Therefore, using the same approach as
that for sinusoidal quantities we can write:
P
PF = (9.58)
S
Therefore, substituting in the definitions into this expression we can write:
Vs Is1 cos φ1 Is1
PF = = cos φ1 (9.59)
Vs Is Is
Remark 9.7 From (9.59) one can see that with a non-sinusoidal current source
that the sinusoidal power factor is modified by the term Is1 /Is – i.e. the fun-
damental current rms value divided by the total current rms value. Therefore,
as the harmonics increase, the rms value of the current will increase, but the
fundamental will not. Therefore the power factor will decrease.
The normal power factor expression is given a new name in this context – it
is called the displacement power factor (DPF):
DPF = cos φ1 (9.60)
Therefore the power factor with the non-sinusoidal current is:
Is1
PF = DPF (9.61)
Is
Using (9.21) it is possible to write the power in terms of the total harmonic
distortion:
1
PF = DPF (9.62)
1 + THD2i
v diode
+ - i
+
vs vd R
-
v s , vd v diode
i
i, vd v s , v diode
v diode + vL - iL
+ -
L
+ +
vs R v out
- -
the current continues to flow even when the source voltage has gone negative.
When the energy stored in the inductor reaches zero then the current stops
flowing. If the resistor value is made smaller then the current will flow further
into the negative half cycle. If the resistance was zero then the current would
continue to flow for the whole of the negative half cycle.
Let us analyse the situation in Figure 9.6. At t = 0 then the diode becomes
forward biased and current begins to flow. Assuming an ideal diode then the
318 Line Frequency Uncontrolled Rectifiers
t1 t2 t3
0.8
0.6
iL
0.4
(A)
0.2
0.0
-0.2
Due to simulation numerics
60.0 vs v out
vL
40.0
20.0
Area A
(V)
0.0
Area B
-20.0
-40.0
v diode
-60.0
0.0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
t(s)
Figure 9.6: Plots for a half wave rectifier with an LR load – L = 200mH and
R = 50Ω.
9.3 The Half Wave Rectifier Circuit 319
v diode - + vL - iL
+
L
+
+
vs Ed
-
-
Figure 9.7: Half wave rectifier circuit with an inductor and back emf.
One can see the difference in the performance of the circuit from the Saber
simulation plots shown in Figure 9.8.
320 Line Frequency Uncontrolled Rectifiers
t1 t2 t3
20.0
0.0 v diode
-20.0
(V)
-40.0
-60.0
-80.0
-100.0
0.2
iL
(A)
0.0
-0.2
60.0
40.0
20.0
(V)
0.0
-20.0
vL
-40.0 Ed vs
Area A Area B
-60.0
0.0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
t(s)
Figure 9.8: Plots for a half wave rectifier with an inductor and back emf as a
load.
One can see from Figure 9.8 that the inductor current iL has much the
same shape as that shown in the Figure 9.6, but the magnitude of the current
in smaller. This is an obvious result, since the voltage that can increase the
current through the inductor is much smaller in this case because of the Ed
voltage. In addition the time for the current to build up is also smaller. The
other notable difference between this case in that of Figure 9.6 is that the diode
reverse voltage is substantially larger in this case.
vL D1
+ -
Ls
is
+
vs vD D2 vd Id
1
v s , vd
is
vd
Waveforms with Ls = 0
i D1
+ vL - D1
Ls
+
vs is Id vd = 0
D2 Id
-
i D2
is = I d
+ vL = 0 - D1
Ls
+
vs is D2 Id vd = v s
-
Let us analyse this situation as little more closely. Consider the situation
when the input voltage vs initially becomes greater than zero. The voltage on
the load side of the inductor is zero because D2 is on. Therefore the current
across the inductor is:
√ dis
vL = 2Vs sin ωt = Ls 0 < t < tc (9.67)
dt
√ tc Id
2Vs sin ωt dt = Ls dis (9.68)
0 0
which becomes:
√
Aθc = 2Vs (1 − cos ωtc ) = ωLs Id (9.69)
ωLs Id
cos θc = 1 − √ (9.70)
2Vs
Remark 9.10 Another interesting effect of the commutation is that the aver-
age voltage produced at the output of the circuit is lower due to commutation
notches. These “notches” result in sections of vs not appearing at the output. commutation
notches
Waveforms for the commutation of the current are shown in Figure 9.11.
These waveforms are the outputs of a Saber simulation. These plots clearly
show the commutation notches in the output voltage, vd . The commutation
notches appear as the voltage across the Ls inductor. The area of these com-
mutation notches, where the horizontal axis is θ = ωt, was evaluated in the
expression (9.69). The plots of Figure 9.11, however, are on the time axis.
Therefore, under this condition it can be shown that the expression for the area
under the inductor notch is Ls Id (the ω term is omitted). Examination of the
notch integral plot of Figure 9.11 shows that the area is 0.0050081 – in other
words Ls , which it should be since Id = 1.
It is clear from Figure 9.11 that the commutation notches lower the output
voltage. We can calculate voltage loss analytically. Firstly we can calculate the
average output voltage as follows:
√
1 π √ 2 2
Vd0 = 2Vs sin ωt d(ωt) = Vs = 0.45Vs (9.71)
2π 0 2π
In the case where one has commutation notches then the average voltage
can be calculated as:
π√
1
Vd = 2Vs sin ωt d(ωt) (9.72)
2π θc
This expression can be rewritten as the average voltage with Ls = 0 minus the
324 Line Frequency Uncontrolled Rectifiers
(V*sec) : t(s)
0.006
Notch Area
0.004
(V*sec)
(0.020805, 0.0050081)
0.002
0.0
(V) : t(s)
20.0 Comm notches
(0.020007, 0.10216) vL
10.0
(V)
0.0
-20.0
(A) : t(s)
Inductor current
1.0 i L , is
(A)
0.5
0.0
(V) : t(s)
60.0
Output vd vs
40.0
20.0
(V)
0.0 vD
1
-20.0
-40.0
-60.0 Output vd
Figure 9.11: Plots of the currents in the test circuit of Figure 9.9 – vs = 50 sin ωt,
Ls = 5mH, Id = 1 Amp.
9.5 Practical Uncontrolled Single Phase Rectifiers 325
id
Ls Rs
+ is
+
vs Cd vd Rload
-
voltage (similarly to the waveforms for the circuit in Section 9.3.3), then we don’t
have to worry about the current commutation from one diode to another.
We shall generate the analytical equations for the circuit under these condi-
tions. We shall not solve the equations, as this is a little complicated, but the
solutions are obtainable. If there is current commutation in the circuit then the
solutions get a little more complicated.
Whilst the diodes are conducting the equivalent circuit is as shown in Fig-
ure 9.13. Applying KVL to this circuit we can write the following differential
equation:
did
vs = Rs id + Ls + vd (9.77)
dt
Similarly one can also apply KCL to the circuit to give:
dvd vd
id = Cd + (9.78)
dt Rload
Rearranging we can write the following matrix expressions when the diode is
conducting:
did
dt
−Rs
Ls − L1s id 1
Ls
= + vs (9.79)
dvd
dt
1
Cd − Cd R1load vd 0
Ls Rs id
+
+
vs Cd vd Rload
Figure 9.13: Equivalent circuit of the single phase rectifier when the diodes are
conducting.
During the time when the diodes are off (i.e. when the energy in Ls has
been expended and vs < vd ), the capacitor is discharging into the load resistor.
Therefore there is an exponential decay of the output voltage. The expression
for this time is (using KCL):
dvd vd
Cd + =0 (9.80)
dt Rload
dvd vd
⇒ =− (9.81)
dt Cd Rload
Remark 9.13 Using equations (9.79) and (9.81) one can solve for the complete
analytical solution for the currents and the voltages in this circuit.
9.5 Practical Uncontrolled Single Phase Rectifiers 327
We shall not attempt to solve (9.79) and (9.81), but instead we shall simulate
the circuit of Figure 9.12 using Saber . The plots in Figure 9.14 are the output
waveforms of this circuit. In particular notice the vert “spikey” current flowing
into the rectifier, and the ripples on the output voltage due to this, and the
discharge time when all the diodes are off and the output is disconnected from
the input.
(V) : t(s)
40.0 80.0
vd
(V)
40.0
0.0
20.0
-20.0 0.0
20.0
(V)
0.0
-20.0
-40.0
-60.0
Figure 9.14: Waveforms for the practical single phase rectifier circuit of Fig-
ure 9.12.
If one evaluates that harmonics on the current waveform the plot shown in
Figure 9.15 is obtained. One can see that the output voltage has a dominant
dc component (as it should) which has an amplitude of approximately 47 volts.
There is also a harmonic at 100Hz corresponding to the fundamental of the
ripple on the dc output voltage.
The main harmonic in the current is at 50Hz, but there are also significant
harmonics at 150, 250 and 350Hz as well (i.e. the 3rd, 5th and 7th harmonics).
One can treat each of the harmonics in the current as a phasor (as in (9.7)).
The amplitudes of the real and imaginary components of these phasors can be
found using the waveform analysis tools in Saber , and these are plotted in
Figure 9.16.
In Figure 9.16 one can see the amplitude of the fundamental real and imag-
inary harmonics – a1 = −0.40077 and −b1 = −4.6573.8 Therefore using the
8 In Saber the b coefficient is called the imaginary coefficient. It is the negative of the
actual b coefficient as appears in a normal Fourier series. Hence we have written the coefficient
328 Line Frequency Uncontrolled Rectifiers
Mag(A) : f(Hz)
6.0
is
4.0
Mag(A)
2.0
0.0
Mag(V) : f(Hz)
60.0
vd
40.0
Mag(V)
20.0
0.0
0.0 50.0 100.0 0.15k 0.2k 0.25k 0.3k 0.35k 0.4k 0.45k 0.5k 0.55k 0.6k 0.65k 0.7k
f(Hz)
Figure 9.15: Input current and output voltage harmonics in a single phase
rectifier.
9.5 Practical Uncontrolled Single Phase Rectifiers 329
0.0
Re(A)
(50.0, -0.40077)
-1.0
-2.0
Im(A) : f(Hz)
4.0
is
2.0
0.0
Im(A)
-2.0
-4.0
(50.0, -4.6573)
-6.0
0.0 50.0 100.0 0.15k 0.2k 0.25k 0.3k 0.35k 0.4k 0.45k 0.5k 0.55k 0.6k 0.65k 0.7k
f(Hz)
Figure 9.16: Real and imaginary components of the harmonic phasors for the
harmonics single phase rectifier harmonics plotted in Figure 9.14.
330 Line Frequency Uncontrolled Rectifiers
Comparison of (9.82) with the fundamental shown in Figure 9.15 indicates that
the value appears to be correct. The phase in (9.83) is the phase of a cos
waveform (which is the time domain representation of a phasor).
The harmonics in Figure 9.15 and Figure 9.16 were taken by looking at
the input current over two fundamental periods of the input voltage starting
at 120msec and ending at 180msec. This was done so that the rectifier was
operating in steady state, and the transients that can be seen in Figure 9.14
would not affect the harmonic analysis. This also means that the phase in
(9.83) is with respect to the voltage input waveform. Consequently we can use
the value in (9.83) to get the phase (and hence power factor) of the current
fundamental. Realising that the time domain form of the phasor is:
one can write the time domain expression for the fundamental current as:
Using the trigonometric identity cos(x) = sin(x + 90◦ ) then we can write:
Hence there is a phase shift of the fundamental from the input voltage of −4.92◦ .
Consequently, from (9.60) we can see that the DPF is:
Remark 9.14 From a fundamental current view point the power factor of the
system is very good. The presence of harmonics is the main contributor to poor
power factor.
as −b1 .
9.5 Practical Uncontrolled Single Phase Rectifiers 331
Remark 9.15 The value in (9.90) shows that the harmonic distortion of the
input current is quite high.
We can now also calculate the non-sinusoidal power factor using (9.59):
Is1
PF = cos φ1
Is
3.3054
= × 0.996
3.1076 + 3.3054
= 0.513 (9.91)
Remark 9.16 From (9.91) one can see that the power factor is very low. Com-
pare this to the DPF which is 0.996. Therefore the presence of the harmonics
in the input current waveform is a major contributor to the poor power factor
of this circuit.
Remark 9.17 Single phase full wave rectifiers such as depicted in Figure 9.12
are present in large numbers on the power supply grid (e.g. in computer power
supplies). Therefore the cumulative affect of this could result in a very poor
overall power factor. Techniques for improving the power factor of this rectifiers
are now being used.
This filter basically filters out the higher order harmonics in the input current.
The filter in the dc link needs a little explanation. Clearly it is also a low pass
filter, and appears to have the classic π structure. The choice of the size of
the components is important from another point of view. The capacitor Cd1 is
chosen to be small so that there is considerable ripple in the vd1 voltage. This
causes the current to flow in smoother fashion from the supply via the diodes.
The extra ripple in vd1 is then filtered via the low pass filter formed by Ld and
Cd . The Cd capacitor is much larger than Cd1 .
Ld
id
Lf 1 Lf 2
+ is
+ + +
vs Cf C d1 vd1 Cd Rload vd
-
Figure 9.17: Single phase rectifier with input and dc link filters.
Remark 9.18 The passive circuits have a limited capacity to smooth the input
current. The filtering achieved is capable of improving the power factor the
acceptable levels. However there are some shortcomings:
2. There is an obvious disadvantage in the cost of the filters, size, losses and
dependence of the output voltage on the load current drawn.
The limitations cited in Remark 9.18 have led to the investigation of active
current shaping techniques to improve the power factor of the rectifiers. These
techniques also have the advantage that they extend the range of operation of
the rectifier – i.e. the input voltage can vary but the output voltage will stay
constant. For any current shaping circuit to be of practical use it has to have
the following attributes:
• The current shaping circuit should be of low cost and small size.
• It should allow the rectifier to provide the correct voltages under over-
voltage as well as under-voltage conditions.
Remark 9.19 Note that the buck converter is in general not suitable for this
application because the input current is highly discontinuous. This is due to the
fact that the switch in the circuit disconnects the output of the diodes in the
rectifier from the input to the converter during normal operation.
Figure 9.18 shows the basic structure of a single phase rectifier with a boost
converter for current shaping.
Boost converter
Ld id i load
iL
Ls ic
Rs
+ is
+
vs vs Cd Rload vd (> v s )
-
Figure 9.18: Circuit for the a single phase rectifier with current wave shaping
boost converter.
As can be seen from Figure 9.18 the circuit is simply a conventional rectifier
followed by a conventional non-isolated boost converter. The boost converter
is usually controlled so that the output voltage is approximately 10% higher
than the nominal rated voltage of the rectifier. This allows the circuit to work
correctly if the supply is up to 10% higher than the nominal voltage. One
implicitly gets a circuit that can operate with low voltages because of the boost
converter. How low the voltage can go depends on the design of the boost
converter and the load current and voltage required.
The key to the operation of the unity power factor rectifier is the control of
the boost converter. Before considering the general principles of the control we
firstly need to clarify the requirements for the control. If we want unity power
334 Line Frequency Uncontrolled Rectifiers
factor, than we need a sinusoidal input current which is in phase with the input
voltage and does not have any significant harmonics. The desired waveforms
are shown in Figure 9.19(a) and (b). One can see that the waveforms in the
boost converter section of the circuit are sinusoidal in nature.
vs
is
wt
(a)
vs
iL
wt
(b)
Figure 9.19: Waveforms for a single phase rectifier with active current waveshap-
ing – (a) the input current and voltage; (b) the boost converter input voltage
and inductor current.
Remark 9.20 Examination of the waveforms in Figure 9.19 indicate that there
will be a ripple voltage on the output filter capacitor (as there is in the conven-
tional rectifier). The capacitor has to be designed to be large enough to keep this
ripple below acceptable limits.
Ignoring power losses in the boost converter we can apply some basic analysis
to
√ the circuit of Figure
√ 9.18 with the waveforms of Figure 9.19. Define Vˆs =
2Vs , and Iˆs = 2Is – i.e. Vs and Is are the rms values of the voltage and
the current. Clearly the instantaneous power flowing into the circuit is (using
sin2 x = 12 (1 − cos 2x)):
which is similar to (9.32), except that this was calculated for cos waveforms
with a θ phase difference between them.
9.5 Practical Uncontrolled Single Phase Rectifiers 335
If we assume that the output capacitor is large then the voltage ripple across
it will be minimal, and consequently the output power can be written as:
pd (t) = Vd id (9.93)
Assuming that the switching frequency is very high then the inductor can
be negligibly small. This allows one to use the simplifying assumption that on
an instantaneous basis that:
pin (t) = pd (t) (9.95)
and therefore we can write:
vs
e = Vd* -Vd ,measured
Switch
i L*
Vd*
PI ´ Current
mode
control
signal
Regulator
control
Vd,measured i L,measued
Figure 9.20: Block diagram of the control system for a single phase rectifier
with active current waveshaping.
implemented in a variety of ways (see Section 6.3.3.3), but the most common
technique is the “constant frequency with turn-on at clock time” controller.
With this control strategy the net result is that the sinusoidal reference
current amplitude is modulated by the output voltage error – the larger the
voltage error the larger the amplitude of the sinusoidal current pulse.
Some other points to note about this circuit:
1. A resistor in series with the Ld inductor is often used to limit the inrush
current at start-up. This resistor is usually shorted out by a SCR (large
voltage drop with this though), a relay or a MOSFET once the circuit
starts to operate normally.
2. A small filter capacitor is usually placed across the output of the diode
bridge to prevent the switching noise from entering the grid supply.
3. The output filter capacitor only has to be about half the size of that in an
uncontrolled rectifier, for the same ripple. Therefore the active rectifier
circuit saves on weight and space.
to affect the supply voltage seen by other devices connected to the grid supply.
The voltage across other equipment at the PCC is:
Point of common coupling (PCC)
id
Ls2 Ls1 Rs
+ is
vs +
v PCC Cd vd Rload
Other equipment
connected to the
supply
Figure 9.21: Single phase rectifier showing the point of common coupling.
dis1
vP CC = vs − Ls1 (9.101)
dt
where vs is assumed to be an ideal sinusoidal voltage source.
The current is1 contains the harmonic currents of the single phase rectifier
(as well as the harmonics drawn by the other equipment). These harmonics will
cause a voltage drop across the Ls1 inductance. This drop can be considerable,
since the impedance of an inductor increases with increased frequency.
One can break the current into a sinusoidal component and the distorted
components as follows:
! dish
dis1
vP CC = vs − Ls1 − Ls1 (9.102)
dt dt
h=1
D1 C1
vd
Double
D2 pos
C2
vac
If the switch is closed then on a positive half cycle of the input voltage
current flows via D1 , capacitor C1 , and the switch back to the supply. On the
negative half cycle the current flow via the switch, capacitor C2 and diode D2
back to the supply. The result is that the two capacitors have the peak supply
voltage across them, and their voltages sum. If the switch is open, then the
circuit behaves as conventional bridge rectifier.
∞
!
ia = ia1 + iah (9.105)
h=2k+1
∞
!
√ √
= 2Is1 sin(ω1 t − φ1 ) + 2Ish sin(ωh t − φh ) (9.106)
h=2k+1
In a similar manner to (9.106) one can write the other currents in the phases
9.5 Practical Uncontrolled Single Phase Rectifiers 339
ia
ib
a
b
n
ic
in
in = ia + ib + ic (9.109)
If one substitutes (9.106), (9.107) and (9.108) into (9.109) then all the non-
triplen and fundamental harmonics add to be zero. The triplen harmonics on
the other hand add to give:
∞
! √
in = 3 2Ish sin(ωh − φh ) (9.110)
h=3(2k−1)
Therefore the third harmonics add together in the neutral, and the neutral
current therefore becomes:
In = 3Is3 (9.112)
The third harmonic current in the lines can be quite significant with single phase
rectifier loads, and consequently the neutral current can be large. In fact under
conditions
√ of highly non-linear loads, the neutral current can be as much as
3Iline . Therefore, the neutral should be a conductor that can at least carry as
much as the lines.
id
D1 D3 D5
a Ls
+
ia
b Ls
+ +
n Cd Rload vd
c ib
Ls
+
ic
D4 D6 D2
Figure 9.24: Basic three phase, six pulse, full wave rectifier circuit.
Graph0
(A) : t(s)
5.0 i(v_sin.phase_c)
(A)
0.0
-5.0
(A) : t(s)
5.0 i(v_sin.phase_b)
(A)
0.0
-5.0
(A) : t(s)
5.0 i(v_sin.phase_a)
(A)
0.0
-5.0
(V) : t(s)
400.0
v(v_sin.phase_a)
200.0
(V)
0.0 v(v_sin.phase_b)
-200.0
-400.0 v(v_sin.phase_c)
(V) : t(s)
600.0 output_voltage
400.0
(V)
200.0
0.0
0.0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
t(s)
Figure 9.25: Waveforms of a three phase rectifier with a constant current source
load.
342 Line Frequency Uncontrolled Rectifiers
Introduction to Other
Power Electronic Devices
and Applications
10.1 Introduction
This chapter briefly introduces several other high power, power electronic switch-
ing devices and applications that are industrially important. The presentation
here is brief and introductory in nature, and by no means comprehensive. It
is intended to introduce the student to other power electronic circuits, hith-
erto not considered, and some of their applications. The applications chosen
are, hopefully, those that are interesting to the readers. Thnose who wish to
research into any of the circuits and applications presented are encouraged to
follow up the topics in the references.
The remainder of this chapter will consider the following:
• Matrix converters
Rectifier mode
P
AC CONVERTER DC
P
Inverter mode
Figure 10.1: Definition of rectifier and inverter modes of operation [4].
Energy
Storage
Element
Many power electronic systems have the configuration shown in Figure 10.2.
Converter 1 transforms the input to DC. There is a storage element that is
able to accept the energy. Converter 2 then converters to DC to the desired
output. The energy storage element is typically a capacitor or inductor. Its
presence means that the instantaneous input power does not have to equal to
instantaneous output power, thereby providing a degree of decoupling of the
input from the output, and allowing a degree of independence in the control
and operation of the two converters.
Figure 10.3 shows a less abstract version of Figure 10.2 for one form of an
10.2 Inverters and Applications 345
DC link
AC + AC AC
Converter 1 Converter 2
Motor
Utility
AC drive system. Notice that in this particular case to energy storage element is
a capacitor. Both the input and the output is AC. Therefore, in this application
there is inherently an inversion process, since one way or another power must
go from the DC to AC side.
In many actual implementations of Figure 10.3 Converter 1 is a rectifier, and
Converter 2 is an inverter. This means that power can only flow from the utility
to the motor, and not in the reverse direction since the rectifier cannot transfer
power back to the utility. Depending on the details of the implementation of
Converter 2, it is possible that it can act as a rectifier, and power can from the
motor (which is now acting as a generator, the mode being called regeneration)
back to the DC link. In this case the capacitor can accept the energy, but
one must be careful to ensure that not too much energy is transferred, else the
capacitor will experience over-voltage and be destroyed.
If a motor is going to be regenerating for a significant percentage of time
during operation, then both Converter 1 and Converter 2 need to be able to
act as both a rectifier and an inverter. If this is the situation then regenerated
energy can be transferred back to the utility supply, and the capacitor voltage
can be controlled to remain within bounds.
Artificial ground
DC link
R 3 phase AC load
vag
Z
a
+
DC b
g Z n Z
c
vbg vcg
DC link
Modulator
+
Z
Reference waveform
Carrier waveform
Approximate
fundamental
A notation that we shall use is that the leg switching states are represented
by a binary value – a ‘1’ denotes that the top switch of a leg is closed, and the
bottom switch is open, and a ‘0’ denotes that the top switch is open and the
bottom switch is closed. Therefore, the possible switching combinations, with
the phase leg voltages with respect to the mid link ground point (denoted as
“g”), and the line-to-line voltages across a three phase load (such as that in
Figure 10.4) are shown in Table 10.1.
Table 10.1: Switching combinations and associated phase and line-to-line volt-
ages.
Remark 10.3 Note from Table 10.1 that the line-to-line voltages always add
together to be zero (similar to line-to-line voltages in a sinusoidal three phase
system).
Remark 10.4 Note also from Table 10.1 that two of the switching states lead
to zero line-to-line voltages. These two states correspond to all the top switches
on, or all the bottom switches on. These switching combinations lead to a short
circuit across the three phases.
The phase voltages – i.e. van , vbn , vcn are also of interest. Let us consider
switching state 001 as an example. In this case we have:
One can immediately see from (10.1) that van = vbn . However, these equa-
tions are not independent, and therefore one cannot solve for the phase voltages.
If one considers the three phase load to be a passive one of the form shown
in Figure 10.4, then one can write, unisng Kirchoff’s voltage law, the following
expressions:
va = ia Z + vn (10.4)
vb = ib Z + vn (10.5)
vc = ic Z + vn (10.6)
Remark 10.5 Adding together equations (10.11),(10.12) and (10.13) one gets:
2 1 1
van + vbn + vcn = (vag + vbg + vcg ) − (vag + vbg + vcg ) − (vag + vbg + vcg )
3 3 3
(10.14)
∴ van + vbn + vcn = 0 (10.15)
Therefore the phase voltages always add to be zero, regardless of the applied
voltages, when the three phase load is passive. It can be shown that this also
applies if there are three phase sinusoidal voltage sources in the load as well.
Remark 10.6 The neutral voltage of the three phase load moves around relative
to the ground at the mid point of the DC link. Consider the extreme cases of
switching patterns 000 and 111. For 000, using (10.10) and substituting for the
voltages from Table 10.2 one can see that vn = − 12 VDC . Similarly for the case
of 111 we get vn = 12 VDC . Therefore the neutral voltage has moved around by
VDC . These large voltage excursions in the neutral can cause bearing currents
to flow when electrical machines are the load on the inverter.
350 Introduction to Other Power Electronic Devices and Applications
Remark 10.7 It can be shown that if we have three phase sinusoidally spatially
distributed windings, fed with three phase temporal sinusoidal currents, then
one ends up with a spatially sinusoidally distributed resultant mmf that moves
around the machine at the electrical supply frequency. This can be represented
as a single vector that is rotating with an angular velocity of ω (the electrical
supply frequency).
C B A
va
V dc vb
vc
V 3 (010) (110) V 2
2 A B C
3 V7 1
V 4 (011) (111) (100) V 1
(000)
4 V8 6
5
V 5 (001) (101) V 6
Figure 10.6: Switch positions and the resultant voltage space vectors.
The reason for introducing the space vector concept here is because it is
convenient to use this concept to represent the output voltages for an inverter.
Figure 10.6 shows the space vector diagram for the various switch positions
for the inverter. The length of the space vector corresponds to the maximum
10.2 Inverters and Applications 351
phase-to-neutral voltage for each phase – i.e. 23 VDC . Notice that there are six
active vectors that can be spaced around a machine every 60◦ electrical.
Remark 10.8 Although the space vector concept comes about because of the
spatial properties of machine windings, it is often used in situations where this
does not exist. For example, in Figure 10.3 we have a passive load consisting of
impedances, and we can use the space vector concept to represent the voltages
on this circuit. I will not, in this brief introduction, go into detail as to why this
can be done, suffice to say that it is due to the very close relationship between
space vectors and temporal phasors in circuits.
Space vectors can be used as a basis for a different type of PWM, called
Space Vector PWM (SVPWM). The basis of this PWM strategy is the realisa-
tion that three phase temporal sinusoidal voltages lead to a spatially rotating
voltage vector in a three phase sinusoidally wound machine (as noted previ-
ously). However, with an inverter we do not have infinitely variable voltages
that we can apply to each phase, and therefore we can switch the inverter so that
at any instant of time we can, in an average sense, produce a desired voltage
vector.
T
T/2 T/2
10 1 1 1 1 1 1 0 A
0
10 0 0 0 B
0 1 1 1 1
10 0 0 1 1 0 0 0
0 C
t 0 t1 t2 t0 t0 t2 t1 t 0
Figure 10.7: Switching waveforms for double edge pulse width modulation.
In order to develop a PWM strategy using space vectors let us define α as the
duty cycle for a vector. Consider Figure 10.7 which shows the switching wave-
forms to generate a particular voltage vector. One can see from this diagram
that the same switching pattern is generated symmetrically around the centre of
the PWM period. By reading vertically one can determine the switching states
for this switching sequence – they are 000, 100, 110, 111, 111, 110, 100, 000 –
i.e. we are switching between vectors V8 , V1 , V2 , V7 , and then the reverse. The
vector nomenclature appears in Figure 10.6. As one can imagine this would
lead to an average vector somewhere in between V1 and V2 , the length of the
vector being controlled by the duration of the zero vectors V7 and V8 . The duty
cycle for each of the vectors is simply the total time of the vector divided by
the control period time T . For example, the duty cycle for the V1 vector is:
352 Introduction to Other Power Electronic Devices and Applications
2t1
α1 = (10.16)
T
Similary one can defined the duty cycle for V2 . Using this notation, if only
this vector and the zero vector was switched during an interval of T then the
average voltage vector magnitude produced over the interval is α1 VDC volts.
Note 10.1 Space vectors are defined (for reasons that I shall not elaborate on
here) as 23 the amplitude of the resultant vector in the machine. For a three
phase machine this means that the maximum voltage vector magnitude is the
same as the peak voltage that occurs across the phases. It is this correspondence
of the voltage vectors with the phase voltages that is one of the main reasons for
using this convention.
Remark 10.9 A further comment on note 10.1 – one can resolve the space
vector onto three axes 120◦ apart and get the instantaneous value of the voltage
on the respective three phase axes. The same logic applies to the current vector.
q
V2
Desired voltage
vector
1
aq
2t 2
60 o d
ad V1
2t 1
One of the very convenient features of vectors is that one can take orthogonal
components of them – i.e. one can not only resolve the vectors onto the 120◦
axes but one can also resolve them onto 90◦ axes.
Consider the situation depicted in Figure 10.8. This shows a desired voltage
vector. Note that we have not considered what limits there are on the length
of the voltage vector that can be produced by this system. We do know that
the limit if the voltage vector lies on one of the natural vectors that can be
produced by the inverter is 23 VDC .
One can consider the vector in Figure 10.8 is a normalised vector (i.e. divided
by 23 VDC ), and hence αd and αq are the normalised orthogonal projections onto
10.2 Inverters and Applications 353
a set of orthogonal dq axes. If we apply vector V1 for 2t1 seconds, and V2 for 2t2
seconds then the desired normalised vector, in an average sense, is obtained.
It is possible to show, from the geometry of this situation, that for a given set
of normalised orthongal vectors αd and αq the switching times for the vectors
in sector 1 of the PWM star are:
T αq
t1 = (αd − √ ) (10.17)
2 3
αq T
t2 = √ (10.18)
3
T αq
t0 = (1 − αd − √ ) (10.19)
4 3
where the various t values are defined in Figure 10.7. If a similar analysis is
carried out for all the sectors then one can get a complete set of switching times
as shown in Table 10.3.
Another important aspect that was eluded to earlier was that there is limiting
of the resultant space vectors. For example, one cannot ask for αd = 1 and
αq = 1, since this would be asking for a resultant space vector that is larger than
that which can be obtained given the vectors that the inverter can produce. If
one applies the expressions from Table 10.3 to such a situation then this problem
manifests itself by the condition [21]:
2t1 2t2
+ >1 (10.20)
T T
or:
αq
αd + √ > 1 (10.21)
3
in the case of sector 1 limiting. Clearly (10.20) means that the total switching
time of the active vectors exceeds the total control period.
It can be shown that the limitations imposed by the available firing times
result in a hexagon limit. This is shown in Figure 10.9. If a desired vector
exceeds the limit hexagon, then it has to be limited to the hexagon [21].
If the times are to be scaled so that they add to give one, then we require:
2t1 2t2
γ + =1 (10.22)
T T
or:
1
γ= α (10.23)
αd + √q
3
354 Introduction to Other Power Electronic Devices and Applications
Limit hexagon
Limit circle
V3 V
(010) (110)2
2
3 V7 1
V4 (011) (111) (100)V
(000) 1
4 V8 6
5
(001) (101)
V5 V6
Figure 10.9: Voltage limit hexagon.
Remark 10.10 Note that the use of the γ on both the total times means that
the angle of the resultant vector is preserved.
The new limited firing times for sector 1 are now:
2t1lim = 2t1 γ (10.24)
2t2lim = 2t2 γ (10.25)
The 1/γ values for all the sectors are summarised in Table 10.4.
Remark 10.11 Space vector based PWM is particular amenable to implemen-
tation in digital form. This can be contrasted with carrier wave based PWM,
which was originally devised for analogue implementation. Of particular impor-
tance is that this technique does not involve the solution of any transcendental
equations, and it does not involve the use of any trigonometric functions.
Sector 1/γ
α
1 αd + √q3
2αq
2 √
3
α
3 √q− αd
3
α
4 −(αd + √q3 )
2α
5 − √3q
α
6 αd − √q3
Remark 10.12 Another interesting feature of space vector PWM is that the
maximum amplitude of the fundamental that can be produced by the technique
is larger, by approximately 15%, than that produced by carrier based sinusoidal
PWM. A similar effect can be obtained in sinusoidaly PWM by putting a third
harmonic in the reference waveform.
Remark 10.13 The “shoot through” problem also exists in low power digital
circuits. One may recall from Chapter 1 that CMOS and TTL both suffer from
“shoot through”. In the case of digital systems the shoot through is a very short
period of time, and the power levels involved are low. Consequently the problem
can be tolerated. However, in high power inverter systems the devices will fail
if “shoot through” occurs.
Shoot through is overcome by making sure that the outgoing device is turned
off before the incoming device turns on. This is achieved in practice by manip-
ulating the device signals that turn the devices on and off.
Phase A Phase B Phase C
Leg Leg Leg
+ Initial current
Final current
ib
ia i i
Three
DC
Bus
Input/Output
ia f
ib
f
} Phase
Input/Output
Figure 10.10: Inverter showing the initial and final current flow after a leg is
fired.
On
{
Top
Off
Leg A
switching On
Bot
Off
Dead - time Td
{
Top and actual switching point
0
Leg A
currents
ia f = ia i
Bot
0
On
{
Top
Off
Leg B
switching On
Bot
Off
Dead - time Td
Actual switching point
{
0
Top
ib
i
Leg B
currents
0
Bot i = i
b b
f i
depending on the direction of the current through the inverter leg. The follow-
ing discussion is with reference to Figures 10.10 and 10.11. Figure 10.10 shows
two legs of an IGBT based inverter, with the current flowing out of leg A and
into leg B. Figure 10.11 shows the effects of the current direction on the actual
time of switching. As can be seen when current flows out of a leg (i.e. leg A) the
actual time of switching is the desired time of switching. Therefore the dead-
time of the inverter does not cause a problem. However, when current is flowing
into a leg (i.e. leg B) then the switching time is delayed by the dead-time.
Therefore, if one wishes to compensate for the dead-time so that correct
switching always occurs, one should sense the current direction and compensate
the switching time as appropriate. However, because the compensation of the
switching time has to occur in the control interval before the interval it is going
to be applied, then there is the possibility that the current direction may be
incorrect. This situation only occurs around the times that the fundamental
current is about to change direction. The result of incorrect compensation is
that the cross-over of the current through zero may be considerably distorted –
even more than if compensation is not being applied. This issue has not been
resolved.
Controller
DC AC
Photo-voltaic Utility
solar cells Inverter
supply
Domestic
load
Appendices
Appendix A
The supplementary course materials for the course for 2003, which are issued
as separate documents, are:
These materials are handed out in class. They are also available from the
following website:
http://www.eecs.newcastle.edu.au/users/staff/reb
364 List of Course Materials
Appendix B
Course Outline
B.1 Text
These notes written by the Lecturer. Further information and clarification of
issues presented in the course can be found in the references listed in the Bibli-
ography at the end of these notes.
B.2 Introduction
This subject covers a wide variety of issues related to switching in electronic sys-
tems. The issues range from switching in digital systems to switching in switch
mode power supplies and high power converters. The emphasis throughout the
course will be on practical design related issues.
The switching in digital systems will consider issues such as: logic families
and their interfacing, signal propagation in digital systems, transmission lines
and digital systems, cross talk mechanisms, printed circuit board issues, inter-
board cabling and measurement techniques.
The switch mode power supply section of the course will consider the stan-
dard buck and boost switch mode configurations, and various combinations of
these types. The presentation will necessarily be brief, but where possible rel-
evant practical issues will be highlighted. Practical design issues will also be
considered.1
The final section of the course is on high power line commutated converters
and hard switched inverters. This section will begin with an introduction to the
semiconductor devices used at these power levels, since these dictate the types of
applications for this equipment. The basic operation principles of single phase
and three phase converters will be presented. There will be a brief introduction
to the concepts power factor and harmonic control in rectifier circuits. Some
other power electronic devices and their applications will be introduced.
1 Due to time considerations, the chapter on the practical design of switch mode power
5. Establish the basic principles behind good ground plane design for printed
circuit boards.
10. Very basic understanding of the control strategies for switch mode power
supplies.
Assessment
The subject will have two assignment/labs worth a total of 40% of the final mark.
There is a mid semester quiz worth 10%. The examination at the end of the
semester contributes the remaining 50% to the final mark. The assignments are
intended to be done individually, although discussion of concepts and approaches
with colleagues is permissible. Assignments that are copied will be given zero.
B.4 Plagiarism 367
B.4 Plagiarism
A student plagiarises if he or she gives the impression that the ideas, words or
work of another person are the ideas, words or work of the student2 .
Plagiarism includes:
• copying any material from books, journals study notes or tapes, the web,
the work of other students, or any other source without indicating this
by quotation marks or by indentation, italics or spacing and without ac-
knowledging that source by footnote or citation;
• rephrasing ideas from books, journals, study notes or tapes, the web, the
work of other students, or any other source without acknowledging the
source of those ideas by footnotes or citations; or
• unauthorised collaboration with other students that goes beyond the dis-
cussion of general strategies or other general advice.
Plagiarism is not only related to written works, but also to material such as
data, images, music, formulae, websites and computer programs.
Aiding another student to plagiarise is also a violation of the Plagiarism
Policy and may invoke a penalty.
For further information on the University policy on plagiarism, please re-
fer to http://www.newcastle.edu.au/policy/academic/general/academic-
integrity policy new.html
Course Schedule
D.1 Introduction
Saber1 is a software simulation program. Its main attribute is that it allows
the simulation of mixed mode systems – i.e. one can have continuous time
analogue circuitry, digital circuits, continuous and discrete time transfer func-
tions, magnetic systems (such as electrical machines and magnetic actuators),
mechanical systems, and hydraulic systems all in the same simulation. This is
unusual since most simulation packages cannot readily handle this mix of sys-
tems. They tend to be more specialised – i.e. only for electronic circuits, only
for power systems, digital simulation packages etc.
Simulation packages are very useful for the simulation of electronic systems,
since the models of electronic components behave nearly the same as the actual
component. In some circumstances simulation is almost mandatory, since a
poor design can result in immediate catastrophic failure of the real circuit. An
example where this is often true is in the area of power electronics.
The Saber simulator consists of four major components:
• SaberSketch: This provides a means to graphically enter a schematic to
be simulated.
• SaberGuide: To some degree this component is hidden, since it provides
the connection between SaberSketch and the Saber Simulator.
• Simulator: This module is the actual simulation engine. It is activated
via SaberGuide.
• SaberScope: This is the back end postprocessing section of the Saber
system. SaberScope allows the user to process the files produce by the
Saber simulator and produce new files of results, but more importantly it
allows the user to generate graphs of the results.
In this introductory exercise we shall be using the Saber simulator for circuit
simulation. The circuit to be simulated is a very simple one, but it is able to
1 Saber is a registered trademark for Avant!
372 Introductory Exercise using Saber Simulator
vd
i
vL
L
vS
R vR
Saber ground
node
Figure D.1: Simple single phase, half wave rectifier, with an LR load.
{
Zooming
controls Select to
draw a line
Grid
control
Invoke SaberGuide
Parts
menu
Place parts on the schematic: The next step is to place the desired com-
ponents on the blank schematic. The is achieved using the Parts Gallery
button. When clicked-on this opens up another window which allows one
to select the parts folder to be used. The folder that you will use for this
exercise is the Analogy Parts Library. If one double-left-clicks on this then
the contents of the Available Categories window will change to a selection
of component categories. One can select a category, eventually ending
up with a listing of individual parts in the Available Parts list scroll win-
dow. An example of this window is shown in Figure D.3, which shows the
content of the Inductors & Coupling component category.
To place a component in the schematic one selects a particular component
from the Available Parts window and then click-on Place. The component
will then appear in the middle of the schematic window. An alternative
is to left-click-on the part and then go the to schematic window and click
the middle mouse button (if there is one).3
One can also access the Parts Gallery via using the right mouse button
selecting Get Parts→Parts Gallery, or from the Schematics main menu.
As a specific example, if we want to place a diode on the schematic
3 Only works if a mouse driver that recognises the middle mouse button is installed.
374 Introductory Exercise using Saber Simulator
Set a parts properties: Once a part is on the schematic then its properties
can be set. This is carried out by double-left-clicking on the part (one can
also get the properties of the part by right clicking and then selecting the
Symbol Properties on the drop-down menu). One can also obtain help on
a part by selecting the Help drop-down menu from the properties screen.
The Help explains the meaning and range of values for all the properties
listed for the part.
The properties window contains three columns – Property Name, Property
Value and a set of round buttons on the right that denote the visibility of
the property on the schematic. The latter two of these can be altered by
the user. The Property Value fields can contain undef, or *req*. The undef
field usually means means that the value is undefined, but the part will
execute correctly with some underlying default value. However, in many
cases this does not make sense. For example the resistor component has
undef for its value, and clearly one would wish to set the value of a resistor
in a particular circuit. If an undef value has to be defined the simulator
will let you know when you try to run the simulation. The *req* field
D.2 Circuit Schematic Capture 375
Wires: We have already mentioned how to draw wires on the schematic. One
can also select a wire and delete it by pressing delete on the keyboard, or
right clicking and selecting Delete Wire on the drop-down menu. One can
also alter the properties of a wire by right-clicking on the selected wire
and selecting Attributes... on the drop-down menu (see Figure D.4 for an
example of the Attributes... window). For example, one can change the
name of a wire in the Name field in the window, and then select whether
this name should be displayed on the schematic (which is often very handy
for documentation reasons).
Repeat the above steps until the complete circuit shown in Figure D.1 has
been drawn. At this point we are now ready to start the simulation phase of
the exercise.
4 A part can be copied by selecting the component and then moving the cursor to the
place where one wishes to have the duplicate component, and then clicking the middle mouse
button.
376 Introductory Exercise using Saber Simulator
In order to carry out the simulation of a design one now has to invoke the
simulator. This is achieved by pressing the SaberGuide button (see Figure D.2).
One then gets the screen shown in Figure D.5. Note the new toolbar at the top
of the screen. This toolbar allows one to control the Saber simulator from the
SaberSketch window.
The main tool used in SaberGuide is the DC/Transient button shown in
Figure D.5. If one clicks on this button then the window shown in Figure D.6
appears. The parameters circled should be filled out so that the end time and
time step of the simulation are set-up, and the simulator will automatically open
SaberScope upon the completion of the simulation. One can see that there are
a number of other tabs on the window. In more sophisticated simulations some
of these may have to be used. The only other one that we shall look at in this
simulation is the Input Output tab, which is shown in Figure D.7. The circled
quantities have been altered from the default values. These alterations cause to
simulator to save all the signals in the design, and all types of variables (across
variables (i.e. voltages) and through variables (i.e. currents)).
Remark D.1 One can also select specific signals for the simulator to save. This
is essential in large simulations otherwise the output files produced by the simu-
lator are huge. The signals can be selected using the Browse Design... selection
from the Input Output→Signal List→Select sub-menu. Note that the simulator
has to be running to carry out this function, therefore it is necessary to start a
simulation and stop it (using the Stop button), and then reenter this menu to
carry out this function.
Once all this information has been filled out then one simply clicks OK at the
bottom of the window and the simulation will begin. It firstly netlists the design,
and if this is successfully completed it will work out the dc starting condition,
and then finally start the transient analysis. A rotating icon in the top right
corner of the Saber window indicates that the simulator is running. When it
finishes, which is very fast in the case of this simulation, the simulator will
automatically open up SaberScope to allow the results of the simulation to be
post-processed.
D.4 Plotting and Processing Results 377
Remark D.2 From Figure D.9 one can see the advantage of naming signals
with meaningful names, as opposed to the default names given to the signals by
Saber. The default names in the signal list window do not make much sense.
When one is scanning through the signal list for complex designs, it is much
easier to find the signals/components of interest if the names make sense.
If one wishes to plot a number of variables, then left-click the desired sig-
nals holding down the Ctrl key on the keyboard, and then left-click Plot. The
selected signals will all be plotted on separate axes. One can also superimpose
several plots on the one set of axes. This can be achieved in two different ways,
378 Introductory Exercise using Saber Simulator
DC and transient
analysis button
Figure D.5: An example of SaberSketch with the Saber guide toolbar activated.
dependent on whether one has already plotted the signals on separate axes. If
one wishes to plot two signals on the same axis then select one of the signals
and plot it, and then select the other, and go the the plot window and press the
centre mouse button over the graph upon which one wishes the second signal
to be plotted.
The other way of plotting two or more signals on the same axis, is to firstly
plot the signals on separate axes, and then use the Stack Region feature. This
is activate by selecting one of the signals to be “stacked” on the same axis (this
is achieved by placing the mouse cursor over the signal name to the right of
the plot – the plot will go red, and then left-click), and then right-click and go
the drop-down sub-menu Stack Region. At the bottom of this flyout one can
see a number of Analog signals listed (the number dependent on the number
of signals plotted on the graph window), with Analog 0 being the one at the
bottom of the graph window. Select the analog signal number that corresponds
to the axis that one wishes to plot onto.
If one plots a signal and wants to delete it, then select the signal in the graph
window, and then right click to get the drop-down menu and select the Delete
Signal option.
Changed fields
Changed
variables
result then appears in the top window of the calculator. We can then plot this
result by left clicking the small graph icon at the extreme left of the calculator
toolbar.
In order to look at a waveform in more detail one can expand the horizontal
or vertical axis by simply selecting the axis by left-clicking, and then holding
down the button to extend a yellow bar along the region of the axis that one
wishes to expand. One can do this more precisely by right-clicking on the axis
of interest and then using the drop-down menu to carry out a more precise
numerical expansion of the axis (or alternatively go back to the original axis
scaling).
In addition to expanding the axes using the mouse cursor, one can also
zoom in on the waveforms by simply clicking the mouse over the section of the
waveform of interest, and then dragging out a square marque over the area.
This area will then be zoomed on the plot.
D.4 Plotting and Processing Results 381
All plotted curves have properties that can be altered. This is achieved by
selecting the plot of interest, and then right-clicking and selecting Attributes....
The contents of the resultant window are self explanatory.
The other major facility that is of use for processing plots is the measurement
tool. This is activate by left clicking the “Caliper” button at the bottom of the
SaberScope screen. This tool allows one to measure the precise absolute values of
the quantities on the screen, rise time of steps etc. There are too many features
to document here, so it is suggested that you have a look at the features, and
try them to see what happens.
3. Another tab in the Fourier window is the Input Output tab. Its contents
appear as the right window in Figure D.11. In this case I have set the
Signal List to be /... which means all signals, and the Include Signal Types
is set to all, meaning that through and across variables are to be included.
4. Finally we left click OK or Apply and the Fourier analysis is carried out
on the signals selected.
2. Measure the average and rms load current from the plots.
3. Measure the average voltage across the inductor, and try and explain the
result.
4. Measure the voltage across the diode. What is the maximum reverse
voltage it is subject to?
5. Plot graphs of the power dissipated in the load and the energy stored in
the inductor. Measure the average power dissipation.
6. Measure the ac source power, and compare this value with the value dis-
sipated in the load resistor. Why is there a discrepancy?
8. Replace the load resistor with a 300 volt dc source. Plot vS , i and vL . Note
that current only flows for part of the half cycle of the voltage supply. Note
where the peak current occurs.
9. Measure the average and rms values of the load current and voltage. Also
measure the average power transferred to the load. Note that the average
load power is now the product of the average current and average load
voltage.
10. Perform a frequency analysis of the load current and voltage, and compare
the results with the resistive load case.
If the above exercise is carried out successfully then you should have a good
preliminary working knowledge of the operation of the Saber simulation system.
There are many other aspects of the system that we have not considered – you
will need to know these for more sophisticated simulations.
Acknowledgment
This tutorial is partially based on a Saber tutorial written by Dr. B.J. Cook of
the Department of Electrical and Computer Engineering, University of Newcas-
tle, Australia.
Appendix E
Assignment 1
Introduction
This is a combined theoretical assignment and practical laboratory.
In planning the time, one needs to take into consideration the time consuming
nature of simulation studies, and the availability of the laboratory equipment.
The assignment section mainly involves carrying out simulations of various
PCB terminations in the Saber simulation package. Saber is available in the
PC laboratory on the top floor of building EE (i.e. EE107/108). Students
can also install and run the software at home. In order to run the software
reasonably one will need the following:
• At least 128Mb ram (this is the absolute mininum and the software will
only just run with this) – the more the better as Saber is very resource
hungry.
• At least 400 MB of disk space for the Saber installation. You will also
need approximatley 500MB of free space for swap on the disk.
• An internet connect via modem or ADSL so that the licence server can be
contacted to allow the software to run. Note that one must be connected
to the internet for the duration of the simulation session.
• The details of how to set up the environment variables so that the licencing
will work. These instructions should be included with the software.
If you don’t know how to use this package there is a demonstration exer-
cise in the course notes appendix which you can do at your own leisure. This
386 Assignment 1
exercise will introduce you to the features of the Saber package needed for the
assignment.
The laboratory section of the assignment is designed so that you can confirm
the results of the simulations using a special PCB that has appropriate traces
and terminations placed on it. There are only two sets of equipment available
for these labs1 , therefore the laboratory work will be carried out in an open
laboratory manner. This means that you can come in to the laboratory, at a
convenient time, and when the lab is open, and do the lab. It is quite OK for
several students to do the lab together, but the interpretation of the results
should be carried out individually.
The equipment is very expensive, so please be careful during your
experiments. Be particularly careful with the CRO probes, they are
not very robust!
Collaboration Policy
This assignment is meant to be an individual assignment. However, it is accept-
able for students to discuss the assignment in order to understand what is going
on. However, each student should produce their own individual report with the
simulation and experimental results, with their own interpretation of the effects
they observe.
I draw your attention to the copy of the institutional plagiarism policy in-
cluded in the course handout.
• Could you please put a heading on these titled “Explanation for Q??.??”,
highlighted, so that it is easy to located in the document.
• Could you please keep the answers short and to the point.
• Only include relevant plots.
If the above is followed then this assignment should not be too arduous.
Don’t get carried away with doing hours and hours of simulation – the simula-
tions required for the assignment should not take inordinate amounts of time to
complete.
quired.
E.2 Software Tools to Aid Report Production 387
the past its capabilities in relation to this have not always generated the results
one would desire (I have not checked the very latest version). Often the files
produced, especially Postscript files, are huge and very difficult to manage in a
word processing program.
In order to aid the inclusion of diagrams students can download some soft-
ware from my anonynous FTP server, at the following address in a Web browser:
ftp://eecsbobb.newcastle.edu.au
username: anonymous
password: put in your email address
Once logged on, navigate to the Useful files directory. There are a number
of files here, such as MWSnap, which is a very nice freeware screen capture
program2 , IrfanView (a freeware viewer that also allows conversion of files to
greyscale), Emacs (a public domain editor with LATEX aware mode), Miktex3
(a public domain version of the LATEX documentation system), Jpeg2ps (public
domain converter for Jpeg files to Postscript), and several text editors.
SaberScope produces by default colour plots. However, most students will
be printing out their reports on black and white printers, therefore it may be
advantageous to have the plots generated as black and white. This can be done
by accessing the Graph→Color Map→Mono menu item. The actual lines of the
plot will be converted to solid, dashed, dotted etc. lines. One can also right
click select a plot and change these line styles as desired.
Question 1
Consider a fibre glass PCB that has a track width of 0.01 inch (which is a fairly
typical). The permittivity of the FR4 board material is r = 4.5. The board
FR4 material is 0.063 inch thick (i.e. 1.6mm). The copper on the board is
1oz per inch2 , or 30µm thick. From these specifications calculate the L0 and
C0 per cm parameters for the line (hint the expressions in the Useful Formulae
Appendix in the notes are useful for this, and pay attention to the limitations
on physical dimensions for these expressions so that the right on is used).
The track is sitting on a ground plane PCB – this means that one can
consider that the ground return path has negligible inductance compared to
the track. Given these parameters construct a transmission line of length 30cm
using the Saber simulator. The line is being driven by a voltage source that
has a rise time of 800psec and a ∆V of 3 volts. Carry out the following virtual
experiments on this model of the transmission line:
a. Generate the time domain plot for the voltages on the line at the source,
load end several intermediate points along the line with the line terminated
2 This program allows one to capture any area of the screen and then save it to disk in a
as an open circuit, short circuit (use a small resistance value for this ≈
0.01Ω) and with its characteristic impedance. Explain the waveforms that
you observe.
c. Allow another track to branch off the transmission line from the middle
point. Initially make the two branch tracks the same length. Terminate
both tracks at the end with the characteristic impedance and generate
plots for the same points as in item a. Try different length branches for
the tracks. Explain what you see from heuristic and theoretical viewpoints.
How would you fix any problems observed?
d. Investigate the effects of a mid track capacitive load of 10pf on the per-
formance of the transmission line with a load characteristic impedance
termination. Explain your observations.
e. Design a RC load termination and simulate under the same input wave-
form conditions it to prove that it works correctly.
Hints
• Make sure that you choose the appropriate time scale for the plots you
generate. For example, for a transmission line of the type specified above
the propagation delay is of the order of 2nsec. Therefore, depending on
the question, time scales of 6 or 7 nsec in some instances, and between 12
and 15 nsec in others are appropriate.
Question 2
Consider the situation of two printed circuit board tracks on a PCB with the
same parameters as in Question 1. These tracks are located 0.02 inch (or
0.508mm) apart, so there is mutual capacitance and inductance between them.
One of the tracks is being driven with the same input signal as in Question 1,
with the driver modelled as a voltage source with 31Ω of output impedance
(i.e. similar to a TTL or CMOS output impedance). It is terminated with its
characteristic impedance. The other line is initially terminated at the near (i.e.
the end near the source of the driving line) and far ends with its characteristic
impedance.
Set up a Saber simulation to model this. Assume that the mutual capac-
itance is 0.1pF/cm, and the mutual inductance is 1nH/cm. For the following
simulation results try and use theory to explain the results where possible.
Carry out the following virtual experiments:
E.2 Software Tools to Aid Report Production 389
a. Initially set the mutual capacitance to zero and consider what happens
on the receiving PCB track at the terminations and mid points along the
line.
b. Repeat the above with the mutual inductance equal to zero and the ca-
pacitance equal to 0.1pF/cm.
c. Now carry out the same tests with the mutual inductance and capacitance
both present. Which of the two effects is dominant in the response?
d. The situation thus-far is artificial in that the receiving line is terminated
at both ends with the line characteristic impedance. Now replace the left
hand termination with a short circuit and then repeat item a. Explain the
results.
Laboratory
The laboratory experiments will be carried out using a PCB with a ground
plane, traces, and terminations place on it. The layout of the board is shown
in Figure E.1. You will note that the board uses BNC connectors to connect to
the CRO. These connectors connect to the measurement points using the “home
brew” probe technique discussed in class.
The objective of the lab is for you to see that the effects discussed in class,
and seen in the simulations, actually do occur in a real PCB trace. In addition,
comparison of the simulation and experimental results will allow an assessment
to be made as to the usefulness of simulation in understanding the issues in this
area.
The laboratory equipment is located at the rear of the communications lab-
oratory (EE104) on the top floor of building EE.
Laboratory Equipment
The following equipment should be available on the lab bench for you to carry
out the experimental studies:
• Switching Electronics Laboratory PCB (see Figure E.1 for layout).
• Agilent 81110A 165/330MHz Pulse/Pattern Generator, OR, Philips PM5776
1Hz–100MHz 1nsec risetime Pulse Generator, OR any other signal gener-
ator capable of producing a pulse rise time of 1nsec or less. Most of the
standard signal generators are not capable of doing this.
• HP 54542A 2Gs/sec 500MHz CRO, OR, Agilent 2Gs/sec 500MHz CRO,
OR other 500MHz 2Gs/sec CROs with file storage and mathematical
processing facilities. The oscilloscopes should have conventional 500MHz
probes. The later Agilent CROs are the easiest CROs to use.
• Three working 50Ω coaxial cables with standard size BNC connectors on
both ends.4
You will also need a 1.44MB floppy disk to store the plots from the CRO.
4 Note that sometimes the coaxial cables have faulty soldred connections, so check that
• The storage options will then come up on the screen. Select “Store image
enable”.
The auto-increment feature for the file name means that the default file name
will have a number added to it for each stored screen. If this is not selected
then the initial file will be overwritten.
To save a screen to the floppy disk, Press “Stop” to freeze the screen, and
then “Print”. A message should appear saying that the data is being saved to
a file.
One other task that you have to do is to integrate a waveform. This function
can be accessed from the “Math/FFT” button on the front panel of the HP
CRO.
If you are using another CRO then consult the manual to see how to carry
out the equivalent operations.
Preliminary Work
There is a little preliminary work to be done before doing the actual experiments.
Several resistors are shown in Figure E.1. Determine the values of the resistors.
In order to do this one must know what the resistors are to do:
5 Make sure that you have a floppy in the drive before doing any of this.
392 Assignment 1
• The first track has resistors RS1 and RT1 . These resistors have to be
selected to make the trace look like 50Ω from the signal generator coaxial
cable point of view, and the characteristic impedance of the line looking
from the trace side.
• The RT2 resistor is to match the 50Ω signal cable to the trace. There is no
requirement for matching from the trace back to the coaxial signal cable.
The Experiments
The experiments to be conducted on the PCB will mirror the simulation studies
carried out in Questions 1 and 2.
Carry out the following:
1. For the trace at the top of the PCB (i.e. the source terminated trace)
generate a plot for the source end, mid-point and end of line waveforms.
2. For Experiment d generate the end of line plot using the standard CRO
probe for the oscilloscope that it being used. There is a connection loop at
the load end of the line to allow this measurement. Explain the different
result from that obtained using the inbuilt “home brew” probe. A
3. For the second set of traces from the top of the board (i.e. the two traces
that are very close together) plot the voltages across the non-driven line
at the mid point and the end termination. Explain what you see and
compare the results to those obtained for the equivalent situation in the
simulation of Question 2. Were the parameters estimated in Question 2
close to the correct values.
4. The next experiment involves a trace with a branch off it – i.e. the third
trace from the top of the board. Plot the waveforms on the originating
trace prior to the branch, and at the end termination, and explain what
you see. How well do the experimental results correlate to the simulation
results.
5. The fourth trace from the top of the board has a 10pf capacitor on it to
simulate the input capacitance of a logic gate. Plot the waveforms before
the capacitor, and at the end termination and explain the observations.
How well do they conform to the same situation when simulated.
6. Using the set of resistor to the left hand side of the board (capacitively
coupled resistor circuit) and plot the coupling voltage waveforms. Work
out what the coupling current and mutual capacitance values are.
7. Using the right most resistor circuit (inductively coupled resistor circuit),
plot the coupling voltage. Calculate what the mutual inductance is be-
tween the two components is (account for the capacitance coupling that
will also be present in this case).
Appendix F
Assignment 2
F.1 Introduction
This assignment/lab is on switching regulators. We shall consider the following
switch mode converter structures:
Remark F.1 You should note that the transformer used in the kit is a stan-
dard pulse transformer and has four windings. Only three of the windings are
available to the user. The fourth winding is terminated with a resistor so that
any oscillations that occur due to the interaction of the leakage inductance and
the winding capacitance will be damped out (i.e. one can get underdamped LC
oscillations due to this interaction). If you are not using a winding you should
also terminate that winding with a resistor (don’t make it too small or too big –
394 Assignment 2
+12V 1 2
220W
BC327
1kW 1kW
0.01mF BC337
BC337
BC337
46V
1kW BC337 BC337
100W 1N4448 1kW 220W
2.2kW 2.2kW
0V
10k OSC
FB (feedback) PWM
1N914 10V
1N914
5k 4.7k
22k 10k 1k 10k
5k
1 16
2 15
2.2k
3 14
560 2.2k
4 13
9V LM3524
5 12 + + +
6 11 0.1mF
7 10 3 ´ 1000 mF 16V
8 9
1N914
1nF 50k
0.0047 mF
3.3k 4.7k 0.0047 mF
0.001mF
0V
several kΩ should be OK). The presence of the unused windings (even correctly
terminated ones) leads to a distortion of the waveforms across the switching
transistor when the transistor is turned off.
Remark F.2 Most of the output transistors are current overload protected.
However, please don’t test this, as I don’t know how good the current protec-
tion is.
Remark F.4 For many of the plots suggested below it may make sense to plot
the switching waveform to the transistor at the same time. This allows one to
correlate the waveform with the switching signals.
prbit_l4 prbit_l4
BIT BIT
STREAM STREAM
50e-3
sw1_l4
pwld
pwld
v_dc 10
100e-6 40000
d. Simulate the transient performance of the circuit in open loop with a step
change in the load resistance.
e. Increase the load value in the simulation and verify that the inductor
current becomes discontinuous at the value calculated in Item b
f. Place a closed loop PWM controller around the circuit of Figure F.3. The
controller should have the general form shown in Figure F.4. You can
use the ideal operational amplifier components from the Saber simulator
library. Simulate the circuit with the control around it (you will have
to determine the feedback gain to get the best performance without the
system becoming unstable). Again simulate a step change in the load on
the circuit performance (i.e.1kΩ to 500Ω).
g. Set up the open loop circuit of Figure F.3 on the experimental module.1
Plot the current through the switch and through the inductor. Plot the
output voltage ripple. Comment on the comparison of these plots with
those obtained in the simulations. Find the value of load resistance re-
quired to get discontinuity in the inductor current, and compare with the
theoretical value.2
h. Finally close the loop around the buck converter. The output voltage of
the output is fixed by the resistance setting in the control circuit shown
in Figure F.2. Experiment with step changes in the load resistance and
consider the transient response of the output.3
verr
R1
Error amplifier
PWM generation
-
Vo +
Switch To
+
- interface switch
R2
Vref Vtri
(Voltage reference) (Triangular waveform)
Figure F.4: Conceptual PWM control circuit for the buck converter.
prbit_l4
BIT
STREAM prbit_l4
BIT
STREAM
pwld 100
v_o
50e-3
sw1_l4
sw1_l4
the output transistor (as shown in Figure F.1) from distorting the
output waveform.
a. Calculate the output voltage versus duty cycle for the circuit of Figure F.5
with: (i) continuous inductor current, and (ii) a discontinuous inductor
current. The load is a 1000Ω resistor and a 30V output voltage. Calculate
the output ripple.
b. Simulate the circuit of Figure F.5 and confirm the calculations of Item (a).
c. Place a feedback controller, based on that of Figure F.4, around the circuit
of Figure F.5 and simulate the stability of the resultant configuration.
Apply step changes in the load resistance and plot the resultant output
transient performance. Comment on the stability of circuit, and suggest
how it may be improved.
d. Set up the boost converter circuit of Figure F.5 on the experimental mod-
ule. Apply a duty cycle so that a 30V output voltage is generated. Make
sure that you start with a small duty cycle so that you do not generate
a voltage that is too high for the transistor. Plot the current through
the inductor. Experiment with changes in the duty cycle and look at the
inductor current – is there any non-linearity in it and if so why?
e. Change the load resistance in the experimental circuit of Item (d) so that
the current in the inductor becomes discontinuous. Use the value calcu-
lated in Item (a) as a starting point. Plot the current in the system as
that current becomes discontinuous. Generate plots that demonstrate the
voltage gain of the converter under discontinuous current operation.
a. Calculate the duty cycle boundaries for the isolated forward converter
circuit shown in Figure F.6 assuming that N1 : N2 = 1 : 1 and N1 :
N3 = 1 : 2, and alternatively N1 : N2 = 1 : 2 and N1 : N3 = 1 : 1.
Comment on the effect of the various turns ratios on the performance of
the circuit. Calculate the voltage gain of the converter with continuous
and discontinuous output filter current and arbitrary turns ratios.
b. Set up the circuit of Figure F.6 in Saber and plot the output voltage, the
voltage across the switch, the voltage across the energy feedback winding,
the current through the energy feedback winding, and the current through
the filter inductor for the various winding configurations. Alter the duty
cycle so that the filter inductor current becomes discontinuous and check
the value against the values from the expressions calculate in Item a.
F.3 The Experiments 399
iL
D1 L
N3 + vL -
N1 N2 D2 C RL Vo
Vd
D3
SW
d. Set up the circuit of Figure F.6 on the experimental module. Plot the same
results as for Item b, and explain any discrepancies between the simulation
and experimental results. Is there any sign of leakage inductance effects
in this circuit? Apply a snubber to the switching transistor and replot the
output voltage across the transistor.
400 Assignment 2
Appendix G
This appendix will give a brief review of second order circuits. This is included
as second order series and parallel circuit inevitably come into high speed dig-
ital systems due to the presence of inductance and capacitance in the various
circuits.
di d2 i i dv
R +L 2 + = (G.1)
dt dt C dt
Taking the Laplace Transform of (G.1) we can write the following transfer
function for the current: transfer function
i(s) sC
= (G.2)
vin (s) LCs2 + RCs + 1
and therefore the transfer function for the voltage across the capacitor is:
vo (s) 1
= 2
(G.3)
vin (s) LCs + RCs + 1
vin C vout
i
-
where:
R
α= (G.6)
2L
1
ωo = √ (G.7)
LC
One can get a better impression of the position of the poles if they are plotted
on the complex plane. This is shown in Figure G.2. Note that this diagram is
only showing one of the two conjugate poles.
We can define several other terms from this diagram. The natural resonant
natural resonant frequency, ωd , is the frequency of oscillation of the natural response (i.e. source
frequency free response) of the circuit when there is resistance present. This is different
resonant frequency from the resonant frequency, ωo , which is the resonant frequency of a lossless
damping factor series RLC circuit.1 Another variable of interest is the damping factor . The
formal definitions are:
ωd = ωo2 − α2 (natural resonant frequency) (G.8)
α
ξ = cos θ = (damping factor) (G.9)
ωo
From Figure G.2 one can see that if the poles are off the real axis of the com-
plex plane then there is a projection of the complex vector onto the imaginary
axis. This means that there is an oscillatory mode in the response of the circuit.
If the angle θ is zero, then the two poles are coincident. This condition corre-
critical damping sponds to critical damping.2 Because there is not projection onto the imaginary
1 The resonant frequency is the frequency at which a driven series RLC circuit will exhibit
is minimum impedance.
2 Critical damping gives the fastest response without overshoot.
G.1 Series RLC Circuits 403
Im
wo
wd
wo
q
Re
a
axis there is no oscillatory or over shoot behaviour in the response. From the
viewpoint of the equations critical damping corresponds to the condition:
ωd = ωo2 − α2 = 0 (G.10)
α = ωo
R 1
=√
2L LC
L
∴R=2 (G.11)
C
For the case where:
α > ωo (G.12)
we have two real poles generated. One the these poles will move towards the
left on the real axis and the other to the right. The system response is now very
slow, and it is said to be overdamped . There are no oscillations. overdamped
Another important property of a series RLC circuit is its impedance. Rear-
ranging (G.2) we can write the impedance transfer function:
vo (s) LCs2 + RCs + 1
Z(s) = = (G.13)
i(s) Cs
If we let s = jω (i.e. the resonant frequency), and substitute this into (G.13)
we get:
1 ωL
Z(s) = R + −
jωC j
2
ω LC − 1
=R+j (G.14)
ωC
404 Review of Second Order Circuits
Clearly the magnitude of this expression has a minimum value when the imag-
inary term is zero. Therefore:
1
ω 2 LC − 1 = 0 ⇒ ω = √ = ωo (G.15)
LC
The minimum impedance is R under this condition. As noted earlier, this occurs
at the resonant frequency (ωo ), and not the natural resonant frequency (ωd ).
where:
s1,2 = −α ± jωd (G.25)
Expanding the exponential terms in this equation we can write:
where:
B1 = A1 + A2
B2 = j(A1 − A2 )
v0 (0) = V0 (G.27)
dv0 (0)
=0 (G.28)
dt
Applying the first of these conditions to (G.26) we can write:
B1 = V0 (G.29)
dv0
= e−αt [(B2 ωd − αB1 ) cos ωd t − (B1 ωd + αB2 ) sin ωd t] (G.30)
dt
Applying (G.28) to this expression gives:
αV0
αB1 = B2 ωd ⇒ B2 = (G.31)
ωd
and hence the voltage equation becomes:
α
v0 (t) = V0 e−αt cos ωd t + sin ωd t (G.32)
ωd
From (G.8), (G.7), (G.6) and (G.22) we can derive the following expressions:
1 R2
ωd = −
LC 4L2
1 1
= −
LC 4LCQ2
1 1
=√ 1− 2
(G.34)
LC 4Q
We shall assume that Q > 0.5, which means that the circuit is underdamped
and ωd > 0.
If we want to find the point of the first maximum swing in the time response
(i.e. the first maximum in the oscillatory response), then we know this must
occur when ωd t = π. Therefore:
π
tf m =
ωd
√
π LC
⇒ tf m = (G.35)
1 − 4Q
1
2
−π
√
= −V0 e 4Q2 −1
(G.36)
Figure G.3 shows that time plot for a series RLC circuit. In this particular
case the circuit Q is 6.3.
From (G.36) we can drawn the conclusion that:
−π
√
4Q2 −1
Vovershoot /Vstep = e (G.37)
0.8
- LR Ot
e MN 2L PQ
0.6
0.4
Voltage v volts
0.2
-0.2
-0.4
- 0.6
-0.8
0 0.5 1 1.5 2 2.5 3 3.5 4
Time t (secs)
p LC
t fm =
-p 1
1-
v 0 (t fm ) = -V0e 4Q 2 -1 4Q 2
iin
vin R L C
1 1
iin (s) C(s2 + RC s+ LC )
= (G.39)
vin (s) s
impedance transfer The impedance transfer function can be simply written from a rearrangement
function of (G.39 as:
vin (s) s
Z(s) = = 1 1 (G.40)
iin (s) C(s2 + RC s + LC )
poles As in the series RLC circuit case we can now find the poles of this transfer
function, which have a similar form to those for the series RLC circuit:
s = −α ± α2 − ωo2 (G.41)
where:
1
α= (G.42)
2RC
1
ωo = √ (G.43)
LC
As with the series RLC circuit we can define:
ωd = ωo2 − α2 (G.44)
Critical damping Critical damping is defined similarly to that for series RLC circuits in that
ωd = 0. This leads to:
α = ωo
1 1
∴ =√
2RC LC
1 1
⇒R= (G.45)
2 LC
The impedance of the circuit at resonance, as with the series RLC circuit,
is of interest. Substituting s = jω into (G.40) and simplifying and taking the
magnitude we can write:
ω
|Z(s)| = 1 (G.46)
ω2
R2 + L − Cω 2
√
If ω = ωo = 1/ LC then:
|Z(s)| = R (G.47)
which can be shown to be the maximum impedance of the circuit.
Vm2 To
eR (t) = PR To =
2R
Vm2
= (G.53)
2fo R
Review of Transmission
Lines
This appendix carries out a brief review of classical transmission line theory.
Much of the work in the appendix is based on [22].
A transmission is distinguished from a traditional lumped circuit network in
that it is a transmission medium that is long enough that the currents and volt-
ages at various points in the line cannot be considered to be the same value at
any point in time. Therefore the line length is at least of the order of the wave-
length of the signal being propagated down the line. Since an ideal transmission
line is considered to be uniform, then the distributed nature of the currents and
voltages (in respect of distance down the line) lead us to the conclusion that
the line can be considered to be an infinite number of infinitesimal elements
distributed along the line, each set of elements reacting to the local voltage and
currents at any point of time.
1. The separation distance b between the two wires and, therefore also the
radius a of the wires is small in comparison with the space scale length of
variations of the voltage and current as well as the associated electric and
magnetic fields.
3. In general the currents in the two wires at a cutting point across the wires
can obey the following law:
I1 = IB + IU (H.1)
I2 = −IB + IU (H.2)
where:
I1 − I2
IB =
2
I1 + I2
IU =
2
Notice that the currents consist of two components – the IB components
are equal and opposite in the two wires. The IU components though are in
the same direction in the two wires. This is the situation that occurs in an
unbalanced transmission line and has to be treated using electromagnetic
theory. It shall be assumed in this analysis that the line is balanced and
the IU component is negligible.
a<b λ (H.3)
Remark H.3 Assumption 2 means that the line has to be considered to infinite
length. Clearly a finite length line does not satisfy this requirement. However, in
most practical cases the end effects associated with finite length lines are small
enough to justify their omission.
Remark H.4 Assumption 3 states that the circuit approach to the analysis of
the transmission lines can be carried out if the line is balanced. Imbalance an
occur is a line due to things like unsymmetrical placement of the two lines with
respect to other lines or the earth; unsymmetrical placement of a load on the
line, or excitation on an unsymmetrical fashion.
Now that we have outlined the assumptions we are now in a position to begin
the modelling of the transmission line. The following parameters are shown in
Figure H.1. Let use define:
2a
2a
x x + Dx
I (x , t ) A I (x + Dx , t )
LDx
RDx
V (x , t ) C Dx GDx V (x + Dx , t )
Figure H.1: Two wire transmission line and a single element model.
414 Review of Transmission Lines
Given the above definitions for the parameters of the system, then the pa-
rameters for a length of line ∆x is clearly ∆x times the value per unit length.
To develop the circuit equations for the circuit element we resort to our
old favourites – Kirchhoff’s voltage law and Kirchhoff’s current law. Applying
Kirchhoff’s voltage law first we can write:
∂
−V (x, t) + L∆x I(x, t) + R∆xI(x, t) + V (x + ∆x, t) = 0 (H.4)
∂t
Dividing this expression by ∆x we can write:
V (x + ∆x, t) − V (x, t) ∂
+ L I(x, t) + RI(x, t) = 0 (H.5)
∆x ∂t
Let us consider this expression as we take the limit as ∆x → 0. We can see that
the first term of (H.5) is the definition of a derivative, hence we can write the
equation as:
∂ ∂
V (x, t) = − L I(x, t) + RI(x, t) (H.6)
∂x ∂t
Remark H.5 One can see that (H.6) simply says that the rate of change of
voltage along a differential length of line is simply the inductive voltage drop on
the line section plus the resistive voltage drop in the section.
∂
−I(x, t) + C∆x V (x + ∆x, t) + G∆xV (x + ∆x, t) + I(x + ∆x, t) = 0 (H.7)
∂t
Remark H.6 Equation (H.9) simply says that the change in the current across
an element of the line is due to the shunt elements of the line bleeding off current.
H.2 Solution of Transmission Line Equations for the Lossless Case 415
∂2 ∂2 ∂
2
V (x, t) = LC 2 V (x, t) + (LG + CR) V (x, t) + RGV (x, t) (H.11)
∂x ∂t ∂t
Similarly, taking the partial derivative of (H.9) with respect to x gives:
∂2 ∂2 ∂
I(x, t) = − C V (x, t) + G V (x, t) (H.12)
∂x2 ∂t∂x ∂x
Substituting for (∂/∂x)V (x, t) using (H.6) and manipulating the result gives:
∂2 ∂2 ∂
2
I(x, t) = LC 2 I(x, t) + (RC + GL) I(x, t) + GRI(x, t) (H.13)
∂x ∂t ∂t
Summary H.1 We can summarise the fundamental differential equations for
a transmission line as:
∂ ∂
V (x, t) = − L I(x, t) + RI(x, t) (H.14)
∂x ∂t
∂ ∂
I(x, t) = − C V (x, t) + GV (x, t) (H.15)
∂x ∂t
∂2 ∂2 ∂
2
V (x, t) = LC 2
V (x, t) + (LG + CR) V (x, t) + RGV (x, t) (H.16)
∂x ∂t ∂t
∂2 ∂2 ∂
2
I(x, t) = LC 2 I(x, t) + (RC + GL) I(x, t) + GRI(x, t) (H.17)
∂x ∂t ∂t
Remark H.7 Because of the partial differential nature of (H.16) and (H.17) it
is difficult to solve them in general.
Note H.1 The voltage difference V (x, t) at some particular point on the line
(i.e. a particular x) and at a particular time (i.e. a particular t) is the voltage
difference between the two wires at that particular point. It is not the voltage
difference to some single reference point.
Note H.2 The above change of variable implies that the original variables are
related as follows to the new variables:
ξ+η
x= 2
η−ξ (H.24)
t = 2v
Therefore the original V (x, t) and I(x, t) functions can be written as V (ξ, η) and
I(ξ, η).
Using the content of Note H.2 we can develop the following relationships for
the differential of V in terms of the old and changed variables:
∂V ∂V ∂V ∂V
dV = dx + dt = dξ + dη (H.25)
∂x ∂t ∂ξ ∂η
∂V ∂V ∂V ∂ ∂ ∂
= + or = + (H.27)
∂x ∂ξ ∂η ∂x ∂ξ ∂η
1 ∂V ∂V ∂V 1 ∂ ∂
=− + or =− + (H.28)
v ∂t ∂ξ ∂η v ∂ξ ∂η
H.2 Solution of Transmission Line Equations for the Lossless Case 417
∂ 1 ∂ ∂ ∂ 1 ∂ ∂
+ =2 ; − =2 (H.29)
∂x v ∂t ∂η ∂x v ∂t ∂ξ
Considering (H.20) and (H.29) one can see the (H.20) can be written as:
∂ 1 ∂ ∂ 1 ∂
+ − =0 (H.30)
∂x v ∂t ∂x v ∂t
∂2
V =0 (H.31)
∂ξ∂η
Equation (H.31) is now a very simple equation to solve. One merely has to
integrate the equation twice, once for the ξ variable and once for the η variable.
These integrations can be written as follows:
∂ ∂V
dξ = f2 (η) + cv (H.32)
∂ξ ∂η
where the “” denotes the derivative with respect to the functions variable.
Therefore after the first integration we are left with:
∂V
= f2 (η) + cv (H.33)
∂η
We now carry out the second integration with respect to η to find the solution
to the voltage equation: voltage equation
∂V
V (x, t) = dη = (f2 (η) + cv )dη
∂η
= f1 (ξ) + f2 (η) + cv
= f1 (x − vt) + f2 (x + vt) + cv (H.34)
Note H.3 The cv after integration is also a function of η. Therefore this is
rolled into the function f2 (η) upon the η integration step. The cv constant in
the final expression is simply a constant and is independent of either ξ or η.
This has to be the case as it disappears after the two partial differentiations.
Remark H.8 The integrations to end up with (H.34) can be carried out in any
order – i.e. one could integrate with respect to η first followed by ξ and the result
will be the same.
One can easily prove that (H.34) is a solution to the original differential
equation by carrying out the appropriate derivatives. This is most easily carried
out by using the following general identity. Let γ(x1 , x2 ) be an arbitrary function
of two variables, and f (γ) be an arbitrary function of γ, then by the chain rule
of differentiation:
∂ ∂f ∂γ
f (γ) = (H.35)
∂x1 ∂γ ∂x1
418 Review of Transmission Lines
Applying this identity to the derivative of the left hand side of (H.20) we get:
∂2 ∂
2
V (x, t) = (f1 (ξ) + f2 (η))
∂x ∂x2
2 2
∂2 ∂ξ ∂2 ∂η
= 2 f1 + 2 f2
∂ξ ∂x ∂η ∂x
∂2 ∂2
= 2 f1 + 2 f2 (H.36)
∂ξ ∂η
Now applying the same identity to the right side of (H.20) we can write:
∂2 ∂
V (x, t) = 2 (f1 (ξ) + f2 (η))
∂t2 ∂t
2 2
∂2 ∂ξ ∂2 ∂η
= 2 f1 + 2 f2
∂ξ ∂t ∂η ∂t
2 2
∂ ∂
= v2 f1 + 2 f2 (H.37)
∂ξ 2 ∂η
If one compares (H.36) and (H.37) one can see that (H.20) holds as required for
the solution.
In a similar manner to the solution of the voltage equation one can also
current equation derive the solution for the current equation in the line:
Remark H.10 One can see from (H.34) and (H.38) that the f and g functions
(regardless of the direction of propagation) do not contain any attenuation term.
Therefore the waveforms are propagated without any losses and will propagate
forever down an infinite transmission line. This is a fact that follows from not
including any losses in the line.
Remark H.11 Another interesting point about the solutions is that they do not
contain any frequency dependent terms. Therefore the transmission line has an
infinite frequency response. One can propagate a signal of any frequency down
the line without any losses.
We note from (H.18) and (H.19) that there is a relationship between the
voltage and the current at a particular point in the line. For example consider
(H.19), rewritten here for convenience:
∂ ∂
I(x, t) = −C V (x, t) (H.39)
∂t ∂t
H.2 Solution of Transmission Line Equations for the Lossless Case 419
∂ ∂
V (x, t) = (f1 (x − vt) + f2 (x + vt) + cv )
∂x ∂x
∂f1 ∂(x − vt) ∂f2 ∂(x + vt)
= +
∂(x − vt) ∂x ∂(x + vt) ∂x
∂f1 ∂f2
= + (H.43)
∂ξ ∂η
Comparing the derivative in (H.43) with (H.42) one can see that:
∂ ∂f1 ∂f2 d
−L I(x, t) = LCv 2 + LCv 2 − L f3 (t)
∂t ∂ξ ∂η dt
∂f1 ∂f2 d
= + − L f3 (t) (H.49)
∂ξ ∂η dt
420 Review of Transmission Lines
since LC = 1/v 2 .
This expression should be the same as (H.43) because of (H.18), therefore
the function of integration f3 (t) must be zero or a constant since it disappears
when a derivative is taken with respect to x. We shall denote this constant as
ci and hence we can write the expression for the current in terms of the voltage
functions as follows:
I(x, t) = Cvf1 (x − vt) − Cvf2 (xv t) + ci (H.50)
Remark H.12 A comparison of (H.50) with (H.38) leads one to the following
equalities:
g1 (x − vt) = Cvf1 (x − vt) (H.51)
g2 (x + vt) = −Cvf2 (x + vt) (H.52)
Remark H.13 The previous remark leads us to the following conclusion – the
characteristic term Cv is equal to 1/R0 , where R0 the characteristic impedance of the
impedance transmission line. This can be deduced from the fact that the current is related
to the voltage functions via a real constant Cv. Therefore this constant must
have the dimensions of resistance (which can be verified via a formal dimension
analysis). If one expands this definition of characteristic impedance using the
definition of v, then the expression for it is:
L
R0 = (H.53)
C
Using (H.53) one can write the expression for I(x, t) as:
1 1
I(x, t) = f1 (x − vt) − f2 (x + vt) + ci (H.54)
R0 R0
Remark H.14 The constants cv and ci that appear in the (H.34) and (H.38)
do not have any relationship between them defined by the original differential
equations of the system. There values are completely specified by the boundary
conditions of the transmission line – i.e. by the source impedance and the load
impedance. They are DC values for the voltage (cv ) and current (ci ) flowing in
the transmission line under DC conditions. It is easily shown that the value of
cv can be determined independently of the value of ci .
ated.
H.2 Solution of Transmission Line Equations for the Lossless Case 421
Example H.1 Consider the situation shown in Figure H.2. We have a voltage
source that puts a pulse onto the line at time t = 0. The voltage source has an
internal impedance of Rg Ω. We shall work out the values of the functions for
the voltages and currents down the line. The generator function can be written
as:
0 ∀t < 0
Vg (t) = (H.57)
1 ∀t ≥ 0
Therefore:
Vg (t)R0
V (0, t) = = f1 (−vt) (H.58)
Rg + R0
Vg (t) f1 (−vt)
I(0, t) = = (H.59)
Rg + R0 R0
One can manipulate these expressions so that the f1 expressions can be more
readily interpreted with respect to the generator function voltage. For example,
after 10 seconds say, the waveform will have travelled 10v in the positive x
direction. Therefore, position 10v on the x axis corresponds to t = 0 in the time
axis of the voltage generator. Similarly the position 9v corresponds to the t = 1
position in the time axis of the voltage generator. Therefore one can see that
the time axis effectively runs in the negative x direction on the transmission
line voltage versus distance/current plot. Therefore the x axis waveform can be
correlated to the time axis input waveform by realising that:
x
t= (H.60)
v
is the time required for a waveform to travel the distance x. Therefore Vg (t−x/v)
is equivalent to f1 (x − vt) for all t and x.
Using this knowledge and the above equations one can write:
R0 x
V (x, t) = f1 (x − vt) = Vg t − (H.61)
Rg + R0 v
f1 (x − vt) 1 x
I(x, t) = = Vg t − (H.62)
R0 Rg + R0 v
Figure H.3 shows the plots for the time domain and distance domain at some
time t1 . Notice that the plots effectively run in opposite directions to each other –
i.e. the time domain plot evolves to the right in the figure, which corresponds to
moving to the left in the distance plot. The crossed arrows shown corresponding
points on the two plots. Also note the f1 (x − vt) has its own origin at the point
of the dotted line and this origin moves with the waveform when plotted on the
x axis.
Rg
Vg Transmission line R0 To ¥
Vg (t )
t
0 t1
f1(0)
f1(x - vt )
x
-vt1 vt1
We have noted that at every cut plane in the line the voltage and the current
are related as:
V (x, t)
= R0 (H.63)
I(x, t)
The obvious question then arises – what happens at the RL termination? The
key to answering this question is to realise that Kirchhoff’s circuit equations,
which hold all the way along the transmission line also have to hold at the RL
termination.
Before discussing the conditions at the termination in detail, let us introduce
a little extra notation. We shall denote V+ and I+ to be the voltage and current
waveforms that move in the positive x direction as they reach the termination.
Similarly, we denote V− and I− as the voltage and current waveforms travelling
in the −x direction at the termination.
As the voltage and current waveforms approach the termination then in
general:
V+ VL
= R0 = = RL (H.64)
I+ IL
This inequality implies that Kirchhoff’s circuit equations don’t hold. To see this,
assume that the voltage VL = V+ . This would mean that IL = V+ /RL = V+ /R0 .
Therefore, the current at the node required for the resistor does not equal the
current flowing at that point in the transmission line. Kirchhoff’s current law
is not obeyed. Even though this is a slightly artificial example, it nevertheless
shows the basic problem.
Of course Kirchhoff’s laws must be satisfied at the load resistor. In order for
them the hold the V + waveform is considered to reflect from the termination
and generate a waveform that moves in the −x direction. Similarly for the
current waveform. Therefore:
V+ + V− = VL (H.65)
V+ V− VL
I+ + I− = IL or − = (H.66)
R0 R0 RL
One can see from these equations that the voltage and current equations now
make sense.
Let us define the reflection coefficient as: reflection coeffi-
cient
V− I−
ρ= =− (H.67)
V+ I+
Substituting (H.65) and (H.66) into (H.67) one can write:
V+ V− V+ + V−
− =
R0 R0 RL
1 1 1 1
∴ V+ − = V− +
R0 RL R0 RL
V− RL − R0
⇒ρ= = (H.68)
V+ RL + R0
Remark H.15 If RL = R0 then ρ = 0 which means that there is no reflection.
If RL = 0 then ρ = −1 which means that the whole of the incident voltage
waveform is reflected. Therefore V+ + V− = V+ + ρV+ = 0V .
424 Review of Transmission Lines
Remark H.16 If RL > R0 then 0 < ρ ≤ 1, which implies that the incident
and reflected voltage waveforms have the same polarity. Therefore at the load
termination these voltages add together to produce a higher voltage than the
incident voltage on its own. If RL = ∞ then ρ = 1
Switch closed at
time t=0
Rg
V0 R0 , v RL
x =0 x =l
Rg
I +1
V0 R0 V+1
When the switch is closed, after a very long time – in fact an infinite time
if the line is considered to be lossless, the current and the voltage will settle to
DC values. These values are given by:
RL
Vf = V0 (H.69)
R0 + RL
V0
If = (H.70)
R0 + RL
We shall assume that at t < 0 the current and voltage in the line is zero.
As soon as the switch is closed a step waveform will begin to travel done the
transmission line (similar to the diagram in Figure H.3). We shall denote V+1
H.3 Reflection Diagrams 425
and I+1 as the forward travelling waveforms, therefore V+1 = R0 I+1 . From the
equivalent circuit at the input one can deduce that:
R0
V+1 = V0 (H.71)
Rg + R0
V0
I+1 = (H.72)
Rg + R0
We can now apply the superposition. The effective waveform that now propa-
gates in the positive direction down the transmission line is:
Therefore from the generator to the discontinuity we have the voltage of (H.76),
and from the discontinuity to the load termination we have the (1 + ρL )V+1 .
At time t = 3T the forward travelling waveform reaches the load termination
again, and we again have a reflection based in the ρL reflection coefficient.
Therefore the reflected waveform is:
and therefore from the load termination to the discontinuity we have a voltage
of:
(1 + ρL + ρg ρL )V+1 (H.79)
The whole process then repeats again at the generator, and so on forever in
the case of the lossless line.
A good way of visualising reflections and the consequent building of the
reflection diagram voltage waveforms is via a reflection diagram, as shown in Figure H.5. The
horizontal axis is the distance along the transmission line, and the vertical axis
is the time. The thick lines represent the waveforms travelling down the line,
with the arrows indicating the direction of the wave. The annotation on each
of the directed arcs denotes the magnitude of the reflected waveform.
The reflection diagram can be used to obtain either:
6T V+1r 3
Lr 2g
5T 2 2g
V +1r Lr T5
t0
4T V+1 2
r Lrg
T4
3T
T3
V +1rLrg
2T V+1r
L
T T2
T1
V +1
0
x =0 l0 l1 x = l
rg rL
Voltage
Example H.2 Suppose that one wishes to know the voltage distribution along
the line at time t0 shown on Figure H.5. Following the dashed line in this figure
one can see that at this time the voltage discontinuity is at position at l0 . To
find the total voltage at this time we add up the incremental voltages for all the
reflected waveforms on the line to the desired time. In the case of this specific
example that voltage is:
and because the waveform has not reached the section from l0 < x ≤ l then:
V (x, t0 ) = V+1 (1 + ρL + ρL ρg + ρ2L ρg ) for l0 < x ≤ l (H.81)
Suppose, on the other hand, we want to obtain the time dependence of the
voltage at a specific point on the transmission line. Consider the dotted line in
Figure H.5. As one proceeds vertically upwards along this dotted line it crosses
the oblique wave propagation lines. Therefore at time T1 the voltage on the
line at position l1 is V+1 , at T2 the voltage is V+1 (1 + ρL ), at T3 the voltage is
V+1 (1 + ρL + ρL ρg ) and so on. Therefore one is able to plot the voltage on the
transmission line at a particular point against time.
Similarly we can write the following expression for the current equation:
∂ −→ →
−
I (x) = −(G + jωC) V (x) (H.88)
∂x
These expressions can be written as:
∂ −→ →
−
V (x) = −z I (x) (H.89)
∂x
∂ −→ →
−
I (x) = −y V (x) (H.90)
∂x
where:
∂2 −→ →
− →
−
I (x) = − −jωCz I (x) − Gz I (x)
∂x2
→
−
= (G + jω)z I (x)
→
−
= zy I (x) (H.99)
H.4 Time Harmonic Solutions for Lossy Lines 429
z = R + jωL
y = G + jωC
√
γ = (R + jωL)(G + jωC) = zy (H.104)
Remark H.19 Equations (H.102) and (H.103) are simple second order ho-
mogeneous differential equations. Much of the complexity has effectively been
eliminated by the use of the phasor description for the signals.
γ 2 = (α + jβ)2 = a + jb (H.113)
Expanding the α, β expression and equating real and imaginary parts we can
write:
One can solve these expressions simultaneously to get rather complicated and
messy expressions for α and β. From these expressions it is possible to deduce
that α ≥ 0 and β ≥ 0 for all physically realisable transmission line component
values.
For the following sections we only need to consider that:
γ = α + jβ (H.116)
H.4 Time Harmonic Solutions for Lossy Lines 431
Remark H.22 Equation (H.122) shows that the voltage is attenuated as it trav-
els down a lossy transmission line.
Equation (H.123) shows that the phase is proportional to the distance down
the line. This means that there is a modulated co-sinusoidal variation of the am-
plitude down the line. It also means that in the time domain that the waveform
at some point x has a phase displacement of βx compared to the time waveform
at location x = 0.
If we now reintroduce the ejωt and take the Real part so we get:
i.e. the time changes by 2π/ω for the same value of different points down the
transmission line. Therefore this time will clearly relate to the wavelength of the
waveform on the line.
Remark H.25 In time 2π/ω the waveform will have moved 2πv/ω down the
wavelength transmission line. Therefore this distance must define the wavelength of the
wave on the transmission line.
An alternative expression can be derived by realising that at some particular
time t that there will be multiple points down the transmission line with the same
value. These points are clearly defined by the condition that:
where λ denotes the wavelength of the waveform on the line. For this condition
to hold we can see that equating the right and left sides:
βx = βx + n2π
n2π
∴x=x+ (H.129)
β
2π
λ= (H.130)
β
We can equate this expression for the wavelength with that mentioned earlier
in this remark to give:
2π 2πv
=
β ω
ω
∴v= (H.131)
β
−
→ 1
V 1 = (V0 + I0 Z0 ) (H.134)
2
→
− 1
V 2 = (V0 − I0 Z0 ) (H.135)
2
→
− 1 1
∴ V (x) = (V0 + I0 Z0 )e−γx + (V0 − I0 Z0 )eγx (H.136)
2 2
Similarly:
−
→ 1 1
I (x) = (V0 + I0 Z0 )e−γx − (V0 − I0 Z0 )eγx (H.137)
2Z0 2Z0
Equations (H.136) and (H.137) can be written more succinctly using the
relations:
ey + e−y
cosh y = (H.138)
2
ey − e−y
sinh y = (H.139)
2
Therefore the equations for the waveform distribution down the transmission
line with source boundary conditions become:
−
→
V (x) = V0 cosh(γx) − I0 Z0 sinh(γx) (H.140)
→
− V0
I (x) = − sinh(γx) + I0 cosh(γx) (H.141)
Z0
−
→ →
−
V (x) = I L [ZL cosh(γs) + Z0 sinh(γs)] (H.150)
→
−
→
− IL
I (x) = [Z0 cosh(γs) + ZL sinh(γs)] (H.151)
Z0
where s = (l − x)
and l the total length of the line
Zs r
I0
r
IL
+
r r
Vs V0 ZL
x =0 x =l
Z in
Zs
r
I0
+
r r
Vs Z in V0
→
− →
−
Therefore if we know Zin then we can work out the V 0 and I 0 coefficients and
substitute them into (H.140) and (H.141) to get the complete solution for the
line.
The general expression for the impedance for the line at any position x can
be found from the ratio of (H.150) and (H.151) to give:2
−
→ −
→
V (x) I L [ZL cosh(γs) + Z0 sinh(γs)]
Z(x) = −→ = →
−
I (x) IL
Z0 [ZL sinh(γs) + Z0 cosh(γs)]
ZL cosh(γs) + Z0 sinh(γs)
= Z0 (H.154)
ZL sinh(γs) + Z0 cosh(γs)
ZL + Z0 tanh(γs)
= Z0 (H.155)
Z0 + ZL tanh(γs)
sinh(γs)
where tanh(γs) =
cosh(γs)
The input impedance for a general terminated line can be written from
(H.154) by realising that for the input impedance s = l (i.e. x = 0). Therefore
the expression is:
ZL cosh(γl) + Z0 sinh(γl)
Zin = Z(0) = Z0 (H.156)
ZL sinh(γl) + Z0 cosh(γl)
2 Remember that s = l − x.
436 Review of Transmission Lines
In one uses this new definition of γ into the expressions for cosh(γl) and
sinh(γl) we can write the following:
Making these substitutions into (H.156) we can get the input impedance for a
lossless line:3
ZL cos(βl) + jZ0 sin(βl)
Zin = Z0 (H.160)
jZL sin(βl) + Z0 cos(βl)
Combining these two terms we can write the transfer function as:
−
→
VL Z0 ZL
→ = (Z Z + Z Z ) cos(βl) + j(Z 2 + Z Z ) sin(βl)
− (H.166)
Vs s 0 0 L 0 s L
Equation (H.166) can be used as a starting point for carrying out a frequency
domain analysis of a transmission line with a particular loading on it.
Z eq
r
IL
+
r r
Vse ZL VL
Let us begin with the equivalent impedance of the line looking from the load
end towards the source. In order to find this the normal technique is to short
circuit the source voltage and then work out the impedance looking from the
load. In this particular case we can use the results we have in (H.160) to do this
because of the symmetry on the system. We simply need to replace ZL with Zs
in the input impedance expression which gives:
Zs cos(βl) + jZ0 sin(βl)
Zeq = Z0 (H.167)
Z0 cos(βl) + jZs sin(βl)
To find the equivalent source voltage one has to work out the current flowing
at the load point if the load is replaced with a short circuit. We can use (H.163)
to express the load voltage for a general load ZL in the following expression for
438 Review of Transmission Lines
If one considers the equivalent circuit of Figure H.7 then the load current is:
→
−
−
→ V se
IL=
Zeq
→
−
[Z0 cos(βl) + jZs sin(βl)] V se
= (H.170)
Z0 [Zs cos(βl) + jZ0 sin(βl)]
The currents in the actual line and the equivalent circuit under the condition
of a short circuited load have to be the same, therefore equating (H.169) and
(H.170) and then simplifying we can write:
→
−
−
→ Z0 V s
V se = (H.171)
Z0 cos(βl) + jZs sin(βl)
4 Note →
−
that with ZL = 0 then implicitly V L = 0.
Appendix I
Useful Formulae
I.1 Introduction
This appendix contains a number of formulae that are useful in the area of
transmission lines, especially when they occur in digital transmission systems.
Most of the expressions here can be found scattered throughout the literature,
but one reference that collects them together in one place is [1]. The expressions
in this reference are almost all in imperial units. We shall use MKS units in
this appendix where appropriate. In some cases imperial units will still be used
because these are the units that are used extensively in the literature.1
I.3 Formulae
I.3.1 AWG Related Conversions
Equations (I.1) and (I.2) allows the American Wire Gauge to be converted to a
wire diameter in metres and vice-versa.
d
AWG = −10 − 20 log( ) (I.1)
0.0254
d = 2.54 × 10−[ 20 −2] m
AWG+10
(I.2)
Equation (I.3) allows one to obtain the resistance of a round wire given its
diameter (or AWG) and length in metres:
4ρl
R= (1 + (T − 20)δρ) (I.3)
πd2
1 For example, imperial units are used almost exclusively in PCB measurements, because
much of the sofrtware used in this industry has been written in the USA, or its target market
is in the USA.
440 Useful Formulae
Constant Value
a This value takes into account the changes in the resistivity due to the annealing process
and the chemical imperfections caused by the manufacturing process for wires.
b The resistivity can be thought of as the resistance of the 1m3 block of material.
c This ¡ is the conventional value for the resistivity of copper at 20◦ .
d This quantity of defined as 1 dρ .
ρ dt
ρl
R= (1 + (T − 20)δρ) (I.5)
0.000034798(CPW)w
This assumption is good for normal PCB traces, but breaks down with wide structures such
as ground and power supply planes.
I.3 Formulae 441
l
Dielectric
Figure I.1 shows a generic parallel plate capacitor. It is assumed that the ma-
terial between the plates has a dielectric constant of = r 0 . The capacitance
of the system is:
A lw
C= = Farads (I.8)
h h
Remark I.1 Note the weak dependence of the inductance with respect to the
wire radius. This is a result of the ln function in (I.9). However, the inductance
of the loop is strongly dependent on the radius of the loop.
442 Useful Formulae
Characteristic Impedance
L0
Z0 = (I.13)
C0
Propagation delay per cm
D= L0 C0 (I.14)
Capacitance per cm
D
C0 = (I.16)
Z0
Inductance per cm
L0 = DZ0 (I.17)
where:
L0 inductance per cm
C0 capacitance per cm
D propagation delay per cm
reff effective relative permittivity
d2 d1
Figure I.2 shows the cross-section of a coaxial cable. The relevant transmis-
sion line characteristic impedance expression is:
60 d2
Z0 = √ ln (I.18)
r d1
444 Useful Formulae
The inductance and capacitance of the coaxial transmission line are respec-
tively:
d2
L = (2.002 × 10−9 )x ln (I.19)
d1
(5.56 × 10−13 )xreff
C= (I.20)
ln dd21
Assume air
dielectric
Figure I.3 shows the situation of a round wire suspended in air above a
ground plane. This is the situation that occurs in a wire wrap board layout.
The relevant expressions for this are:
4h
Z0 = 60 ln (I.21)
d
where:
One of the advantages of wire wrap is that the propagation delay per cm
is as fast as it can be – i.e. 3.336 × 10−11 sec/cm or 33.36 psec/cm. This is
because it operates in an air dielectric.3
The total inductance of the wire trace can be found using (I.17) and multi-
plying by the length of the trace:
−9 4h
L = (2.002 × 10 )x ln (I.22)
d
3 We are assuming in this that the ground plane is on top of the supporting PCB material.
In many situations this may not be the case, and consequently the relative dielectric will be
greater that 1 and the propagation velocity will be lower.
I.3 Formulae 445
(5.560 × 10−13 )x
C= (I.23)
ln 4h
d
Figure I.4 shows the configuration of the twisted pair conductors. The effec-
tive permittivity of the conductors depends on the degree of twist of the cables,
since this alters the amount of flux the flows through the insulation dielectric
and air. Suffice to say, the effective dielectric constant will be greater than one
for insulated wire.
The relevant expressions of this transmission line are:
120 2s
Z0 = √ ln (I.24)
reff d
Total inductance of the twisted pair transmission line can be calculated using
the length of the line and (I.17) to give:
−9 2s
L = (4.003 × 10 )x ln (I.26)
d
446 Useful Formulae
and similary the total capacitance for the transmission line is:
(2.78 × 10−13 )xr
C= (I.27)
ln 2s
d
Dielectric constant e r
w
µ0 0 1
Z0 = (I.28)
e Ca
2π0
ln( 8h
when w
h ≤1
ww + 4h )
w
Ca = w w
(I.29)
0 h + 1.393
+ 0.667 ln h + 1.444 when >1
h
− 12
r + 1 r − 1 12h t
e = + 1+ + F − 0.217(r − 1) √ (I.30)
2 2 w wh
w 2
0.02(r − 1) 1 − h w
when h < 1
F = (I.31)
0 when w h >1
where:
Equation (I.29) has a lower limit of 0.25 for the w/h ratio. An approximate
expression for the characteristic impedance that will give values for smaller w/h
ratios is:
87 5.68h
Z0 = √ ln (I.32)
r + 1.41 0.8w + t
which is valid when 0.1 < w/h < 2.0 and 1 < r < 15.
Dielectric constant e r
w t
The following expression are for a stripline where the interior conductor is
in the middle of the top and bottom planes, as shown in Figure I.6 [1]. The
following expressions are accurate for:
t
< 0.25
h
t
< 0.11
w
w
For h < 0.35 (i.e. a narrow line):
60 4h
Z0sym = √ ln (I.33)
r πK1
2
w t 4πw t
K1 = 1+ 1 + ln + 0.255 (I.34)
2 wπ t w
w
For h > 0.35 (i.e. a wide line):
94.15
Z0sym = √ (I.35)
r h−t w
+ Kπ2
2 1 1 1
K2 = ln +1 − − 1 ln −1 (I.36)
1 − ht 1 − ht 1− t
h (1 − ht )2
Dielectric constant e r
t
b w
noted that these equations are an approximation, and a field solver should be
used for more accurate results:
Z0sym (h1 , w, t, r )Z0sym (h2 , w, t, r )
Z0offset = 2 (I.37)
Z0sym (h1 , w, t, r ) + Z0sym (h2 , w, t, r )
where:
h1 = 2a + t
h2 = 2b + t
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