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    Harshali Wavre
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    This document is a certificate from the K. K. Wagh Institute of Engineering Education & Research in Nashik, India for a student completing coursework in ASIC Design. It lists 4 experiments completed for the subject: 1) writing VHDL code to simulate a priority encoder on a PLD, 2) writing VHDL code to simulate a RAM/FIFO on a PLD, 3) drawing a CMOS layout and simulating a full adder/MUX using backend tools, and 4) simulating a stuck-at fault model. The certificate is signed by the faculty in charge, department head, and principal to certify the student has satisfactorily completed the term work and experiments for the

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    This document is a certificate from the K. K. Wagh Institute of Engineering Education & Research in Nashik, India for a student completing coursework in ASIC Design. It lists 4 experiments completed for the subject: 1) writing VHDL code to simulate a priority encoder on a PLD, 2) writing VHDL code to simulate a RAM/FIFO on a PLD, 3) drawing a CMOS layout and simulating a full adder/MUX using backend tools, and 4) simulating a stuck-at fault model. The certificate is signed by the faculty in charge, department head, and principal to certify the student has satisfactorily completed the term work and experiments for the

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    17 views2 pages

    K. K. Wagh Institute of Engineering Education & Research, Nashik

    Uploaded by

    Harshali Wavre
    This document is a certificate from the K. K. Wagh Institute of Engineering Education & Research in Nashik, India for a student completing coursework in ASIC Design. It lists 4 experiments completed for the subject: 1) writing VHDL code to simulate a priority encoder on a PLD, 2) writing VHDL code to simulate a RAM/FIFO on a PLD, 3) drawing a CMOS layout and simulating a full adder/MUX using backend tools, and 4) simulating a stuck-at fault model. The certificate is signed by the faculty in charge, department head, and principal to certify the student has satisfactorily completed the term work and experiments for the

    Copyright:

    © All Rights Reserved
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    Download as docx, pdf, or txt
    of 2

    K. K.

    WAGH INSTITUTE OF ENGINEERING EDUCATION & RESEARCH,


    NASHIK.
    Department of Electronics & Telecommunication Engineering
    M. E. (E & TC VLSI & Embedded
    Systems)
    ASIC Design
    INDEX
    Sr. No.
    1.

    Name of Experiments

    Date

    Write VHDL code to simulate, synthesis, place & route


    priority encoder in PLD. Check the results and also write
    the test bench.

    2.

    Write VHDL code to simulate, synthesis, place & route


    RAM/FIFO on PLD. Check the results and also write the
    test bench.

    3.

    Draw CMOS layout & simulate FULL adder/MUX by


    applying DRCs of appropriate foundry using backend tool
    and check the outputs.

    4.

    Simulate stuck-at fault model of a given function.

    CERTIFICATE
    This is to certify that Mr./Ms. _____________________________________________
    Roll No.

    Exam Seat No.

    has satisfactorily completed

    the term work & experiments in the subject ASIC Design in fulfillment of Third
    Semester of Masters Degree course in E & TC Engineering (VLSI & Embedded
    Systems) during the academic year 2016-2017.

    Prof. Dr. S.P. Ugle


    Faculty Incharge

    Prof. Dr. D. M. Chandwadkar


    HOD
    (E & TC / Electronics)

    Prof. Dr. K. N.
    Nandurkar
    Principal

    Remark

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