4.

Double the Clock Frequency

An input signal can be doubled in frequency, provided the resulting 2f clock can tolerate cycle-to-cycle jitter
caused by an imperfect input duty cycle. The circuit below generates an output pulse in response to each
transition of the input.
The output rising edge is delayed one TILO from either input transition. The output High time is the sum of a
clock-to-Q delay plus two TILO delays, about 2 ns in a fast part. This output pulse clocks other flip-flops on the
same die reliably. (At a low temperature and high VCC, the pulse will be shorter, but the flip-flop response is also
faster under these conditions.)
Any control input that prevents the flip-flop from toggling changes the output frequency to fout = fin.
This asynchronous circuit is frowned upon by all true digital designers. It should only be used as a tool of last
resort. Note that the DLL or DCM in all Virtex or Spartan-II devices provide frequency doubling for free, if the
input frequency is larger than 25 MHz. The frequency-doubler circuit shown below has no minimum frequency
limitation.