IEEE INDICON 2015 1570186537

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CMOS Current Starved Voltage Controlled Oscillator

Circuit for a Fast Locking PLL
Abdul Majeed K.K, Binsu J Kailath
Electronics Department
IIITDM Kancheepuram, Chennai, India
edm12d001@ iiitdm.ac.in, bkailath@iiitdm.ac.in
been extensively used in VCOs as it results in smaller
integration area and wider tuning range when compared with
the LC VCOs. Implementation of a two stage CMOS ring
oscillator using a delay cell with good phase noise performance
has been presented by W.S.T Yan, et al [1]. Better tuning range
and quadrature output have been obtained by modifying the
delay cell and the same has been used to implement a four
stage VCO [2]. Two stage CMOS voltage controlled ring
oscillator using scaled differential delay has been reported to
result in wideband while a three stage differential delay VCO is
found to result in better phase noise as well [3]. Another LC
VCO with better phase noise but with lower tuning range and
higher the power dissipation is also reported [4].

Abstract Two novel voltage controlled oscillators (CSNVCO and CSD-VCO) have been proposed in this paper. CSNVCO has been designed with 20 transistors while CSD VCO with
24 transistors. It has been observed that CSN-VCO could operate
in the frequency range from 0.066 to 2.2 GHz, and CSD VCO
could operate from 0.047 to 2.5 GHz. Tuning range for these
VCOs are determined to be 97 %, and 98.2 % while the values of
gain obtained are 8.94 and 10.2 GradV-1 respectively. Phase noise
analysis has been performed and the phase noise contribution by
CSN-VCO and CSD VCO are found to be -126 and -129 dBc/Hz
@ 1 MHz respectively. Prototype has been designed in Cadence
virtuoso environment and implemented using GPDK090 library
of 180 nm technology with a supply voltage of 1.8 V. Simulation
of transfer function of PLL built with the VCOs has been done in
MATLAB and the step response has been compared with the
circuit simulation results from Cadence. Lock time as low as 355
ns and 313 ns have been achieved for the CSN-VCO and CSDVCO respectively.

It could be observed that VCO designed using CMOS delay

cell ring oscillator may be a better option to be used as a VCO
in PLL as the phase noise could be reduced by increasing the
number of delay cells. In view of this, two VCOs based on
current starved CMOS NAND cells and current staved CMOS
delay cells are presented in this paper. The proposed VCOs are
integrated into a PLL and the design parameters have been
optimized for a better PLL design. Proposed VCO circuits and
the delay cells are presented in section II and the simulation
results are presented in section III. Performance analysis of
PLL circuit and discussion based on derived transfer function
are presented in section IV.

Keywordsphase locked loop, voltage controlled oscillator,

delay cell, phase noise.

I.

INTRODUCTION

Radio frequency integrated circuits (RFICs) are widely

used in all types of wireless communications. Phase locked
loop represents a class of commonly used RFIC wherein
Voltage controlled oscillator (VCO) is one of the important
building blocks. Designing a PLL with less locking time while
maintaining optimum values for power dissipation, phase noise
and chip area is a challenging task. And lot of research is being
carried out in this field to improve the topologies by which the
VCOs are built in order to optimize various parameters like
higher operating frequencies, low phase noise, increased tuning
range, low power dissipation and less area etc.

II. PROPOSED VCO DESIGN

The ring oscillators designed with a series of delay cell
stages have created great interest among researchers due to
their numerous useful features. These attractive features are (i)
the ease with which the circuits could be designed with CMOS
and BiCMOS technology, (ii) lower control voltage required
for oscillation, (iii) low power dissipation while providing
higher frequency of oscillations, (iv) electrical tuning and wide
range and (v) possibility to obtain multiphase outputs due to
their basic structure [6].

The various sources of phase noise in a PLL could be

categorized as either in-band or out-of-band. The loop filter
and VCO are subjected to high-pass filtering by loop action
and are therefore significant sources of out-of-band phase noise
[5]. VCO has been reported to be a significant factor in
optimizing the phase noise of the PLL system as it has been
found to be the dominant source of out-of-band phase noise [14].

A. Current starved NAND based VCO (CSN-VCO)

Schematic diagram of the proposed CSN-VCO is shown in
Fig. 1 which uses three delay cells so as to reduce the phase
noise contribution from the VCO. NAND gates present in the
center row act as inverter while upper PMOS and lower
NMOS operate as current sources which limit the current
available to the NAND gate forcing it to starve for current.
The current in the first NMOS and PMOS (P1-N1) are

Many different types of voltage controlled oscillators are

used in PLL. It has been reported in literature that LC VCOs
result in better phase noise and higher frequency at the expense
of larger integration area. Hence CMOS ring oscillators have
978-1-4673-6540-6/15/$31.00 2015 IEEE

Fig.1. Schematic diagram of Current starved NAND based VCO (CSNVCO)

Fig.3. Schematic diagram of Current starved delay-cell based VCO (CSDVCO)

mirrored in successive stages. The frequency of oscillation

could be effectively controlled as the propagation delay is
proportional to the charging and discharging currents. All the
NMOS and PMOS transistors are designed with a width of 2
m and length of 180 nm.

mirrored in the successive delay cell stages. Comparatively

better control of VCO output frequency is achieved in this
circuit as the propagation delay could be effectively controlled
using charging and discharging currents.

B. Current starved Delay-cell based VCO (CSD-VCO)

The proposed current starved delay-cell based VCO (CSDVCO) is shown in Fig. 3. which is implemented using the
modified delay cell given in Fig. 2. This delay cell is
composed of a differential pair of NMOS transistors (N1 and
N2) with cross-coupled PMOS transistors (P3 and P4) as load,
along with two PMOS current sources (P2 and P5) which
perform the function of increasing or decreasing the output
load current depending on the variation in the control voltage.
The operation of CSD VCO implemented with three stages of
this modified delay cell is similar to that of CSN VCO. Each
NAND gate present in the centre row in the CSN VCO is
replaced with modified delay cell, while upper PMOS and
lower NMOS are operated as current sources. The current
sources limit the current available to the delay cell starving it
for current. The current in the first NMOS and PMOS are

III. SIMULATION RESULTS OF VCO

The proposed current starved voltage controlled oscillators
are simulated using GPDK 180 nm CMOS technology in
CADENCE environment and performance parameters such as
tuning range, phase noise, power dissipation and gain of the
VCOs are analyzed using Virtuoso ADE. A discussion on these
results is provided in the following section with the summary
of analysis presented in Table I.
A. Transient Analysis
Transient analyses of the proposed circuits have been
performed in Cadence Virtuoso ADE with a supply voltage
Vcnt=0.5
Vcnt=0.64

Vcnt=0.77

Vcnt=1.15

Vcnt=1.54

Vcnt=1.8

Fig.2. Schematic diagram delay cell used in Current starved delay-cell based
VCO (CSD-VCO)

Fig.4. Transient response of proposed CSN-VCO with different control

voltage

-80.0

Phase Noise (dBc/Hz)

Vcnt=0.5

Vcnt=0.64

Vcnt=0.77

Vcnt=1.15

CSD VCO
CSN VCO

-100.0

-120.0

-140.0

-160.0

Vcnt=1.54
100

100M

B. Tuning Range.
Oscillating frequency versus control voltage characteristics
of the proposed VCOs are presented in Fig. 6. The output
frequency of the CSN-VCO is found to vary from 66 MHz to
2.2 GHz as the control voltage is varied from 0 V to 2 V
resulting in a tuning range of 97% and gain of 8.94 GradV-1.
Whereas, the output frequency of CSD-VCO is found to vary
from 47 MHz to 2.5 GHz for the same range of control voltage
resulting in a better tuning range of 98.12 % and gain of 10.2
GradV-1.

Fig.5. Transient response of proposed CSD-VCO with different control

voltage

(Vdd) of 1.8 V. Corresponding transient responses of CSNVCO and CSD-VCO with X-axis time scale varying from 485
ns to 500 ns are presented in Fig. 4 and Fig. 5 respectively.
VCO output signals for six different control voltages (Vcnt)
viz. 0.5 V, 0.64 V, 0.77 V, 1.15 V, 1.54 V and 1.8 V are
presented from top to bottom in both the figures. Increase in
frequency of oscillation with increase in control voltage can be
observed from both the plots. Also, output frequency of CSDVCO is found to be larger than that in CSN-VCO for the same
control voltage and the transfer characteristics is explained in
the following section.

Oscillating Frequency (Hz)

1M
Frequency (Hz)

Fig.7. Phase noise analysis of proposed CSN-VCO and CSD-VCO

Vcnt=1.8

3G

10k

C. Phase Noise Analysis.

Phase noise characteristics have been obtained by
performing periodic steady state analysis and phase noise
analysis [5] for the two VCOs and the same are presented in
Fig. 7. It can be inferred from measured values given in Table I
that the CSD-VCO is much more appropriate candidate for low
jitter applications.
IV. PLL ANALYSIS
Basic block diagram of the conventional PLL is presented
in Fig. 8 and the transfer function for such a PLL implemented
with the proposed VCOs has been determined to compare the
simulation results obtained from circuit simulation with that
from simulation in MATLAB.
,

CSN VCO
CSD VCO

2G

where
And hence
1G

(1)
(2)

0
0

F(s) is the transfer function of loop filter and using F(s) in

equation (1) would give:
1
Control Voltage (V)

(3)

Fig.6. Transfer characteristics (Oscillating frequency versus control voltage

characteristics) of CSN-VCO and CSD-VCO

This could be expressed in terms of natural frequency and

damping factor as

(7)
The constant values are obtained as A=N, B=-N and C=0.

] (8)

The inverse Laplace transform of the equation (8) is obtained

as

Fig.8. Block diagram of PLL

*
(4)

where

(9)

. Equation (9) could be expressed as

Where

and

A. Lock time (settling time:ts) of the PLL.

Lock time of the PLL have been determined by computing
the inverse Laplace transform of step response as well as by
simulation in MATLAB and circuit simulation in Cadence and
the results are compared. Coefficient of third order term in the
denominator of transfer function is found to be of the order of
10-8 to 10-10 for (C1=9 Pf, C2=1.125 pF, R1=5 K, Icp=100 A
and
) and hence the transfer function given
in equation (4) could be expressed as:

and hence
]

of the final value. The exponentially decaying term

(11)

in

the time response of the PLL determines the settling time of

PLL. As divide by N counter was set to divide the VCO
frequency by 16, the settling time
needed to reach within
the 1% tolerance limit (15.84) of the steady state value of 16 V
could be computed from equation (11) as:
[

C(s) is the output of the VCO for a step input u(t)=1 and
U(s)=

] for 1 % tolerance which gives

(12)

The values so obtained are presented in Table I along with the

1.6
CSN VCO
CSD VCO

(6)
By partial fraction equation (6) could be expressed as
CSD VCO
CSN VCO

Voltage (V)

1.04
Voltage (V)

(10)

Settling time or lock time is defined as the time taken by the

response to reach and stay within a specified error of 1 to 2 %

(5)

1.02

1.2

0.8

1.00

0.98
0

where as

1.06

250n
Time (s)

500n

Fig.9. Step Response of the PLL TFs using proposed CSN-VCO (14) and
CSD-VCO (15) in MATLAB

250n

Time (s)

500n

Fig.10. Circuit level simulation of PLL control voltage using proposed CSNVCO and CSD-VCO in Cadence

TABLE I.

VCO PERFORMANCE COMPARISON TABLE

parameters
Output Frequency (GHz)
Tuning Range (%)
Gain (GradV-1)
Phase Noise (dBc/Hz@1MHz
Power dissipation (mW)
No. of stages
Lock Time

CSNCSDVCO
VCO
0.066 to 0.047 to
2.2
2.5
97
98.12
8.94
10.2
-126
-129
6.76
12.7
3
3

By calculation (ns)
By TF analysis (MATLAB) (ns)
By simulation (CADENCE) (ns)

[3]

[1]

1.22 to
3.22
62.11
9.66
-90
9.61
2
CSNVCO
250
300
355

0.66 to
1.27
48
2.1
-106
15.5
2
CSDVCO
219
260
313

V. DISCUSSION
The performances parameters of CSN-VCO and CSD-VCO
have been compared with different architectures reported in
literature and are presented in Table I. The phase noise
contributions of the proposed VCOs are found to be -126
dBc/Hz and -129 dBc/Hz @ 1 MHz for CSN-VCO and CSDVCO respectively. The tuning range and gain of the designed
VCOs are also found to be better. Higher gain of VCO results
in accelerating the lock-in process of the PLL. Lower phase
noise contribution from CSD-VCO when compared with that
of CSN-VCO could be attributed to its higher delay due to the
delay cells. Reduction in phase noise and increase in gain is
found to result in improved lock-time for the PLL with CSDVCO and this has been verified by analytical computation, TF
analysis in MATLAB and by circuit simulation using
CADENCE. Hence these VCOs are proposed to be utilized for
low jitter and fast locking PLL.

corresponding values obtained from circuit simulation in

Cadence and TF analysis using MATLAB.

VI. CONCLUSION
Two novel current starved CMOS VCOs are presented in
this paper. Both the VCOs are found to provide higher tuning
range and larger gain which make these designs suitable for
PLL in wide band and fast locking applications. The PLL
circuit has been implemented in Cadence and the response has
been verified using simulation in MATLAB. CSD-VCO is
found to be a better design suitable for low jitter PLL design
due to its reduced phase noise and faster locking time when
compared with CSN-VCO.

B. Step Response
In order to find the step response of the PLL implemented
with designed VCOs, the respective transfer functions in each
case has been determined and MATLAB simulation studies
have been performed and are discussed in the following sub
sections. The transfer function would be
(13)
B.1. Analysis of PLL with CSN-VCO
The gain of the CSN-VCO is computed from its transfer
characteristics as
-1
*
+ = 8.94G HzV-1 , n=29.6 Mrads and =0.66
and the TF for this circuit is obtained as:

REFERENCES
[1]

(14)

[2]

B.2. Analysis of PLL with CSD-VCO

The gain of the CSD-VCO is computed as
-1
*
+ = 10.2G HzV-1 , n=31.7 Mrads and =0.714
and the TF for this circuit is obtained as:

[3]

[4]

(15)
Step responses of PLL built in MATLAB with above TF and
for both CSN-VCO (14) and CSD-VCO (15) are plotted in
Fig.9 and the lock time so computed are presented in Table I.

[5]

D. Lock time analysis of PLL using the designed VCOs.

PLL circuits have been implemented using each of the
proposed VCOs using CADENCE, along with phase
frequency detector and charge pump [7], loop filter [8] and
divide by eight counters. The charge pump circuit carries a
constant current (Icp) of 100 A.
Lock time characteristics have been obtained by performing
transient analysis of PLL implemented with each of the
designed VCOs and are presented in Fig.10. It can be inferred
from measured values given in Table I that the CSD VCO is
having lower locking time when compared with CSN VCO.

[6]

[7]

[8]

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