ANANTH SHETTY K R

Email: ananthsetty05@gmail.com
Mobile No: 8105010222

Objective
To become a more challenging full custom layout design engineer by becoming proficient in effective floor plan and
optimized layout designs in future technologies
Core Competencies

Worked on Custom layout design of 180nm, 90nm & 28nm technologies

Good understanding of transistor matching and common centroid techniques

Good exposure to technology by undergoing additional training in VLSI

Good understanding of fundamentals of Transistors and CMOS device operation

Basic understanding of Networking concepts like OSI model, network topology, multiplexing techniques
and error detection schemes

Good knowledge of Digital Design Concepts

Basic working Knowledge of Linux

Basic understanding of layout proximity effects such as WPE and LOD and DFM issues such as latch - up,
poly density etc

Education Profile

M.Tech - Industrial Electronics from SJCE, Mysore, Affiliated to VTU, 2015, with 8.48 CGPA (77.3%)

B.E Electronics and Communication Engineering (under VTU) from KLEIT, Hubli, 2012, with aggregate
of 70.12%

Senior Secondary Class 12 (PUC II), Fatima Composite PU College, Hubli, 2008, with aggregate of 78%

Class 10 (SSLC), Saint Andrews English Medium High School, Hubli, 2006, with aggregate of 82.24%

Experience
Trainee at RV-VLSI Design Center:
As a trainee for 6 months in RV-VLSI Design Center, I physically verified layouts for various standard cells in
180nm, 90nm and 28nm technology nodes of TSMC and Jazz semiconductor foundries respectively. Worked on
28nm 32x32 SRAM Memory Layout compiler where I was designing layouts of leaf cells.
Projects
RV-VLSI Design Center Projects
1) 9-Track Standard Cell Library Design using 90nm CMOS Technology
Project Deliverables:
Understanding the JAZZ PDK document, achieving LVS free Layout and making the layout more effective

keeping in mind the performance of the standard cell, and gaining the knowledge about compatibility rules
(Track height, pin placement, area).
Tools Used:
IC studio: Mentor Graphics
Pyxis: Schematic and Layout editor
Calibre RVE: DRC & LVS check
Challenges Faced:
1. Fitting the complete layout within the PR-Boundary maintaining all DRC rules
2. Solving LVS related errors such as nets and instances
3. Reducing the parasitics by making use of metal over poly
4. Placement of pins on horizontal and vertical grids
5. Routing using only one metal layer
2) Two Stage Differential Amplifier Layout Design using 180nm Technology
Project Deliverables:
Design layout of op-amp with dummy placements of transistors, with different transistor matching techniques
implementing any one of them and with different floor plans. Sitting of guard rings around active transistors and
following transistor fingers to reduce area.
Tools Used:
IC studio: Mentor Graphics.
Pyxis: Schematic and Layout editor.
Calibre RVE: DRC & LVS check.
Challenges Faced:
1. Understanding and making use of device matching techniques
2. Placement of dummy transistors for minimum mismatch
3. Using common centroid technique to get layout in square shape
4. To overcome Latch-up & Electro Migration problem
5. Maintaining the optimum metal spacing to avoid cross talk
3) Design of 6-Transistor SRAM Memory Compiler using 28nm Technology Leaf Cells
Project Deliverables:
Layout design of Pre-charge block with MUX factor 4 within the given boundary, layout design of Sense
amplifier block using common centroid techniques and designing the layout of the other blocks such as
decoders, controller etc by making use of given constraints in the project.
Tools Used:
IC studio: Mentor Graphics.
Pyxis: Schematic and Layout editor.
Calibre RVE: DRC & LVS check.
Challenges Faced:
1. Designing the floor plan of the whole layout in the given area

2. Placement of poly and contact on grids

3. Placement of pins for easy connection when we abut with the neighboring blocks
4. Routing using M1, M3 horizontally and M2 vertically
5. Avoiding poly routing to reduce parasitics
4) A Robust Algorithm for Text Detection in Complex Background Images
Project Deliverables:
1. Detects text of varying sizes, different background, different languages and orientation
2. Perform Edge Box filtering to filter out the non-text regions
3. To binarize the image by employing connected component analysis
Tool Used:
MATLAB - Version 8.5 and Release R2015a
Challenges Faced:
1. Detecting the text which is partially occluded
2. Detecting the text on images where text components are stuck together
3. Detecting the text on images with varying illumination
4. Detecting the text when the background of the image is textured
5) Blind Navigation and Safety using GSM Modem
Project Deliverables:
1. Gas leakage sensing
2. Fire Sensing
3. Door Break Detection
4. Obstacle Detection and
5. Outdoor navigation system for blind pedestrians
Tools Used:
ST-TX01 ASK Tx Module, ST-RX01 ASK Rx Module, HT12E Encoder, HT12D Decoder, MAX 232, APR9600
Voice Processor, GSM Modem, Keil uVision 3.2, Embedded C.
Challenges Faced:
1. Maintaining the proper range of distance to receive signals
2. Maintaining the proper delay between the message segments so that the message is received quickly and
appropriately