ANANTH SHETTY K R

Email: ananthsetty05@gmail.com
Mobile No: 8105010222

Objective
To become a more challenging full custom layout design engineer by becoming proficient in effective floor plan and
optimized layout designs in future technologies.
Core Competencies

Worked on Custom layout design of 180nm, 90nm & 28nm technologies

Good understanding of full custom/analog flow

Good understanding of CMOS fabrication process

Knowledge of Layout development and Verification (DRC,LVS& Parasitic Extraction)

Exposure to designing the layouts for standard cells and analog blocks such as OPAMP using 90nm and
180nm technologies respectively

Exposure in designing the layout for SRAM Memory Compiler using 28nm technology

Exposure to different types of DRC and LVS errors such as shorts, opens, co-grid check, property errors,
device mismatch etc

Good understanding of transistor matching and common centroid techniques

Good understanding of SRAM operation

Good understanding of fundamentals of Transistors and CMOS device operation

Good knowledge of Digital Design Concepts

Basic working Knowledge of Linux

Basic understanding of layout proximity effects such as WPE and LOD and DFM issues such as latch - up,
poly density etc

Good knowledge on parasitics and their effects on performance

Education Profile

M.Tech - Industrial Electronics from SJCE, Mysore, Affiliated to VTU, 2015, with 8.48 CGPA (77.3%)

B.E Electronics and Communication Engineering (under VTU) from KLEIT, Hubli, 2012, with aggregate
of 70.12%

Senior Secondary Class 12 (PUC II), Fatima Composite PU College, Hubli, 2008, with aggregate of 78%

Class 10 (SSLC), Saint Andrews English Medium High School, Hubli, 2006, with aggregate of 82.24%

Experience
Trainee at RV-VLSI Design Center:
As a trainee for 6 months in RV-VLSI Design Center, I physically verified layouts for various standard cells in
180nm, 90nm and 28nm technology nodes of TSMC and Jazz semiconductor foundries respectively. Worked on
28nm 32x32 SRAM Memory Layout compiler where I was designing layouts of leaf cells.

Projects
RV-VLSI Design Center Projects
1) 9-Track Standard Cell Library Design using 90nm CMOS Technology
Project Deliverables:
Understanding the JAZZ PDK document, achieving LVS free Layout and making the layout more effective
keeping in mind the performance of the standard cell, and gaining the knowledge about compatibility rules
(Track height, pin placement, area).
Tools Used:
IC studio: Mentor Graphics
Pyxis: Schematic and Layout editor
Calibre RVE: DRC & LVS check
Challenges Faced:
1. Fitting the complete layout within the PR-Boundary maintaining all DRC rules
2. Solving LVS related errors such as nets and instances
3. Reducing the parasitics by making use of metal over poly
4. Placement of pins on horizontal and vertical grids
5. Routing using only one metal layer
2) Two Stage Differential Amplifier Layout Design using 180nm Technology
Project Deliverables:
Design layout of op-amp with dummy placements of transistors, with different transistor matching techniques
implementing any one of them and with different floor plans. Sitting of guard rings around active transistors and
following transistor fingers to reduce area.
Tools Used:
IC studio: Mentor Graphics.
Pyxis: Schematic and Layout editor.
Calibre RVE: DRC & LVS check.
Challenges Faced:
1. Understanding and making use of device matching techniques
2. Placement of dummy transistors for minimum mismatch
3. Using common centroid technique to get layout in square shape
4. To overcome Latch-up & Electro Migration problem
5. Maintaining the optimum metal spacing to avoid cross talk
3) Design and Verification of Leaf Cells for SRAM Memory Compiler using 28nm Technology
Project Deliverables:
Designing Leaf Cells for combinational circuits:
INVERTER: INVx1, INVx2. NAND: NAND2x1, NAND2x2, NAND2x4. NOR: NOR3x1, NOR3x2, NOR3x4.
AND: AND2x1, AND3x1. OR: OR3x1, OR3x2, OR3x4 and performing verification process of leaf cells by

DRC, LVS Check.

Tools Used:
IC studio: Mentor Graphics
Pyxis: Schematic and Layout editor
Calibre RVE: DRC & LVS check
Challenges Faced:
1. Placing contacts and polys on grid
2. Reducing the parasitics by making use of metal over poly
3. Reducing device parasitics by using more contacts
4. Routing using only one metal layer
4) Layout Design of SENSE AMPLIFIER block used in SRAM Memory Compiler using 28nm Technology
Project Deliverables:
Since the block is analog, the layout has to be designed by using different matching techniques and by sitting
guard rings around transistors. Use transistor folding to reduce area and obtain symmetry by using common
centroid technique.
Tools Used:
IC studio: Mentor Graphics.
Pyxis: Schematic and Layout editor.
Calibre RVE: DRC & LVS check.
Challenges Faced:
1. Proper pin placements so that it could be connected to other blocks of SRAM at the top level when we abut it
2. Placement of dummy transistors for minimum mismatch
3. Using common centroid technique by keeping width of the transistor same to get layout in square shape
4. To overcome Latch-up & Electro Migration problem
5) Design of 6-Transistor SRAM Memory Compiler using 28nm Technology Leaf Cells
Project Deliverables:
Layout design of Pre-charge block with MUX factor 4 within the given boundary, layout design of Sense
amplifier block using common centroid techniques and designing the layout of the other blocks such as
decoders, controller etc by making use of given constraints in the project.
Tools Used:
IC studio: Mentor Graphics.
Pyxis: Schematic and Layout editor.
Calibre RVE: DRC & LVS check.
Challenges Faced:
1. Designing the floor plan of the whole layout in the given area
2. Placement of poly and contact on grids
3. Placement of pins for easy connection when we abut with the neighboring blocks
4. Routing using M1, M3 horizontally and M2 vertically