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Micro Processor Design-Resumen
Micro Processor Design-Resumen
Unlike a dedicated or custom microprocessor that is capable of performing only one function, a general-purpose
microprocessor, such as the Pentium CPU, is capable of performing many different functions under the direction
of program instructions. Given a different instruction set or program, the general-purpose microprocessor will
perform a different function. However, a general-purpose microprocessor can also be viewed as a dedicated
microprocessor because it is made to perform only one function, and that is to execute the program instructions. In
this sense, we can design and construct a general-purpose microprocessor in the same way that we constructed the
dedicated microprocessors in the last chapter.
+1
PC
control
signals
Datapath
address
Memory
decode
execute
instruction1
execute
instructionn
status
signals
IR instruction
Datapath
for
executing
all the
instructions
control
signals
Output
Figure 12.1. Overview of a general-purpose microprocessor.
In designing a CPU, we must first define its instruction set, and how the instructions are encoded and executed.
We need to answer questions such as how many instructions do we want? What are the instructions? What operation
code (opcode) do we assign to each of the instructions? How many bits do we use to encode an instruction?
Once we have decided on the instruction set, we can proceed to designing a datapath that can execute all the
instructions in the instruction set. In this step we are creating a custom datapath, so we need to answer questions
such as what functional units do we need? How many registers do we need? Do we use a single register file or
separate registers? How are the different units connected together?
Creating the datapath for a general-purpose microprocessor is exactly the same as creating the datapath for a
dedicated microprocessor. However, in addition to being able to perform all the instructions in the instruction set,
there are other data operations and registers that must be included in the datapath for the general-purpose
microprocessor. These data operations and registers deal with how the general-purpose microprocessor fetches the
instructions from memory and executes them. In particular, there is a program counter (PC) that contains the
memory location of where the next instruction is stored. There is an instruction register (IR) for storing the
instruction being fetched from the memory. Each time an instruction is fetched from a memory location pointed to
by the PC, normally the PC must be incremented to the next memory location for the next instruction. Alternatively,
if the instruction is a jump instruction, the PC must be loaded with a new memory address instead.
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The control unit for a general-purpose microprocessor basically cycles through three main steps, usually
referred to as the instruction cycle: 1) fetches an instruction; 2) decodes the instruction; and 3) executes the
instruction. Each step is executed in one state of the finite-state machine. For step 3, each instruction is usually
executed in one clock cycle, although some memory access instructions may require two or more clock cycles to
complete, hence they may require several states for correct timing.
For fetching the instruction in step 1, the control unit simply reads the memory location specified by the PC,
and copies the content of that location into the instruction register (IR). The PC is then incremented by 1 (assuming
that each instruction occupies one memory location). For decoding the instruction in step 2, the control unit extracts
the opcode bits from the instruction register and determines what the current instruction is by jumping to the state
that is assigned for executing that instruction. Once in that particular state, the control unit performs step 3 by simply
asserting the appropriate control signals for controlling the datapath to execute that instruction.
Instructions for the program are usually stored in external memory, so in addition to the CPU, there is external
memory that is connected to the CPU via an address bus and a data bus. Hence, step 1 (fetch an instruction) usually
involves the control unit setting up a memory address on the address bus and telling the external memory to output
the instruction from that memory location onto the data bus. The control unit then reads the instruction from the data
bus. To keep our design simple, instead of having external memory, we will include the memory as part of the
datapath. This way, we do not have to worry about the handshaking and timing issues involved for accessing
external memory.
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not really necessary. It is only included just because a program should have an output instruction. The DEC A
instruction decrements the content of A by 1, and stores the result back into A. The JNZ (Jump Not Zero) instruction
tests to see if the value in A is equal to 0 or not. If A is equal to 0, then nothing is done. If A is not equal to 0, then
the last four bits of the instruction, designated as aaaa in the encoding, is loaded into the PC. The four bits, aaaa,
represent a memory address. When this value is loaded into the PC, we are essentially performing a jump to this new
memory address, since the value stored in the PC is the location for the next fetch operation. Finally, the HALT
instruction halts the CPU by having the control unit stay in the halt state indefinitely until reset.
Instruction
IN A
OUT A
DEC A
JNZ address
HALT
Encoding
011
100
101
110 aaaa
111
Operation
A input
output A
AA1
if (A != 0) then PC = aaaa
Halt
Comment
Input to A
Output from A
Decrement A
Jump to address if A is not zero
Halt execution
Notations:
A
= accumulator.
PC = program counter.
aaaa = four bits for specifying a memory address.
= dont cares.
Figure 12.2. Instruction set for the EC-1.
12.2.2 Datapath
Having defined the instruction set for the EC-1 general-purpose microprocessor, we are now ready to design the
custom datapath that will execute all the operations as defined by all the instructions. The custom datapath for the
EC-1 is shown in Figure 12.3.
The datapath can be viewed as having three separate parts: 1) for performing the instruction cycle operations of
fetching an instruction, and incrementing or loading the PC, 2) the memory, and 3) for performing the data
operations for all the instructions in the instruction set.
The portion of the datapath for performing the instruction cycle operations basically contains the instruction
register (IR), and the program counter (PC). The bit width of the instructions determine the size of the IR, whereas,
the number of addressable memory locations determines the size of the PC. For this datapath, we want a memory
with 16 locations, each being 8-bits wide, so we need a 4-bit (24 = 16) address. Hence, the PC is 4-bits wide, and the
IR is 8-bits wide. A 4-bit increment unit is used to increment the PC by 1. The PC needs to be loaded with either the
result of the increment unit, or the address from the JNZ instruction. A 2-to-1 multiplexer is used for this purpose.
One input of the multiplexer is from the increment unit, and the other input is from the four least significant bits of
the IR, IR3-0.
As mentioned in Section 12.1, to keep our design simple, instead of having external memory, we have included
the memory as part of the datapath. In this design, the memory is a 16 locations 8 bits wide read-only memory
(ROM). Since, the instruction set does not have an instruction that writes to memory, we only need a read-only
memory. The output of the PC is connected directly to the 4-bit memory address lines, since the memory location is
always determined by the content of the PC. The 8-bits memory output Q7..0 is connected to the input of the IR for
executing the instruction fetch operation.
The portion of the datapath for performing the instruction set operations includes the 8-bit accumulator A, and
an 8-bit decrement unit. A 2-to-1 multiplexer is used to select the input to the accumulator. For the IN A instruction,
the input to the accumulator is from the data input port, whereas for the DEC A instruction, the input is from the
output of the decrement unit, which performs the decrement of A. The output of the accumulator is directly
connected to the data output port, hence the OUT A instruction does not require any specific datapath actions.
Furthermore, with this direct connection, it is equivalent to always performing the OUT A instruction. The JNZ
instruction requires the 8-input OR gate connected to the output of the accumulator to test for the condition (A 0).
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The actual operation required by the JNZ instruction is to load the PC with the four least significant bits of the IR.
The HALT instruction also does not require any specific datapath actions.
The control word for this custom datapath has five control signals, IRload, PCload, INmux, Aload, and JNZmux.
The datapath provides one status signal, Aneq0, to the control unit. The control words for executing the instruction
cycle operations and the instruction set operations are discussed in the next section.
Input
IRload
IR7-5
D7-0
Load 8-bit register
Clear
IR
IR7-5 IR3-0
3
1
JNZmux
8
4
4
D3-0
Load 4-bit register
Clear PC
PC3-0
PCload
4-bit
increment
Q7-0
16 locations 8bits
ROM
Address3-0
INmux
Aload
Reset
Clock
D7-0
Load 8-bit register
Clear
A
A7-0
8
8
Aneq0
8-bit
decrement
Output
Instruction Cycle Operations
Memory
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In the five execute states corresponding to the five instructions, the appropriate control signals for the datapath
are asserted to execute that instruction. For example, the IN A instruction requires setting the INmux signal to a 1 for
the input multiplexer, and setting the Aload signal to a 1 to load the input value into A. Notice that in order for the
input instruction to read in the correct value, the input value must be set up first before resetting the CPU.
Furthermore, since the INPUT state does not wait for an Enter key signal, therefore, only one value can be read in,
even if there are multiple input statements. The DEC A instruction requires setting INmux to 0 and Aload to 1 so that
the output from the decrement unit is routed back to the accumulator, and gets loaded in.
The JNZ instruction asserts the JNZmux signal to route the four address bits from the IR to the PC. Whether the
PC actually gets loaded with this new address depends on the condition of the Aneq0 status signal. Hence, the
PCload control signal is asserted only if Aneq0 is a 1. By asserting the PCload signal conditionally depending on the
status signal Aneq0, the state diagram will require one less state, thus making the finite-state machine smaller, and
making it into a Mealy FSM. Otherwise, the FSM will need two states for the JNZ instruction: one state for asserting
the PCload signal when Aneq0 is true, and one state for de-asserting the PCload signal when Aneq0 is false.
Once the FSM enters the HALT state, it unconditionally loops back to the HALT state, giving the impression
that the CPU has halted.
The next-state / implementation table for the state diagram, and the three excitation equations as derived from
the implementation table are shown in Figure 12.4 (b) and (c) respectively. With eight states, three D flip-flops are
used for the implementation of the control unit circuit. Notice that the derivation of the excitation equations is fairly
straight forward since most of the entries in the table contain 0s. Only the decode state row contains different
values.
The output equations shown in Figure 12.4 (e) are derived directly from the output table in (d).
Finally, we can derive the circuit for the control unit based on the excitation equations and the output equations.
The complete control unit circuit for the EC-1 general-purpose microprocessor is shown in Figure 12.4 (f).
start
000
fetch
001
decode
010
IR[7..5] =
011
input
011
IR[7..5] =
100
output
100
IR[7..5] =
101
dec
101
IR[7..5] =
110
jnz
110
(a)
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IR[7..5] =
111
halt
111
Current State
Q 2Q 1Q 0
000 start
001 fetch
010 decode
011 input
100 output
101 dec
110 jnz
111 halt
D2 = Q2Q1Q0 + Q2'Q1Q0'IR7
D1 = Q2Q1Q0 + Q2'Q1Q0' (IR6IR5 + IR7IR6) + Q2'Q1'Q0
D0 = Q2Q1Q0 + Q2'Q1Q0' (IR6IR5 + IR7IR5) + Q2'Q1'Q0'
(c)
Control
Word
0
1
2
3
4
5
6
7
State
Q2Q1Q0
000 start
001 fetch
010 decode
011 input
100 output
101 dec
110 jnz
111 halt
IRload
0
1
0
0
0
0
0
0
PCload
0
1
0
0
0
0
if (Aneq0 = 1) then 1 else 0
0
INmux
0
0
0
1
0
0
0
0
Aload
0
0
0
1
0
1
0
0
(d)
IRload = Q2'Q1'Q0
PCload = Q2'Q1'Q0 + Q2Q1Q0' (Aneq0)
INmux = Q2'Q1Q0
Aload = Q2'Q1Q0 + Q2Q1'Q0
JNZmux = Q2Q1Q0'
Halt
= Q 2Q 1Q 0
(e)
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JNZmux
0
0
0
0
0
0
1
0
Halt
0
0
0
0
0
0
0
1
IRload
D2
Q2
Clk
Clear
PCload
Q'2
INmux
D1
Q1
Clk
Clear
Aload
Q'1
JNZmux
Halt
D0
Q0
Clk
Clear
Clock
Reset
Q'0
Aneq0
IR7
IR6
IR5
(f)
Figure 12.4. Control unit for the EC-1: (a) state diagram; (b) next-state / implementation table; (c) excitation
equations; (d) control word/output table; (e) output equations; (f) circuit.
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