TRNG I HC BCH KHOA H NI

VIN IN T - VIN THNG

TT NGHIP I HC
ti:

THIT K B TO XUNG CLOCK CHO H

THNG DELTA-SIGMA ADC

Sinh vin thc hin:

Nguyn Vn Quyt
Lp T3 K56

Ging vin hng dn: TS. Phm Nguyn Thanh Loan

H Ni, 12-2016

TRNG I HC BCH KHOA H NI

VIN IN T - VIN THNG

TT NGHIP I HC
ti:

THIT K B TO XUNG CLOCK CHO H

THNG DELTA-SIGMA ADC
Sinh vin thc hin:

Nguyn Vn Quyt
Lp T3 K56

Ging vin hng dn: TS. Phm Nguyn Thanh Loan

Cn b phn bin:

H Ni, 12-2016

nh gi quyn n tt nghip
(Dng cho ging vin hng dn)
Ging vin nh gi: TS.Phm Nguyn Thanh Loan
H v tn Sinh vin: Nguyn Vn Quyt MSSV: 20112054
Tn n: Thit k b to xung Clock cho h thng Delta-Sigma ADC
Chn cc mc im ph hp cho sinh vin trnh by theo cc tiu ch di y:
Rt km (1); Km (2); t (3); Gii (4); Xut sc (5)

1
2
3
4

5
6

10a

10b

C s kt hp gia l thuyt v thc hnh (20)

Nu r tnh cp thit v quan trng ca ti, cc vn v
cc gi thuyt (bao gm mc ch v tnh ph hp) cng nh
1 2 3
phm vi ng dng ca n
Cp nht kt qu nghin cu gn y nht (trong nc/quc t) 1 2 3
Nu r v chi tit phng php nghin cu/gii quyt vn
1 2 3
C kt qu m phng/thc nghim v trnh by r rng kt qu
1 2 3
t c
C kh nng phn tch v nh gi kt qu (15)
K hoch lm vic r rng bao gm mc tiu v phng php
thc hin da trn kt qu nghin cu l thuyt mt cch c h 1 2 3
thng
Kt qu c trnh by mt cch logic v d hiu, tt c kt
1 2 3
qu u c phn tch v nh gi tha ng.
Trong phn kt lun, tc gi ch r s khc bit (nu c) gia
kt qu t c v mc tiu ban u ra ng thi cung cp
1 2 3
lp lun xut hng gii quyt c th thc hin trong
tng lai.
K nng vit (10)
n trnh by ng mu quy nh vi cu trc cc chng
logic v p mt (bng biu, hnh nh r rng, c tiu , c
nh s th t v c gii thch hay cp n trong n,
1 2 3
c cn l, du cch sau du chm, du phy v.v), c m u
chng v kt lun chng, c lit k ti liu tham kho v c
trch dn ng quy nh
K nng vit xut sc (cu trc cu chun, vn phong khoa
1 2 3
hc, lp lun logic v c c s, t vng s dng ph hp v.v.)
Thnh tu nghin cu khoa hc (5) (chn 1 trong 3 trng hp)
C bi bo khoa hc c ng hoc chp nhn ng/t gii
SVNC khoa hc gii 3 cp Vin tr ln/cc gii thng khoa
5
hc (quc t/trong nc) t gii 3 tr ln/ C ng k bng
pht minh sng ch
c bo co ti hi ng cp Vin trong hi ngh sinh vin
2
nghin cu khoa hc nhng khng t gii t gii 3 tr

4 5
4 5
4 5
4 5

4 5
4 5

4 5

4 5

4 5

ln/t gii khuyn khch trong cc k thi quc gia v quc t

khc v chuyn ngnh nh TI contest.
10c Khng c thnh tch v nghin cu khoa hc
im tng

0
/50

im tng quy i v thang 10

3. Nhn xt thm ca Thy/C
..................................................................................................................................
.......................................................................................................................................
.......................................................................................................................................
.......................................................................................................................................
.......................................................................................................................................
..................................................................................................

Ngy:

/201

Ngi nhn xt
(K v ghi r h tn)

nh gi quyn n tt nghip
(Dng cho cn b phn bin)
Ging vin nh gi:
H v tn Sinh vin: Nguyn Vn Quyt MSSV: 20112054
Tn n: Thit k b to xung Clock cho h thng Delta-Sigma ADC
Chn cc mc im ph hp cho sinh vin trnh by theo cc tiu ch di y:
Rt km (1); Km (2); t (3); Gii (4); Xut sc (5)

1
2
3
4

5
6

10a

10b

C s kt hp gia l thuyt v thc hnh (20)

Nu r tnh cp thit v quan trng ca ti, cc vn v
cc gi thuyt (bao gm mc ch v tnh ph hp) cng nh
1 2 3
phm vi ng dng ca n
Cp nht kt qu nghin cu gn y nht (trong nc/quc t) 1 2 3
Nu r v chi tit phng php nghin cu/gii quyt vn
1 2 3
C kt qu m phng/thc nghim v trnh by r rng kt qu
1 2 3
t c
C kh nng phn tch v nh gi kt qu (15)
K hoch lm vic r rng bao gm mc tiu v phng php
thc hin da trn kt qu nghin cu l thuyt mt cch c h 1 2 3
thng
Kt qu c trnh by mt cch logic v d hiu, tt c kt
1 2 3
qu u c phn tch v nh gi tha ng.
Trong phn kt lun, tc gi ch r s khc bit (nu c) gia
kt qu t c v mc tiu ban u ra ng thi cung cp
1 2 3
lp lun xut hng gii quyt c th thc hin trong
tng lai.
K nng vit (10)
n trnh by ng mu quy nh vi cu trc cc chng
logic v p mt (bng biu, hnh nh r rng, c tiu , c
nh s th t v c gii thch hay cp n trong n,
1 2 3
c cn l, du cch sau du chm, du phy v.v), c m u
chng v kt lun chng, c lit k ti liu tham kho v c
trch dn ng quy nh
K nng vit xut sc (cu trc cu chun, vn phong khoa
1 2 3
hc, lp lun logic v c c s, t vng s dng ph hp v.v.)
Thnh tu nghin cu khoa hc (5) (chn 1 trong 3 trng hp)
C bi bo khoa hc c ng hoc chp nhn ng/t gii
SVNC khoa hc gii 3 cp Vin tr ln/cc gii thng khoa
5
hc (quc t/trong nc) t gii 3 tr ln/ C ng k bng
pht minh sng ch
c bo co ti hi ng cp Vin trong hi ngh sinh vin
2
nghin cu khoa hc nhng khng t gii t gii 3 tr

4 5
4 5
4 5
4 5

4 5
4 5

4 5

4 5

4 5

ln/t gii khuyn khch trong cc k thi quc gia v quc t

khc v chuyn ngnh nh TI contest.
10c Khng c thnh tch v nghin cu khoa hc
im tng

0
/50

im tng quy i v thang 10

3. Nhn xt thm ca Thy/C
..................................................................................................................................
.......................................................................................................................................
.......................................................................................................................................
.......................................................................................................................................
.......................................................................................................................................
..................................................................................................

Ngy:

/201

Ngi nhn xt
(K v ghi r h tn)

LI NI U
Vic truyn dn tn hiu truyn thng hin nay hu ht c thc hin theo cc
phng php s. Trong khi tn hiu t nhin (thoi, s liu, hnh nh,) li bin
thin lin tc theo thi gian, ngha l tn hiu t nhin tn ti dng tng t. Chnh
v vy, cn phi c mt mch chuyn i cc tn hiu tng t ny sang dng s
c th x l c trn cc h thng s, c gi l mch chuyn i tng t - s
(ADC: Analog to Digital Converter), v cc mch chuyn i t tn hiu s sang dng
tng t (DAC: Digital to Analog Converter). Mt trong cc loi ADC c hiu sut
cao ang c nghin cu v pht trin hin nay l Delta-Sigma ADC ( ADC).
Cc tn hiu sau khi i qua khi ADC i hi phi t c lng nhiu nh
hng n tn hiu t nht c th. Mt trong nhng yu t t c iu l cc
xung Clock cung cp cho b chuyn i ADC phi c chnh xc cao. Chnh v
vy, em la chn ti Thit k b to xung Clock cho b chuyn i tng t-s
Delta-Sigma ADC lm n tt nghip vi hi vng s hiu hn v h thng ADC
v trau di thm kin thc v thit k mch trong cng ngh CMOS.
Bo co gm c ba phn: phn u gii thiu tng quan v b chuyn i tng
t - s ADC; phn hai gii thiu v MOSFET, cc loi flip-flop v cc cng logic
Tranmission Gate; phn ba trnh by v qu trnh thit k khi Clock v a ra kt
qu m phng ca mch.
Em xin chn thnh cm n TS.Phm Nguyn Thanh Loan tn tnh gip em
em c th hon thnh n tt nghip ny mt cch hiu qu nht.

TM TT N
Bo co gm c ba phn. Phn u gii thiu khi qut v ADC bao gm cc
nh ngha quan trng nh Oversampling, Noise Shaping, Dynamic Range v cc
thng s nh gi ca mt khi ADC nh t s tn hiu trn nhiu SNR, SNDR,
SQNR Phn hai s gii thiu v cc c tnh ca MOSFET cng c cp ti,
bn cnh s i su vo phn tch nhng li th ca Dynamic Transmission Gate
(DTG) flip-flop so vi nhng loi flip-flop thng thng khi hot ng tn s cao.
Phn ba trnh by nguyn l hot ng ca tng khi trong b to xung Clock (Clock
Generator) a ra kt qu m phng, phn tch chng nh gi mch thit k.

ABSTRACT
To improve the performance of ADC, signals are required to have the smallest
rate of noise by ameliorating the accuracy of clocks which still a remaining problem
owing to the difference between the input frequencies. My thesis will concentrate on
the topic Design a high accuracy clocks generator for Delta-Sigma ADC with three
chapters. Chapter one informs primary definitions about ADC such as
Oversampling, Noise Shaping, Dynamic Range and specification parameters like
Signal to Noise Ratio SNR, Signal to Noise-plus-Distortion Ratio SNDR,
Spurious-Free Dynamic Range SFDR Chapter two introduces the overview of
CMOS Technology, MOSFET characterizes and analyzes advantage of Dynamic
Transmission Gate (DTG) flip-flop compare to other flip-flops when actives in high
frequencies. Operating principle and proposed structure of each subsystem are
mentioned in chapter three along with several significant attentions in design
processing to obtain the target of duty-cycle and synchronization between output
clocks.

MC LC
LI NI U ........................................................................................................1
TM TT N .................................................................................................2
MC LC ..............................................................................................................3
DANH SCH HNH V ........................................................................................6
DANH SCH BNG BIU ..................................................................................8
DANH SCH T VIT TT ................................................................................9
Chng 1.
1.1.

B Chuyn i Tng T-S Delta-Sigma ADC .........................10

Gii thiu v ADC ................................................................................10

1.1.1.

nh ngha ADC ............................................................................10

1.1.2.

Phn loi ADC ...............................................................................10

1.2.

Nguyn l hot ng chung ca h thng delta-sigma ADC. ..............12

1.2.1.

Sampling v Oversampling ............................................................13

1.2.2.

Lng t ha (Quantization) .........................................................13

1.2.3.

Noise-shaping.................................................................................14

1.3.

Cc thng s nh gi hiu nng ca ADC .....................................15

1.3.1.

T s tn hiu trn nhiu SNR (Signal to Noise Ratio) .................15

1.3.2.

Signal to Noise and Distortion Ratio (SNDR) ...............................16

1.3.3.

Dynamic Range (DR).....................................................................16

1.3.4.

Effective Number of Bits (ENOB). ...............................................16

1.4.

Single Stage Delta-sigma Modulator ....................................................17

1.4.1.

First Order Delta-sigma Modulator (MOD1) ................................17

1.4.2.

High Order Delta-sigma Modulator (MODN) ...............................18

1.5.

Tnh n nh ca Delta-sigma ADC .....................................................21

1.5.1.

Single bit modulator .......................................................................21

1.5.2.

Multi bit modulator ........................................................................21

1.6.

Kt lun chng ....................................................................................22

Chng 2.
2.1.

MOSFET V Flip-Flop ..................................................................23

Gii thiu v MOSFET. ........................................................................23

2.1.1.

Cu to ca N-MOSFET. ...............................................................23

2.1.2.

c tnh ca N-MOSFET ..............................................................24

2.2.

Gii thiu v Flip-Flop .........................................................................27

2.2.1.

nh ngha v phn loi. ................................................................27

2.2.2.

D flip-flop. .....................................................................................28

2.3.

Kt lun chng. ...................................................................................30

Chng 3.

B To Xung Clock Cho Khi Delta-sigma ADC ........................31

3.1.

Cc thng s k thut............................................................................31

3.2.

Tng quan h thng ..............................................................................33

3.3.

Khi DIV1_2 v khi LO_GEN ...........................................................34

3.4.

Khi LF_GEN.......................................................................................36

3.4.1.

Khi Divider ..................................................................................36

3.4.2.

Nguyn l to 2 v 3 ..................................................................37

3.4.3.

Nguyn l to 1 v 4 ..................................................................38

3.5.

Kt qu m phng .................................................................................39

3.5.1.

So snh kt qu gia DTG flip-flop v flip-flop thng thng .....39

3.5.2.

Kt qu m phng ton mch. .......................................................40

3.6.

Tm tt kt qu t c ......................................................................46

3.7.

Kt lun chng. ...................................................................................47

Kt Lun ...............................................................................................................48
4

Ti Liu Tham Kho .............................................................................................49

DANH SCH HNH V

Hnh 1.1 Cu trc n gin ca Flash ADC .............................................................10
Hnh 1.2 Cu trc SAR ADC ....................................................................................11
Hnh 1.3 First order delta-sigma modulator ..............................................................11
Hnh 1.4 Delat-sigma modulator, (a). S khi, (b). M hnh tuyn tnh .............12
Hnh 1.5 M hnh nhiu trng ca tp m lng t. (a). B lng t, (b). M hnh
tuyn tnh, (c). Hm phn b xc sut, (d). Mt ph cng sut PSD ...................13
Hnh 1.6 M hnh ADC trong min Z ..................................................................14
Hnh 1.7 Quantization noise shaping ........................................................................15
Hnh 1.8 First order ADC modulator ...................................................................18
Hnh 1.9 Noise shaping ca MOD1 ..........................................................................18
Hnh 1.10 M hnh Nth order delta-sigma modulator ...............................................18
Hnh 1.11 M hnh Loop Filter .................................................................................19
Hnh 1.12 Nosie shaping ca MOD2 ........................................................................20
Hnh 2.1 Cu trc ca N-MOSFET ..........................................................................23
Hnh 2.2 (a) MOSFET iu khin bi in p cc G, (b) s hnh thnh vng ngho,
(c) qu trnh o ngc bt u, (d) s hnh thnh ca lp o ngc. ...................24
Hnh 2.3 Knh dn vi VDS > 0.................................................................................25
Hnh 2.4 th theo VDS ca ID vng tuyn tnh ..................................................26
Hnh 2.5 th theo VDS ca ID vng bo ha ......................................................26
Hnh 2.6 Cu trc ca D flip-flop .............................................................................29
Hnh 2.7 Dynamic Transmission Gate flip-flop........................................................30
Hnh 3.1 Thit k nhnh I ca khi ADC MOD4 ................................................31
Hnh 3.2 S tng qut v th m t trong trng hp TS = 2TLO ....................33
6

Hnh 3.3 S khi bn trong ca h thng.............................................................34

Hnh 3.4 Cu trc khi DIV1_2 ................................................................................35
Hnh 3.5 u ra ca khi DIV1_2 ............................................................................35
Hnh 3.6 Cu trc khi Divider .................................................................................37
Hnh 3.7 Nguyn l to 2 v 3 ..............................................................................37
Hnh 3.8 Nguyn l to 1 v 4 ..............................................................................38
Hnh 3.9 Kt qu chia 2 tn s 800 MHz ...............................................................39
Hnh 3.10 Kt qu m phng chia 2 tn s 12 GHz ..............................................40
Hnh 3.11 Mch m phng ca b to xung clock ...................................................40
Hnh 3.12 Kt qu m phng 4 xung LO vi Clock 0.8 GHz ..................................41
Hnh 3.13 Kim tra sn ca LO vi Clock 0.8 GHz ..............................................42
Hnh 3.14 Kt qu m phng 4 pha nhnh I vi Clock 0.8 GHz ..........................42
Hnh 3.15 Kt qu m phng 4 pha nhnh Q vi Clock 0.8 GHz ........................43
Hnh 3.16 Kt qu m phng ng b gia LO v vi Clock 0.8 GHz ...............43
Hnh 3.17 Kt qu m phng 4 xung LO vi Clock 12 GHz ...................................44
Hnh 3.18 Kim tra sn ca LO vi Clock 12 GHz ...............................................44
Hnh 3.19 Kt qu m phng 4 pha nhnh I vi Clock 12 GHz ...........................45
Hnh 3.20 Kt qu m phng 4 pha nhnh I vi Clock 12 GHz ...........................45
Hnh 3.21 Kt qu m phng ng b gia LO v vi Clock 12 GHz ................46

DANH SCH BNG BIU

Bng 2.1 Bng trng thi ca D latch ...................................................................28
Bng 3.1 Thng s k thut ca LO .....................................................................32
Bng 3.2 Thng s k thut ca LF ......................................................................32
Bng 3.3 La chn h s chia N ...........................................................................36
Bng 3.4 So snh kt qu m phng v yu cu k thut ca LO .......................46
Bng 3.5 So snh kt qu m phng v yu cu k thut ca LF ........................47

DANH SCH T VIT TT

ADC

Analog to Digital Converter

SAR ADC Successive Approximation ADC

OSR

OverSampling Ratio

STF

Signal Transfer Function

NTF

Noise Transfer Function

SNR

Signal to Noise Ratio

DR

Dynamic Range

SNDR

Signal to Noise and Distortion Ratio

ENOB

Effective Number of Bits

MOSFET

Metal-Oxide Semiconductor Field-Effect Transistor

DTG

Dynamic Transmission Gate

Chng 1. B Chuyn i Tng T-S Delta-Sigma ADC

Chng ny s trnh by tng quan v ADC, cc khi nim c bn v i vo
phn tch trng hp n gin nht l Single Stage Delta-sigma Modulator. Cc thng
s nh gi v hot ng ca loi ADC ny cng s c cp ti trong chng
ny.
1.1.

Gii thiu v ADC

1.1.1. nh ngha ADC

ADC hay Analog-to-Digital Converter l mt mch tch hp c chc nng chuyn
i mt i lng vt l tng t lin tc no (thng l in p) sang gi tr s
biu din ln ca i lng . S chuyn i lin quan n vic lng t ha tn
hiu ng vo, do nht thit mc mt lng li. Thay v lm mt chuyn i duy
nht, ADC thc hin vic chuyn i theo nh k gi l mu ng vo (sample).
1.1.2. Phn loi ADC

Vref
R1

R3

+
-

+
-

Memory

R2

Vin

Bus
Data

+
-

R4

Hnh 1.1 Cu trc n gin ca Flash ADC

Ty vo cu trc ca tng ADC m ngi ta phn loi ADC ra thnh nhiu loi
khc nhau. Tuy nhin, hin nay c ba loi ADC c s dng ph bin l Flash
ADC, SAR ADC v Delta-Sigma ADC.

10

Flash ADC: l dng n gin nht, thc hin bng dy in tr phn p v cc

comparator in p. N l minh ha hot ng nhp cho hot ng ca ADC c
m t nh hnh 1.1 [1].
SAR ADC (Successive Approximation ADC): ADC ny c mt u im ln l
thi gian chuyn i ch t l thun vi s bit ca m s v thi gian ca thanh ghi
xp x lin tip ch khng ph thuc vo ln ca in p cn chuyn i. thc
hin qu trnh chuyn i, ngi ta cn t ln lt mi bit ca m s ln mt, bt
u t bit cao nht (MSB) [2]. S m t ADC kiu ny c m t hnh 1.2.

EOC

Clock

SAR
DN-1

DN-2

VREF

D2 D1 D0

DAC
Comparator
_
VIN

S/H

Hnh 1.2 Cu trc SAR ADC

_
Z-1

Z-1

DAC

Hnh 1.3 First order delta-sigma modulator

11

Delta-Sigma ADC: ADC loi ny s dng cu trc ca mt h thng , tn hiu

tng t i vo s c ly mu vi tn s cao hn rt nhiu so vi tn s Nyquist
yu cu (thng l 2N ln), tn hiu sau ly mu s c lng t ha to ra tn
hiu s. Cc bit s ny c hi tip li x l cng tn hiu ng vo. Qu trnh ny
lm cho nhiu sinh ra trong qu trnh lng t gim i rt nhiu. Cu trc n gin
nht ca mt khi ADC (First order delta-sigma modulator) c m t nh hnh
1.3 [3].
Nh vo nhng li th v mt lc v loi b nhiu m h thng ADC ang c
nghin cu v pht trin mnh m nht hin nay.
1.2.

Nguyn l hot ng chung ca h thng delta-sigma ADC.

B iu ch Delta-sigma bao gm vng hi tip m tnh ton sai lch gia tn

hiu c lng t trc , s dng loop-filter H(z) v tn s ly mu ln
a phn ln tp m lng t ra ngoi bng tn tn hiu. Tn hiu u ra s c i
qua b lc s lc lc ly tn hiu v loi b cc thnh phn khng mong mun.
M hnh hot ng chung ca h thng c th hin hnh 1.4

XS(n)

xf(t)

S/H

Y(n)
H(Z)

fS
a

DAC

gp

H(Z)

Y
+

b
Hnh 1.4 Delat-sigma modulator, (a). S khi, (b). M hnh tuyn tnh

12

1.2.1. Sampling v Oversampling

Ly mu l mt qu trnh chuyn i mt tn hiu lin tc thnh mt tn hiu ri
rc. Theo Nyquist, mt hm s tn hiu x(t) khng cha bt k thnh phn tn s no
ln hn hoc bng mt gi tr fm c th biu din chnh xc bng tp cc gi tr ca
n vi chu k ly mu T = 1/(2fm). Nh vy, tn s ly mu phi tha mn iu kin
fS 2fm = fN (fN c gi l tn s Nyquist).
Trong nhiu ng dng c yu cu cao v phn gii (c th l 18 hoc thm ch
20 bit). B chuyn i vi tn s Nyquist ch c th hot ng chnh xc trong cc
qu trnh tch hp v m. Nh vy, s chu k clock cn thit chuyn i mt mu
s l 2N chu k, iu ny lm cho qu trnh chuyn x l tn hiu tn rt nhiu thi
gian, khc phc hn ch ny, ngi ta s dng k thut Oversampling.
Oversampling l qu trnh ly mu s dng tn s ly mu (fS) ln hn rt nhiu
so vi tn s Nyquist (fN), t s fS/fN c gi l Oversampling-rate (OSR). i vi
mt b iu ch ADC gi tr OSR thng l t 8 n 512. Oversampling gip cho
h thng t c yu cu v phn gii v tuyn tnh vi tc x l nhanh
hn rt nhiu so vi qu trnh ly mu tn s Nyquist [4].
1.2.2. Lng t ha (Quantization)

Hnh 1.5 M hnh nhiu trng ca tp m lng t. (a). B lng t, (b). M

hnh tuyn tnh, (c). Hm phn b xc sut, (d). Mt ph cng sut PSD
13

Lng t ha l qu trnh phn loi mt mu tn hiu thnh mt trong cc mc

lng t nh trc. B iu ch Delta-sigma s dng lng t ha u, lng
cc v lm trn. Trong qu trnh lng t, li lng t sinh ra do s thay i ngu
nhin ca tn hiu v do mc lng t khng thch hp. Li lng t c th c m
hnh ha nh mt nhiu trng, gi l tp m lng t. M hnh nhiu lng t c
m t nh hnh 1.5.
Vi b lng t s dng B bit lng t ha, mc lng t =

1
2
1

vi XFS l

in p full-scale ca b lng t
Cng sut ca tp m lng t:
+/2

1
2
= () = =

12
2

/2

Mt ph cng sut ca tp m lng t:

() =

2
2
=

12

1.2.3. Noise-shaping.
Mt m hnh n gin ca h thng ADC min Z c m t nh hnh 1.6
E(z)
U(z)

1
Z-1

V(z)

Hnh 1.6 M hnh ADC trong min Z

T hnh 1.6 ta c th d dng tnh c:
V(z) = STF(z)U(z) + NTF(z)E(z).
Trong , STF(z) l hm truyn ca tn hiu (Signal Transfer Function), NTF(z)
l hm truyn ca nhiu (Noise Transfer Function).

14

Tp m lng t c hi tip v vng lp tip theo, khi i qua loop-filter H(z)

(

) mt ph cng sut ca tp m lng t s thay i:

() =

2
. |()|2
12

trng hp n gin nh hnh 1.6, ta c th tnh c NTF(z) = 1 z-1. Vi

OSR ln, |NTF(z)|2 rt nh tn s thp bn trong bng tn tn hiu (f<fBfS)
|

2 2
( )|

= |1

2 2
|

[2 sin ( )] 4. ( )2

Khi cng sut tp m lng t bn trong bng tn tn hiu c tnh nh sau

+

2
2

2
2
=
. |()|2 =
. 4. ( )2 =
.
12
12

12 3. 3

Thng thng, nu nh loop-filter c h s khuch i cao trong bng tn tn hiu,

nhiu lng t trong bng tn b suy gim mnh nh m t hnh 1.7, qu trnh
ny c gi l noise shaping

Hnh 1.7 Quantization noise shaping

1.3.

Cc thng s nh gi hiu nng ca ADC

1.3.1. T s tn hiu trn nhiu SNR (Signal to Noise Ratio)

T s cng sut tn hiu trn nhiu (Signal to Noise Ratio hay Signal to Noise Ratio
without harmonic) c xc nh bng t s gia cng sut tn hiu v cng sut tp
15

m. Trong iu ch Delta-Sigma, t s SNR c xc nh bng t s gia cng sut

tn hiu v cng sut tp m bn trong bng tn tn hiu (in-band noise) u ra, l
mt thng s quan trng dnh gi mt cch tng i cht lng ca b iu ch.
SNR =

Ps
PN(inband)

1.3.2. Signal to Noise and Distortion Ratio (SNDR)

T s SNDR l t s cng sut tn hiu mong mun trn cng sut cc thnh phn
khng mong mun, bao gm tp m v cc hiu ng phi tuyn. Trong iu ch DeltaSigma, mo hi (harmonic distortion) xy ra khi tn hiu u vo l tn hiu hnh sin
i qua b integrator.
=

() +

T s SNDR l thng s nh gi hiu qu ca b iu ch chnh xc hn t s

SNR v n tnh n cc hiu ng phi tuyn m gy ra tp m.
1.3.3. Dynamic Range (DR)
T s DR l t s gia cng sut tn hiu c bin ln nht m b iu ch c
th x l (full-scale) v cng sut tn hiu c bin nh nht m tn hiu khng b
nhm ln vi tp m (bin m cng sut tn hiu bng cng sut tp m).
DR =

Pfullscale
PN(inband)

1.3.4. Effective Number of Bits (ENOB).

ENOB l s bit hiu dng ca b iu ch, th hin phn gii ca b iu ch
bao gm tt c cc hiu ng phi tuyn. ENOB l thng s nh gi tc x l
ca cc phng php chuyn i ADC.
=

1.76
6.02

16

1.4.

Single Stage Delta-sigma Modulator

1.4.1. First Order Delta-sigma Modulator (MOD1)

B iu ch Delta-sigma bc 1 (MOD1) bao gm 1 vng lp feedback, 1 khi
integrator v mt b lng t ha c th hin hnh 1.8.
() = () (). 1 + (). 1
()(1 1 ) = () (). 1
[ () ()]. (1 1 ) = () (). 1
() = () + (). (1 1 ).
Hm truyn t ca tn hiu:

() = 1 v hm truyn t ca tp m:

() = 1 1 . Vi OSR ln, |()|2 rt nh tn s thp bn trong bng

tn tn hiu ( < ):
|

2 2
( )|

= |1

2 2
|

2
2
)
[2 sin ( )] 4. (

Qu trnh noise shaping ca MOD1 c th hin hnh 1.9

Cng sut ca tp m lng t bn trong bng tn tn hiu:
+

2
2

2
=
. |()| =
. 4. ( )2
12
12

2
2
.
12 3. 3

Vi b iu ch s dng mt bit lng t, cng sut tn hiu:

(/2)2 2
=
=
2
8
T s cng sut tn hiu trn tp m:
=

()

9. 3
2. 2

17

U(z)

V(z)

Y(z)

_
Z-1
E(z)
+

Z-1
Hnh 1.8 First order ADC modulator

Hnh 1.9 Noise shaping ca MOD1

1.4.2. High Order Delta-sigma Modulator (MODN)
B iu ch Delta-Sigma bc N (MODN) bao gm N integrator, N vng lp
feedback ti cc integrator v 1 b lng t ha. c m t nh hnh di

N Integrators
(N-1) non-delaying, 1 delaying
U

+
-

Z
Z-1

+
-

Z
Z-1

+
-

1
Z-1

Hnh 1.10 M hnh Nth order delta-sigma modulator

Vi b iu ch Delta-Sigma bc cao, ta c th biu din m hnh tuyn tnh ca
b iu ch di dng m hnh Loop Filter nh hnh 1.11
18

E
U

L0 =

G
H
Y

Loop Filter
L1 =

V(z) = G(z)U(z)+H(z)E(z)

H-1
H

Hnh 1.11 M hnh Loop Filter

Vi m hnh tuyn tnh hnh 1.10, ta c:
( )
1
2

1
1 () =
=

1
2
( 1)
( 1)
( 1)
( )
1
z N1 + z N2 (z 1) + z N3 (z 1)2 + + (z 1)N1
(z 1)N

=
=

( 1 )

( 1)
( 1 )

( 1)

( 1 )

1
+1
(1 1 )

()
1
1
0 () =
=
=
() ( 1) (1 1 )
Mt khc, () = () () 1 () = 1

()
()

=1

1
()

() = () = (1 1 )
() = () = 0 (). () = 1
Nu OSR ln, |()|2 rt nh tn s thp bn trong bng tn tn hiu:
| (

)| = |1

2 2

[2 sin ( )]

22 . ( )2

19

Hnh 1.12 Nosie shaping ca MOD2

So snh hnh 1.12 vi hnh 1.9 cho thy noise shaping ca MOD2 tt hn MOD1
rt nhiu.
Cng sut tp m lng t trong bng tn tn hiu:
+

2
2

2
|
|
= =
. () =
. 22 . ( )2
12
12

2
2
=
.
12 (2 + 1). 2+1
Vi b iu ch s dng mt bit lng t, cng sut tn hiu:
(/2)2 2
=
=
2
8
T s cng sut tn hiu trn tp m:
=

()

3. (2 + 1). 2+1
2. 2

Da vo cng thc trn ta thy, SNR t l thun vi s bc ca b iu ch v t

s OSR, s bc v OSR cng cao thi SNR cng ln.

20

1.5.

Tnh n nh ca Delta-sigma ADC

i vi b iu ch Delta-Sigma, h thng c nh ngha l n nh khi tn hiu

u ra ca Loop-Filter c bin gii hn, hay ni cch khc l tn hiu u ra ca
Loop-Filter nm trong kh nng lm vic ca b lng t ha.
Trong b iu ch Delta-Sigma, tn hiu vo ca b lng t l tng ca tn hiu
u vo v tp m lng t c noise-shaping bi Loop-Filter:
[] = [] + [] ([] [])
Khi gi tr [] vt qu kh nng lm vic ca b lng t th b lng t b qu
ti (overload hoc saturation). S qu ti ny lm tng li lng t, lm trm trng
thm tnh trng qu ti ban u, dn n b lng t li tip tc qu ti v vng trn
lun qun ny cui cng dn n h thng tr thnh mt n nh (unstable).
1.5.1. Single bit modulator
i vi nhng b iu ch bc cao s dng 1 bit lng t, tiu chun c p
dng rng ri nht l tiu chun Lee (Lees rule):
Mt b iu ch Delta Sigma s dng 1 bit lng t vi hm truyn t ca tp
m () = () s n nh khi max|( )| < 1.5

Trong , max|( )| l gi tr ln nht ca H trong mi tn s, hay cn c

gi l infinity-norm ca H, k hiu l .
Mc d tiu chun Lee l mt tiu chun rt c ch trong vic d on tnh khng
n nh ca nhng b iu ch s dng 1 bit lng t, tuy nhin n khng c c s
l thuyt vng chc v cn phi c xc nhn bng m phng.
1.5.2. Multi bit modulator
i vi nhng b iu ch s dng lng t ha nhiu bit, kt qu tnh ton l
thuyt sau thng c s dng:
Xt b iu ch vi mt b lng t B-bit c s khong lng t = 2 , mc
lng t = 2, s mc lng t l M+1, v in p full-scale l 2M, khong lm vic

21

l [( + 1), + 1]. t gi tr u vo ban u (0) = 0 th b iu ch s khng

qu ti vi cc gi tr u vo tha mn:
max|()| + 2 1

trong 1 =
=0 |() | vi h(n) l bin i Z ngc ca hm truyn dt ca
tp m = ().
Ta c th chng minh kt qu trn mt cch n gin nh sau:
Da vo m hnh tuyn tnh ca b iu ch ta c:
() = () () = ()() + () () ()
Gi thit () l hm tr chu k, ta c:

( ) = ( ) +

()( ) ()

=0

cho b lng t khng qu ti th max|()| + 1. Trong trng hp xu

n

nht (worse-case) th max|()| = max|()| + max|()|. (1 1). Theo gi

n

thit ban u: = 2 max|()| = 1

n

max|()| = max|()| + 1 1 + 1
n

max|()| + 2 1
n

1.6.

Kt lun chng

Chng ny trnh by kh r rng v hot ng ca mt h thng ADC. Vi

vic s dng k thut Oversampling gip cho tc x l tn hiu nhanh hn so vi
nhng loi ADC khc. Hn na, qu trnh noise shaping gip cho tn hiu u ra
sch hn, s MOD cng cao th hiu qu ca noise shaping th hin cng r rng.
Tuy nhin, ngi thit k cng cn lu n n nh ca h thng la chn s
MOD hp l.

22

Chng 2. MOSFET V Flip-Flop

Trong chng ny, em s trnh by tng quan v MOSFET (transistor c s
dng thit k khi Clock). Ngoi ra, cc loi Flip-Flop v cc vn lin quan
cng c cp trong chng ny.
2.1.

Gii thiu v MOSFET.

MOSFET, vit tt ca Metal-Oxide Semiconductor Field-Effect Transistor, l

transistor hiu ng trng oxit kim loi bn dn, l mt thut ng ch cc transistor
hiu ng trng c s dng rt ph bin trong cc mch s v cc mch tng t.
Transistor MOSFET c xy dng da trn lp chuyn tip oxit kim loi v bn
dn (v d oxit Bc v bn dn Silic). MOSFET c hai loi l N-MOSFET v PMOSFET, hai loi ny c cu to v nguyn l hot ng ngc nhau, phn ny
ch ni v N-MOSFET
2.1.1. Cu to ca N-MOSFET.
Hnh 2.1 m ta cu trc ca N-MOSFET, trn nn cht bn dn loi P (c gi l
bulk hoc body), ngi ta pha hai vng bn dn loi N vi nng cao (N+), trn
ph mt lp mng SiO2. Hai dy dn xuyn qua lp cch in ni vo vng bn
dn N+ gi l cc S v D. Cc G c ly ra t kim loi tip xc bn ngoi lp oxit
SiO2 nhng cch in vi bn trong.
Poly
Oxide
S

n+
p-substrate

Leff
Ldrawn

n+
LD

Hnh 2.1 Cu trc ca N-MOSFET

23

Khong cch gia hai cc S v D c gi l chiu di, L, v chiu vung gc vi

L c gi l chiu rng, W. Trong thc t, khong cch gia S v D nh hn L,
khong cch c gi l Leff. Ta c Leff = Ldrawn 2LD, vi Ldrawn l tng chiu di,
LD l chiu di ca lp diffusion [5].
2.1.2. c tnh ca N-MOSFET
2.1.2.1.

in p ngng VTH

VG

VG
0.1V

n+

n+

p-substrate

0.1V
n+

n+

Negative Ions

p-substrate
(a)

(b)

VG

VG
0.1V

0.1V

Cox
n+

+
Cdep n

p-substrate

n+

-- -- -- -- -- -- -- -- -

p-substrate
(c)

(d)

n+

Electrons

Hnh 2.2 (a) MOSFET iu khin bi in p cc G, (b) s hnh thnh vng

ngho, (c) qu trnh o ngc bt u, (d) s hnh thnh ca lp o ngc.
Xt mt N-MOSFET c ni nh hnh 2.2(a), VG c cp tng dn t 0V. C
th thy cc G v cht nn hnh thnh mt t in, v VG tng dn t 0V nn cc l
trng ca cht nn loi p b y li ra xa cc G v li cc ion m, hay vng ngho
c to ra [hnh 2.2(b)]. Trong iu kin ny, khng c dng chy gia S v D v
khng c ht dn (cc ion cht rn khng th dn in).
V VG tng, lm cho dn hnh thnh hai t in ni tip nhau [hnh 2.2(c)]. Khi VG
tip tc tng, cc electron chy dn t cc S sang cc D. Do vy, mt knh dn
c hnh thnh bn di lp oxide gia S v D, lc ny transistor trng thi on.
Qu trnh ny gi l s o ngc [hnh 2.2(d)]. Gi tr ca VG nh nht c th lm
cho s o ngc ny xy ra gi l in p ngng VTH. Nu nh VG vn tip tc
24

tng, mt electron xut hin trn knh dn ngy cng ln, do lm cho dng xut
hin gia cc S v D tng ln [6].
2.1.2.2.

c tuyn I/V
VG

VD

--- -- - - - -

n+

0 x

p-substrate

n+
L

Hnh 2.3 Knh dn vi VDS > 0

Gi Qd l in tch ca t in gia cc G v cht nn. Nh vy Qd s c tnh
bng
Qd = WCox(VGS - VTH)
Gi s VDS > 0 nh c m t hnh 2.3. Gi Vx l in p ti im x, d dng
c th thy c Vx thay i t 0 ti VD khi x chy t 0 n L. Nh vy ta c th vit
Qd(x) = WCox[VGS V(x) VTH]
ID = WCox[VGS V(x) VTH]

()

Vi l linh ng ca bn dn loi N, ly tch phn hai v ta c

=
=0

W [ V(x) ]

=0

Hay
=

1 2
[( )
]

Hnh 2.4 m t th ca ID theo VDS, vng lm vic ca m VDS < VGS VTH
c gi l vng tuyn tnh (linear region hay triode region). Khi VDS = VGS
VTH, dng ID s t gi tr ln nht
=

( )2
2

25

ID
Triode
region

VGS3

VGS2
VGS3 - VTH

VGS2 - VTH

VGS1 - VTH

VGS1
VDS

Hnh 2.4 th theo VDS ca ID vng tuyn tnh

Trong thc t, dng ID khng theo hnh parabol khi VDS > VGS VTH m n c
dng nh hnh 2.5. Lc ny, dng ID gn nh l hng s mc d gi tr in p VDS
vn tip tc tng, vng lm vic ny c gi vng bo ha (saturation region) [7].

ID

VGS3
saturation
region

VGS2

VGS3 - VTH

VGS2 - VTH

VGS1 - VTH

VGS1

VDS

Hnh 2.5 th theo VDS ca ID vng bo ha

2.1.2.3.

Cc thng s khc ca MOSFET

Cng xem li cng thc tnh ID ca vng tuyn tnh

=

1 2
[( )
]

trng hp ny, nu nh VDS 2(VGS VTH) chng ta s c

=

( )

26

C th thy ID hon ton ph thuc tuyn tnh vo VDS, vng ny c gi l vng

tuyn tnh su (deep triode region) ca MOSFET. Nh vy, knh dn c th c coi
nh mt in tr ni gia S v D.
=

( )

Do , MOSFET c th hot ng nh mt in tr m gi tr ca n c th iu
khin c bng cch iu khin gi tr VGS VTH (c gi l overdrive voltage).
V MOSFET hot ng vng bo ha to ra mt dng p ng gi tr ca mc
in p overdrive voltage, chng ta c th nh ngha mt i lng biu l vic
MOSFET c th chuyn t p sang dng, gi tr ny c gi l h dn v k hiu
l gm. Gi tr ca gm c nh ngha nh sau
=

( )

Nh vy gm th hin linh ng ca MOSFET: vi gm cao, mt s thay i nh

ca VGS cng dn n s thay i ln ca ID v ngc li.
2.2.

Gii thiu v Flip-Flop

2.2.1. nh ngha v phn loi.

Flip-flop l mch c hai trng thi bn v c s dng lu tr thng tin trng
thi. Mt flip-flop l mt a hi n nh kp, mch ny thc hin x l trng thi ca
tn hiu ca mt hoc nhiu ng vo v cho kt qu ng ra. y l yu t c bn
lu tr trong logic tun t. Flip-flop v cht (latch) l mch xy dng c bn ca cc
h thng thit b in t k thut s, c s dng trong cc my tnh, truyn thng,
v nhiu loi khc ca h thng iu khin.
Da vo cu to v nguyn l hot ng, flip-flop c chia lm cc loi sau:
RS flip-flop: l mt a hi i, n gin nht, c hai ng vo R (Reset) v S (Set).
R v S ngc nhau v xung t nhau. Flip-flop RS c tch hp lm ng iu
khin trong nhiu Flip-flop cn li.
27

RSH flip-flop: l flip-flop RS c thm ng iu khin EN hay Gate. Khi EN l

active th m cho R hay S tc ng.
D flip-flop: l flip-flop ng b, khi CLK (Clock) tc ng th d liu D (Data)
chuyn ti ng ra Q
JK flip-flop: l flip-flop ng b. N x l gn nh flip-flop RS khi coi (J = Set,
K = Reset) v gii thc s kin (J = 1, K = 0 l lnh Set; J = 0, K = 1 l lnh Reset;
J = 1, K = 1 l lnh flip hay toggle).
T flip-flop hay flip-flop Toggle: thc hin i ngc ng ra khi c T chuyn sang
active hoc khi c CLK tc ng.
Trong cc khi hnh thnh b to xung Clock u ch s dng D flip-flop nn trong
phn ny em ch xin trnh by v D flip-flop.
2.2.2. D flip-flop.
Bng 2.1 Bng trng thi ca D latch
Clock

D flip-flop l mt loi flip-flop ng b. D li u vo D ch c chuyn ti u

ra Q ch khi c sn ln (i khi l sn xung) ca xung clock tc ng vo flipflop. Mt D flip-flop c to nn t hai b cht D latch ni tip nhau (b cht D
latch l mt mch gi trng thi u ra hot ng theo mc cao ca xung clock). Bng
trng thi ca D latch c m t bng 2.1. Da vo cu to m D flip-flop c
chia lm nhiu loi khc nhau, trong ph bin nht l D flip-flop logic c cu
to t cc cng logic c bn v DTG (Dynamic Transmission Gate) flip-flop.

28

2.2.2.1.

D flip-flop logic

IN

Q
D Latch

CLK

CLK

OutP

D Latch
Q

CLK

OutN

CLK

Hnh 2.6 Cu trc ca D flip-flop

Mt D flip-flop logic c to nn t hai D latch nh hnh 2.6. D latch u tin d
liu c a ra theo mc thp ca CLK (Clock), D latch tip theo d liu c a
ra theo mc cao ca CLK, t hnh thnh D flip-flop hot ng theo sn ln ca
CLK.
y l loi D flip-flop thng dng nht thng thy trong cc mch s thng
thng. Tuy nhin, nhc im ca loi flip-flop ny l c qu nhiu cng logic, dn
n tr u ra ln so vi u vo v thm na l cng sut ng (dynamic power)
tiu th ln, c bit l i vi cc mch hot ng tn s cao th cng sut ng
li chim a s. Trong khi , b chia Clock c thit k hot ng di tn t 0.8
GHz n 12 GHz nn flip-flop loi ny khng th s dng c.
2.2.2.2.

Dynamic Transmission Gate flip-flop

Cu trc ca mt DTG flip-flop gm c 2 cng logic NOT v 2 cng logic

Transmission Gate c m t hnh 2.7. Khi tn hiu Clock mc thp (CKP = 0,
CKN = 1) Transmission Gate th nht m, Transmission Gate th hai tt, tn hiu s
c a qua Transmission Gate th nht v np vo t u vo ca cng NOT th
hai. Khi tn hiu Clock chuyn sang mc cao (CKP = 1, CKN = 0) Transmission Gate
29

th nht ng, Transmission Gate th hai m, tn hiu c np trc i qua

Transmission Gate th hai v a ra u ra Q. Nh vy, gi tr ca Q ly gi tr ca
D theo sn ln ca Clock.

CKP

CKN

CKN

CKP

Hnh 2.7 Dynamic Transmission Gate flip-flop.

Chng ta c th thy flip-flop loi ny cha rt t MOS v cng logic so vi flipflop c gii thiu phn 2.2.2.1 nn cng sut tiu th s c ti u hn. Mt
khc cc Transmission Gate hot ng nh cc cng tc ng m (switch) nn tr
u ra so vi u vo ch l tr ca hai cng NOT, t hn rt nhiu so vi vic dng
cc cng logic to flip-flop. Flip-flop loi ny cng hot ng rt tt tn s cao
nh vo cu trc ca Transmission Gate. Tuy nhin, vic dng cu trc ny dn n
vic tn hiu s phi chu mt lng ln cc t k sinh. Do vy, i hi ngi thit
k phi la chn kch thc hp l gim thiu ti a gi tr ca cc t k sinh ny.
2.3.

Kt lun chng.

Trong chng ny, em trnh by kh r rng v cc kin thc c bn ca

MOSFET v cu trc, c tuyn I/V v cc tham s c trng ca MOSFET. V phn
flip-flop cng kh n gin c th hiu c cch thc hot ng ca loi linh
kin ny. Trong qu trnh thit k chng sau, i hi ngi thit k phi nm c
cc c im ca MOSFET v cch thc hot ng ca flip-flop trnh by trn.

30

Chng 3. B To Xung Clock Cho Khi Delta-sigma ADC

Trong chng ny, em s trnh by v qu trnh thit k b to xung Clock, nhng
nguyn l hot ng ca tng khi nh bn trong. Bn cnh , nhng lu v kh
khn d dng gp phi khi thit k cng c nu ra trong chng ny.
3.1.

Cc thng s k thut.

Mt h thng ADC gm c cc khi Integrator, khi Quantizer v khi DAC

nh c trnh by chng 1. Hnh 3.1 m t thit k c th cho mt h thng
ADC MOD4. Cc clock LO c to ra m bo cho hm truyn ca khi Npath Filter l tt nht, cc m bo cho vic np x ca cc t din ra mt cch hp
l.

Hnh 3.1 Thit k nhnh I ca khi ADC MOD4

B to xung y nhn mt tn hiu clock u vo c tn s fCLK thay i trong
khong 0.8GHz12GHz v 3 bit select S0, S1, S2 to ra 4 xung LO c tn s fLO
= 0.5fCLK v 8 pha (hay LF) c tn s c nh fS = 400MHz425MHz. Cc yu
cu k thut ca 4 xung LO v 8 pha c ln lt m t bng 3.1 v bng 3.2
vi iu kin m phng l TT/85oC.

31

Bng 3.1 Thng s k thut ca LO

Thng s

Gi tr

S pha

Duty-cycle

25%

Non-overlapping

YES

Mc cao

1.2V

Mc thp

0V

Sn ln

14 ps

Sn xung

14 ps

Khong tn s

400, 850, 1200, 2100, 2400, 3600, 4000, 6000 MHz

Bng 3.2 Thng s k thut ca LF

Thng s

Gi tr

S pha

Non-overlapping

YES

Mc cao

1.2 V

Mc thp

0V

Sn ln

100 ps

Sn xung

100 ps

Khong tn s

400425MHz, ng vi LO chia cho 1, 2, 3, 5, 6, 9,

10, 15.

Ngoi vic p ng cc thng s k thut hai bng trn, cc clock c to ra

cn phi tha mn v iu kin ng b. Hnh 3.2 m t r hn v iu ny.
Cc thng s trn hnh 3.2 c th c m t nh sau:
1: Sn ln, sn xung ca LO 14 ps
2: Duty-cycle ca LO = 25%
32

3: Sn ln, sn xung ca 2 3 100 ps

4: Tr ca 1I = 0.5TS 0.25TLO.
5: Tr ca 2I = 0.5TS
6: Tr ca 1Q = 0.5TS
7: Tr ca 2Q = 0.5TS + 0.25TLO
T y c th thy cc ca nhnh Q lun lun tr hn so vi cc ca nhnh I
l 0.25TLO. 4 ng b vi 3 theo sn ln, 1 ng b vi 3 theo sn xung,
ngoi ra sn ln ca 3I ng b vi sn ln ca LO_IP.

LO_IP
LO_QP
LO_IN
LO_QN

External clock
(0.812GHz)

Clock Generator

S0
S1
S2

1I
2I
3I
4I
1Q
2Q
3Q
4Q

Hnh 3.2 S tng qut v th m t trong trng hp TS = 2TLO

3.2.

Tng quan h thng

H thng c chia ra lm hai khi nh r rng l mt khi s to ra 4 tn hiu LO

cn mt khi s to ra 8 pha , ngoi ra s c mt khi to ra 4 tn hiu s b cho hai
khi ny (khi DIV1_2). Hnh 3.3 m t s khi bn trong ca h thng.

33

Hnh 3.3 S khi bn trong ca h thng

Hai tn hiu CKP v CKN l hai tn hiu c tn s bng nhau v bng tn s clock
u vo fCLK, tuy nhin hai tn hiu ny ngc pha nhau. c th to ra CKP v
CKN ch cn a tn hiu External Clock qua mt cng NOT to ra hai clock
ngc pha nhau.
Khi DIV1_2 c tc dng to ra 4 pha c tn s ch bng mt na tn s clock u
vo khi LO_GEN c th to ra 4 tn hiu LO yu cu.
Hai tn hiu QP v QN s ng vai tr l tn hiu clock ca khi LF_GEN, t
i qua b chia cng vi 3 bit select to ra tn s c nh 400425 MHz, 2 tn hiu
CKP v CKN ng vai tr quan trng trong vic ng b cc xung sau ny ca khi
LF_GEN.
3.3.

Khi DIV1_2 v khi LO_GEN

Nh trnh by trn, khi DIV1_2 c nhim v to ra 4 tn c tn s bng mt

na tn s u vo. Cu trc ca khi DIV1_2 thc cht l mt b chia 2 s dng
mt loi DTG flip-flop c m t nh hnh 3.4. Bn tn hiu c to ra sau b
DIV1_2 c lch pha nhau ln lt l 0o, 90o, 180o, 270o c th hin trn hnh
3.5

34

Hnh 3.4 Cu trc khi DIV1_2

Hnh 3.5 u ra ca khi DIV1_2

Cu trc trn hnh 3.4 cho php hai u ra QN v QP c tr so vi u vo l ging
nhau, vic ny cho php khi dng cc cng AND to ra 4 tn hiu LO s to ra
c 4 tn hiu c rng xung ging ht nhau. T cho thy t c dutycycle 25% c 4 tn hiu l tng i d dng. T hnh 3.5 cho thy to ra c
4 tn hiu LO chng ta ch cn dng php AND ln lt cc tn hiu nhnh I vi cc
tn hiu nhnh Q, c th nh sau: LO_IP = IN.QN; LO_QP = IP.QN; LO_IN = IP.QP;
LO_QN = IN.QP.

35

Kch thc cc cng AND phi c la chn mt cch ph hp c th t

c 25% duty-cycle.
3.4.

Khi LF_GEN

LF_GEN l khi to ra 8 pha c tn s c nh 400MHz425MHz. c th

to ra c tn s ny cn c mt khi Divider vi h s chia tn (N) khc nhau, 3
bit select S0, S1, S2 c tc dng chn la h s chia cho khi Divider. iu ny c
th hin bng 3.3.
Bng 3.3 La chn h s chia N
fCLK

fLO

(GHz)

(GHz)

0.8

fS

S0

S1

S2

0.4

400

1.7

0.85

425

2.4

1.2

400

4.2

2.1

420

4.8

2.4

400

7.2

3.6

400

8.0

4.0

10

400

12

6.0

15

400

(MHz)

3.4.1. Khi Divider

bng 3.3 c th thy cc h s chia u l bi ca 2, 3 v 5. Nh vy, c b
chia 6 ta s dng mt b chia 2 v mt b chia 3 ghp ni tip. Tng t nh vy, b
chia 9 l 2 b chia 3, chia 10 l chia 2 v chia 5, chia 15 l chia 3 v chia 5. Do ,
c th to ra khi Divider ta ch cn dng 1 b chia 2, 2 b chia 3 v 1 b chia 5.
Cu trc ca khi Divider c m t hnh 3.6

36

CLK_IN

Divider 2

Divider 3

Divider 3

Divider 5
CLK_O

Hnh 3.6 Cu trc khi Divider

Khi Divider s dng 4 b chia tn v 5 b Mux. Cc b Mux c cc chn iu
khin l mt hm logic ca S0 S1 v S2 u ra CLK_O tha mn v iu kin chia
tn c trnh by trn.
3.4.2. Nguyn l to 2 v 3
Hai tn hiu u ra ca khi DIV1_2 l QP, QN a qua b Mux chn la lm
clock u vo ca khi Divider. Vic a hai tn hiu ny qua b Mux gip cho s
ng b gia LO v LF d dng hn sau ny. Tn hiu sau khi i qua khi Divider c
tn s 400425MHz t c yu cu v tn s. Cc pha ca nhnh Q tr hn
nhnh I l 0.25TLO v cng l xung clock u vo. Ngoi ra, 2 tr hn so vi 3
l 0.5TS c th thy c 2 v 3 lch pha nhau 180o. Nh vy, to ra c cc
pha ny ta ch cn a tn hiu u ra ca khi Divider qua cc flip-flop vi clock l
CKP v CKN (hai clock ny c trnh by phn 3.2) nh hnh 3.7.

Hnh 3.7 Nguyn l to 2 v 3

trn hnh 3.7 cho thy, ngoi cc pha 2 v 3 ra cn xut hin thm tn hiu 2I
v 2Q. Hai tn hiu ny c dng to ra 1 v 4 s c trnh by phn sau.
Sau khi to ra c 2 v 3 ta c th d dng thy c 3I ng b vi clock u
vo. Phn 3.3 trnh by v nguyn l to LO cho thy LO_IP cng ng b vi clock
37

u vo. Tuy nhin, LO_IP ng b vi sn ln ca QN cn 3I th chng ta cha

th bit c xung ny ng b vi sn ln hay sn xung ca QN. Hai tn hiu
QP v QN ngc pha nhau v cng ng b vi clock, do vy, gi s nh mt tn
s no , QP sau khi i qua b Divider v qua hai fli-flop cho ra tn hiu c sn ln
ng b vi sn ln ca QN th chng ta s ly tn hiu ny l 3I. Ngc li, nu
tn hiu ny c sn xung ng b vi sn ln ca QN th chng ta s a tn hiu
QN qua v lm tn hiu to ra 3I. lm c iu ny, tn hiu iu khin ca b
Mux phi l mt hm ca 3 bit select S0, S1, S2. Nh vy, b Mux ng vai tr rt
quan trng trong vic ng b gia cc xung LO v LF.
3.4.3. Nguyn l to 1 v 4

1I

1Q

2I

2I

3I

3Q

2Q

2Q

4I

4Q

Hnh 3.8 Nguyn l to 1 v 4

c th to ra c 1 v 4, ta ch cn AND cc tn hiu li nh hnh 3.8. 1I
= 3I. 2I; 4I = 3I. 2Q; 1Q = 3Q. 2I; 4Q = 3Q. 2Q. Vic to ra 1 v 4
tng t nh vic to ra cc xung LO, cn phi lu n kch thc cc cng AND
c rng xung t nh yu cu. Do tn s ca 1 v 4 thp hn nhiu so vi
LO nn kch thc cng AND dng to ra 1 v 4 s khc so vi kch thc cng
AND dng to LO. iu ny l khng th trnh khi v hai loi AND lm vic
hai tn s hon ton khc nhau.

38

3.5.

Kt qu m phng

3.5.1. So snh kt qu gia DTG flip-flop v flip-flop thng thng

Nh trnh by phn 2.2, flip-flop thng thng cha nhiu cng logic hn so
vi DTG flip-flop, iu ny khin cho vic hot ng tn s cao ca flip-flop thng
thng khng c hiu qu nh DTG flip-flop. lm r kt lun ny, y em
s dng mt mch kim tra cho hai b chia 2 khc nhau, mt b c cu to t DTG
flip-flop v b cn li c to nn t flip-flop thng thng. Hnh 3.9 cho thy kt
qu hot ng ca hai b ny tn s Clock u vo thp (800 MHz), tn s ny,
kt qu chia 2 cho thy c hai mch u chy tt.

Hnh 3.9 Kt qu chia 2 tn s 800 MHz

Tuy nhin, khi chy tn s Clock cao (12 GHz) th flip-flop thng thng th
hin rt r rng khuyt im ca mnh, tn s ca u ra b sai lch rt nhiu v
duty_cycle cng khng c 50%, trong khi DTG flip-flop vn hot ng tt
(Hnh 3.10). iu ny cho thy s la chn DTG flip-flop thit k mch l hon
ton ng n.

39

Hnh 3.10 Kt qu m phng chia 2 tn s 12 GHz

3.5.2. Kt qu m phng ton mch.
Hnh 3.11 m t mch m phng ca b to xung clock. u vo ca khi clock
gm c mt tn hiu clock u vo ExtCLK v 3 bit select S0, S1, S2; mi u ra ca
b chia c ni vi mt khi buffer. Mch c thit k trn cng ngh CMOS
TSMC 65nm v c m phng trn phn mm Cadence vi iu kin m phng
85oC. Do mch test nhiu tn s khc nhau nn y ch a ra kt qu ca hai
trng hp clock u vo c tn s l 0.8 GHz v 12 GHz.

Hnh 3.11 Mch m phng ca b to xung clock

40

3.5.2.1.

Kt qu m phng vi tn s Clock u vo 0.8 GHz

Hnh 3.12 m t kt qu m phng ca 4 xung LO. Do mch m phng ch

transient (chy theo thi gian) nn kt qu m phng cn ly ti nhng thi im cui
ca qu trnh m phng m bo lc mch chy n nh. T hnh 3.12 cho
thy rng xung ca LO_IP v LO_IN tng i bng nhau ( 632.3 ps), rng
xung ca LO_QP v LO_QN cng vy ( 630.2 ps). Tuy rng cc xung LO nhnh I
v nhnh Q c rng xung lch nhau 2 ps, nhng gi tr ny l khng ng k, hn
na, cc xung nhnh I v nhnh Q s i theo 2 nhnh khc nhau nn vic cc xung
cng nhnh bng nhau quan trng hn nhiu so vi s khc nhau va I v Q.

Hnh 3.12 Kt qu m phng 4 xung LO vi Clock 0.8 GHz

Nh vy, tn s 0.8 GHz, cc xung LO t yu cu v rng xung (hay
duty-cycle). c th kim tra sn ca cc xung ny, chng ta thc hin php o
trn mt xung i din l LO_IP. Php o c thc hin o sn ln l t 10 mV
n 1.08 V v o sn xung l t 1.2 V n 119 mV. Hnh 3.13 cho thy sn ln
ca LO_IP l 10.9 ps v sn xung l 10.2 ps.

41

Hnh 3.13 Kim tra sn ca LO vi Clock 0.8 GHz

Kt qu m phng cc pha nhnh I v Q ln lt c m t hnh 3.14 v
hnh 3.15. C th d dng thy c tn s cc pha ny tha mn yu cu t ra
(400425 MHz). Ngoi ra, s ng b gia cc pha cng c th hin kh r rng
trn hai hnh.

Hnh 3.14 Kt qu m phng 4 pha nhnh I vi Clock 0.8 GHz

42

Hnh 3.15 Kt qu m phng 4 pha nhnh Q vi Clock 0.8 GHz

Hnh 3.16 m t s ng b gia LO_IP v 3I, ngoi ra, s tr pha gia 3I v
3Q cng c th hin trn hnh vi vic 3Q tr so vi 3I mt khong thi gian
ng bng rng xung ca LO_IP (0.25TLO).

Hnh 3.16 Kt qu m phng ng b gia LO v vi Clock 0.8 GHz

43

3.5.2.2.

Kt qu m phng vi tn s Clock u vo 12 GHz

Hnh 3.17 m t kt qu m phng ca LO vi tn s Clock 12 GHz, kt qu cho

thy h thng vn m bo c duty_cycle ca 4 tn hiu l 25%, rng xung ca
4 tn hiu tng i bng nhau (42.33 ps v 42.5 ps). Sn ca cc xung ny cng
c m bo nh hn 14 ps so vi thng s k thut a ra (hnh 3.18).

Hnh 3.17 Kt qu m phng 4 xung LO vi Clock 12 GHz

Hnh 3.18 Kim tra sn ca LO vi Clock 12 GHz

44

Hnh 3.19 Kt qu m phng 4 pha nhnh I vi Clock 12 GHz

Hnh 3.20 Kt qu m phng 4 pha nhnh I vi Clock 12 GHz

Kt qu m phng cc pha nhnh I v Q ln lt c th hin hnh 3.19 v
3.20, kt qu cho thy cc tn hiu vn p ng c yu cu v ng b gia cc
pha vi nhau khi mch hot ng tn s cao. Hnh 3.21 th hin s lch pha gia
nhnh I v Q, tiu biu y l 3I v 3Q, cng nh phn trc trnh by, 3Q
tr hn so vi 3I l 0.25TLO v p ng c yu cu t ra. Tuy nhin, chng ta c
th d dng nhn thy s ng b gia LO_IP v 3I hnh 3.21 khng cn c tt
45

nh khi mch hot ng tn s thp. y cng l kh khn trong qu trnh thit k

mch hot ng tn s cao.

Hnh 3.21 Kt qu m phng ng b gia LO v vi Clock 12 GHz

3.6.

Tm tt kt qu t c

Kt qu m phng cho LO, LF c so snh vi yu cu k thut ban u ra v

c trnh by ln lt bng 3.4 v 3.5
Bng 3.4 So snh kt qu m phng v yu cu k thut ca LO
Thng s

Gi tr yu cu

Kt qu m phng

S pha

Duty-cycle

25%

Non-overlapping

YES

Mc cao

1.2V

Mc thp

0V

Sn ln

14 ps

Sn xung

14 ps

t
46

Khong tn s

400, 850, 1200, 2100, 2400, t

3600, 4000, 6000 MHz

ng b vi

ng b tt c cc tn s

t tn s 4004000MHz,
lch 3 ps 6000 MHz

Bng 3.5 So snh kt qu m phng v yu cu k thut ca LF

Thng s

Gi tr yu cu

Kt qu m phng

S pha

Non-overlapping

YES

Mc cao

1.2 V

Mc thp

0V

Sn ln

100 ps

Sn xung

100 ps

Khong tn s

400425MHz, ng vi LO chia cho 1, t

2, 3, 5, 6, 9, 10, 15.

3.7.

Kt lun chng.

Chng ny trnh by kh r rng v nguyn l hot ng ca tng khi nh

hnh thnh b to xung clock. Cc kt qu ch ra rng b to xung p ng c
cc yu cu thit k t ra. Tuy rng tn s cao (12 GHz), kt qu v s ng b
vn cha c hon ho nh mong i, nhng cc sai s ny l nh v c th b qua
c khi so snh vi cc thng s m yu cu thit k t ra.

47

Kt Lun
B to xung clock c thit k to ra cc xung clock cho h thng ADC c
th hot ng ng chc nng nh yu cu ban u. Bo co trnh by kh r rng
v nguyn l hot ng ca mt h thng ADC, s khc nhau gia MOD1 v
MODn. Bn cnh , bo co cng gii thiu cu to v hot ng ca MOSFET
cng nh cc loi flip-flop c bn.
B to xung clock c thit k trn cng ngh CMOS TSMC 65nm v c m
phng bng phn mm Cadence. Cc kt qu ch ra rng thit k p ng c cc
yu cu v k thut khi hot ng tn s thp (0.44 GHz). Khi tn s cao (6
GHz), s ng b cn cha c m bo. Do vy, hng pht trin trong tng lai
s l tip tc ti u h thng v tin hnh layout.
Qua ti tt nghip ny, em phn no hiu hn v vic thit k cc h thng
IC tng t, c bit l thit k mch to xung clock cho di hot ng t 0.46
GHz. Mt ln na em xin chn thnh cm n TS.Phm Nguyn Thanh Loan tn
tnh gip em trong qu trnh lm n.

48

Ti Liu Tham Kho

[1]. http://www.allaboutcircuits.com/textbook/digital/chpt-13/flash-adc/, truy cp
cui cng ngy 30/12/2016.
[2]. Ali M.Zargar, Successive Approximation Analog to Digital Converter, San Jos
State University, April 30,2010.
[3]. Richard Schreier, Trevor Caldwell, ECE1371 Advanced Analog Circuits, Lecture
1, pp. 2-14.
[4]. Richard Schreier, Gabor C.Temes, Understanding Delta-Sigma Data Converters,
Wiley-Interscience, 2005.
[5]. Behzad Razavi, Design of Analog CMOS Integrated Circuits, Electrical
Engineering University of California, Los Angeles, 2001, pp. 10-11.
[6]. Behzad Razavi, Design of Analog CMOS Integrated Circuits, Electrical
Engineering University of California, Los Angeles, 2001, pp. 13-15.
[7]. Behzad Razavi, Design of Analog CMOS Integrated Circuits, Electrical
Engineering University of California, Los Angeles, 2001, pp. 15-22.

49