Professional Documents
Culture Documents
Section 11 1 Two Port Power Gains Package
Section 11 1 Two Port Power Gains Package
Section 11 1 Two Port Power Gains Package
1/2
Jim Stiles
Dept. of EECS
5/2/2007
1/14
Gain
Element
+
-
Vg
ZL
S21 > 1
Vg
Jim Stiles
+
-
Zg
Dept. of EECS
5/2/2007
2/14
Vg
Zg
+
-
Zin
ZL
Vg
+
-
Vout
+
-
Zout
Pavn available
power from the
output port
Jim Stiles
Dept. of EECS
5/2/2007
3/14
Zg
Vg
+
-
Vout
+
-
Zout
ZL
Jim Stiles
Dept. of EECS
5/2/2007
4/14
Ii
Vs
Zs
+
-
+
Vi
-
Z0
z = zs
Vs =Vi + Z s Ii
Whereas, from the telegraphers equations we know that:
Vi = V ( z = z s ) = V0+ e j zs + V0 e + j zs
V0+ j zs V0 + j zs
Ii = I ( z = z s ) =
e
e
Z0
Z0
Substituting the definitions:
as V0 e
+ j zg
bs V0+ e
j zg
we get:
Jim Stiles
Dept. of EECS
5/2/2007
5/14
Vi = V ( z = z s ) = bs + as
Ii = I ( z = z s ) =
bs
a
s
Z0 Z0
Vs = (bs + as ) +
Zs
(bs as )
Z0
And rearranging:
Vg + g a g
Z
Z
+
0
g
Z0
bg =
Zs Z 0
Zs + Z 0
(Doh!)
we find by rearranging:
Z0
1 s
=
2
Z0 + Zs
and so:
1 s
2
bs =
Jim Stiles
Vs + s as
Dept. of EECS
5/2/2007
6/14
Vs
bs
1 s
2
1 s
2
bs =
Vs + s as
as
Now, consider the case where we place a load (e.g., the input
impedance of a two port network) at this source port:
Vs
+
-
Zs
Zin
V0 e + j zs as Zin Z 0
in = + j zs =
=
V0 e
bs Zin + Z 0
Thus, the relationship as = in bs can be added to the signal
flow graph:
Vs
bs
1 s
2
in
as
Jim Stiles
Dept. of EECS
5/2/2007
7/14
Vs
1 s
2
bs
as
in
s in
Vs
1 s
1
2 (1 s in )
in
bs
as
bs =Vs
1 s
1
2 1 s in
as = Vs
1 s
in
2 1 s in
b
V
1 s
Pinc = s = s
2Z 0 8Z 0 1 s in
Jim Stiles
Dept. of EECS
5/2/2007
8/14
Pref
a
V
1 s
= s = s
2Z 0 8Z 0 1 s in
in
b as
= s
2Z 0
V
1 s
= s
8Z 0 1 s in
2
V
Z0
= s
2Z 0 Z 0 + Z s
(1 )
2
in
1 in
1 s in
1 s in
Jim Stiles
Dept. of EECS
5/2/2007
9/14
Pavs = Pin
in =s
2
V 1 s
= s
8Z 0 1 s
2
2
2
V
Z0
1
= s
2Z 0 Z 0 + Z s 1 s
=
1
Vs
2
4 Re {Z s }
Now, consider the case where we connect some arbitrary twoport device to the source. We would like to determine the
available power Pavn from the output port of this two-port
device.
Vs
+
-
Jim Stiles
Zs
Pavn =??
Dept. of EECS
5/2/2007
10/14
Vs
1 s
2
S21
a1
b2
S11
S22
S12
a2
b1
s S11
1 s
2
Vs
a1
s S12
S11
b2
a1
11
s S12
S11
1 s S11
S12
b1
Jim Stiles
a2
b1
11
1 s
1
2 1 s S
S22
S12
1 s S21
2 1 s S
Vs
b2
S21
s S12S21
1 s S11
S22
a2
Dept. of EECS
5/2/2007
11/14
1 s S21
2 1 s S
11
Vs
b2
a1
s S12
1 s
1
2 1 s S
1 s S11
11
S22 +
1 s S11
2 1 s S
b1
11
S12 +
s S12S11
s S12S21
1 s S11
a2
1 s S11
Vs
S22 +
s S12S21
1 s S11
a2
Notice this signal flow graph has the same form as the source
signal-flow graph:
Jim Stiles
Dept. of EECS
5/2/2007
Vs
1 s
2
12/14
bs
s
as
To make this comparison more specific, we define variables:
Vout Vs
1 s
S21
1 out 1 s S
11
out S22 +
s S12S21
1 s S11
And thus, using these definitions, our signal flow graph can be
equivalently written as:
Vout
b2
1 out
2
out
a2
It is apparent that Vout and out define an equivalent source
created when the original source is connected to a two-port
device.
Jim Stiles
Dept. of EECS
5/2/2007
13/14
Thus, when some load is connected to the output of the twoport device, the signal flow graph is:
Vout
b2
1 out
2
L
out
a2
Vs
bg
s
in
ag
As a result, the delivered power is precisely the same as the
original case, with the exception that we use the equivalent
values defined above:
2
b a2
PL = 2
2Z 0
V
1 out
2
1
= out
L
8Z 0 1 out L 2
2
1 s
V
S21
2
1
= s
L
8Z 0 1 s S11 2 1 out L 2
Jim Stiles
)
Dept. of EECS
5/2/2007
14/14
1 out L
Pavn = PL
L =*out
2
1 s
V
S21
= s
V
1 s
S21
= s
8Z 0 1 s S11 2 1
out
2
V
1 s
S21
= s
8Z 0 1 s S11 2 1 out
Jim Stiles
2 2
1 out
(1 )
out
2
2
Dept. of EECS
5/7/2007
1/4
Power Gain
G
PL
Pin
G =
=
=
=
=
Jim Stiles
PL
Pin
S21
1 s S11
S21
S21
1 in
1 L
1
1 s S11
1 s S11
1 s in
1
1 in
1 s S11 1 out L
1 s
1 s in
1 out L
1 L
1 out L
1 L
1 in
S21
1 out L
1 L
1 in
1 s
1 S22 L
1 S22 L
Dept. of EECS
5/7/2007
2/4
2.
1 s S11 1 out L
1 S22 L
Available Gain
GA
Pavn
Pavs
GA =
=
=
3.
Pavn
Pavs
S21
1 s
2
2
1 s S11 1 out
S21
1 s
1 s
1 s
2
2
1 s S11 1 out
Transducer Gain
GT
Jim Stiles
PL
Pavs
Dept. of EECS
5/7/2007
3/4
GT =
=
PL
Pavs
S21
1 s S11
S21 1 s
1 L
(1 ) 1
1 s in
2
2
1
2
S21 1 s
2
1 s
(1 )
S21
1 s
(1 )
2
1 out L
1 s
1
1 s in
1 LS22
1 out L 1 s S11
2
1 LS22
L
2
GT = S21
Jim Stiles
Dept. of EECS
5/7/2007
GT =
S21
(1 ) 1
s
1 s S11
4/4
1 LS22
L
2
GTU
* If you are inclined to be mischievous, ask an amplifier vendor if their gain spec.
is actually available gain or transducer gain.
Jim Stiles
Dept. of EECS
5/7/2007
1/9
and
L = out
.
Q: But what if this is not the case? What if our gain element
Q:
Jim Stiles
Dept. of EECS
5/7/2007
2/9
A: Not exactly.
Remember, it is true that a lossless matching network can
change the source impedance to match a specific load. But
the lossless matching network likewise alters the source
voltage Vs such that the available power is preserved!
Messing around directly with the source impedance will
undoubtedly reduce the available power of the source (this is
bad!).
For example, consider this simple problem. Say we have this
source, with a robust available power of 1.25 W:
Z s = 10
Pavs
Vs = 10V
Vs
=
8 Re {Z s }
102
=
8 (10 )
= 1.25 W
Z in = 50
Jim Stiles
Dept. of EECS
5/7/2007
3/9
10
40
Vs = 10V
Pavs
Vs
=
8 Re {Z s }
102
=
8 ( 50 )
= 0.25 W
Vs = 10V
1
2
PL = Vg
Z in = 50
Re {Z L }
Z g + ZL
102
50
=
2 (20 + 50 )2
502
=
702
= 0.51 W
Jim Stiles
Dept. of EECS
5/7/2007
4/9
10
50
50
10 5
Vs
+
-
Input
Matching
Network
Gain
Element
Output
Matching
Network
ZL
Dept. of EECS
5/7/2007
5/9
A Microwave
Amplifier
Input
Matching
Network
Gain
Element
Output
Matching
Network
+
-
Vg
Jim Stiles
Input
Matching
Network
Gain
Element
Output
Matching
Network
Z0
Dept. of EECS
5/7/2007
6/9
Vg
+
-
Vs
+
-
Zs
Z0
Z in
+ V
g
-
Jim Stiles
Vout
+
-
Z out
ZL
Z0
Dept. of EECS
5/7/2007
7/9
Z L = Zout
and so
L = out
And so, our amplifier design problem can be described as:
Z0
+
-
Vg
Vs
Zs
+
-
s = in
Gain
out
= L
Element
ZL
Z0
Vg
+
-
Jim Stiles
Vs
+
-
Zs
Gain
Element
out = S22 +
S12S21s
1 S11s
Dept. of EECS
5/7/2007
8/9
S11 +
S12S21L
= in
1 S22L
Gain
Element
ZL
Z0
matching network.
3. We cant determine the output matching network until we
determine out .
4. We cant determine out until we design the input
matching network.
5. But we cant design the input matching network until we
determine in !
Jim Stiles
Dept. of EECS
5/7/2007
9/9
.
and L = out
out
in
S12 = 0
S12 = 0
= S22 +
= S11 +
S12S21s
1 S11s
S12S21L
1 S22L
= S22
S12 = 0
= S11
S12 = 0
Jim Stiles
and
L = out
Dept. of EECS