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Vlsi Comple Lab Task
Vlsi Comple Lab Task
Vlsi Comple Lab Task
Write the VERILOG gate level module for OR, NOR, NAND, XOR and XNOR
Gates and verify its output using test bench waveforms. Also implement these
gates on trainer
CODE
module ex1(
input a,
input b,
output c,
output d,
output e,
output f,
output g,
output h
);
and(c,a,b);
nand(d,a,b);
or(e,a,b);
nor(f,a,b);
xor(g,a,b);
xnor(h,a,b);
endmodule
AND GATE
TRUTH TABLE
K-MAP
NAND
GATE
K-
TRUTH
OR
GATE
TRUTH
1
K-
NOR GATE
TRUTH
K-
XOR GATE
TRUTH
K-
XNOR GATE
KTRUTH
RTL SCHEMATIC
2
ISE SIMULATOR
WAVEFORM
Lab02
A)
1. Write Gate Level VERILOG module of the following circuits shown below:
module la2(
input a,
input b,
input c,
input d,
output e
);
wire g,h;
and (g,a,b);
and(h,c,d);
or(e,g,h);
endmodule
TRUTH
TABLE
Vlsi lab exam final
WAVEFOR
WAVEFOR
B)
module la2(
input a,
input b,
input c,
input d,
output e
);
wire g,h;
and (g,a,b);
and(h,c,d);
or(e,g,h);
Endmodule
TRUTH
TABLE
WAVEFOR
module la22(
input a,
input b,
input c,
output d
);
wire e,f,g,h,i;
not f1(i,a);
not f2(e,b);
not f3(f,c);
and (g,i,b,c);
and(h,e,f,a);
or(d,g,h);
endmodule
TRUTH
WAVEFOR
module la22(
input a,
input b,
input c,
input d,
output e
);
wire x,f,g,h,i,j,k;
not(x,a);
and(h,x,b,c,d);
not(f,b);
and(i,a,f,c,d);
and(j,a,b,c,d);
not(g,c);
and(k,a,b,g,d);
or(e,h,i,j,k);
endmodule
TRUTH
WAVEFOR
3. Design a circuit that could give a complete control mechanism for the
automatic home overhead water filling system. The system must check if
the upper tank is empty, if water lies in the lower tank it would turn on the
motor for the duration till either the upper tank is filled or the lower tank
gets empty. The tanks status and motor status must be represented by LEDs.
Write the VERILOG Gate Level module for the following logic, also write
the test bench to verify the output and implement this logic on trainer.
module la22(
input a,
input b,
output c
);
wire ap;
not (ap,a);
and (c,ap,b);
endmodule
WAVEFOR
Lab03
7
1. Write the VERILOG gate level module for OR, NOR, NAND, XOR and
XNOR Gates and verify its output using test bench and waveforms. Also
implement these gates on trainer.
module la3(
input a,
input b,
output c,
output d,
output e,
output f,
output g
);
assign c=(a|b);
assign d=~(a|b);
assign e=~(a&b);
assign f=(a^b);
assign g=~(a^b);
endmodule
OR GATE
TRUTH
NOR GATE
TRUTH
NOR GATE
TRUTH
XOR GATE
TRUTH
XNOR GATE
TRUTH
WAVEFOR
2. Write VERILOG module of the followings and Provide RTL Schematic and
Truth Table of the Above Circuits and also implement on trainer
module la3(
input a,
input b,
input c,
output d
);
wire x,y;
assign x=!a;
9
assign
y=(c|b);
assign d=(x&y);
endmodule
TRUTH
Vlsi lab exam final
WAVEFOR
module la33(
input a,
input b,
input c,
input d,
output e
);
wire x;
assign x=(a|b);
assign
e=(x&c&d);
endmodule
TRUTH
10
WAVEFOR
C)
module la33(
input a,
input b,
input c,
input d,
output e
);
wire x,y;
assign x=(a|b);
assign y=~(c|d);
assign e=(x&y);
endmodule
TRUTH
11
WAVEFOR
D)
module la33(
input a,
input b,
input c,
input d,
output e
);
wire x,y,z,t;
assign z=!b;
assign x=(a|z);
assign y=(c|d);
assign t=(x&y);
assign e=(t&d);
endmodule
TRUTH
WAVEFOR
3.
12
De
sign a circuit that could detect the status of the 3 landing gears of aircraft
and generate indications (LED) when all the gears are retracted, extracted,
and malfunctioned. Write the VERILOG Data Flow module for the
following logic, also write the test bench to verify the output and
implement this logic on trainer.
module la33(a, b, c,
d, e, f);
input a;
input b;
input c;
output d;
output e;
output f;
assign
d=(~a&~b&~c);
assign e=(a&b&c);
assign f=~(d^e);
endmodule
TRUTH
NAND
AND
13
WAVEFOR
Lab 04
1) Derive the expressions for S and Cout from the truth table of full
adder, write verilog code for the expressions, verify the results with a test
bench and then implement it on trainer
module la4(
input a,
input b,
input c,
output s,
output cout
);
assign s=(a^b);
assign cout=(a&b);
endmodule
cout :
SUM:
2)
For
a2
bit full adder, write the verilog code, verify
the results with a test bench and then implement it on trainer.
module twobit_adder(a, b, cin,
s, cout);
input [1:0] a;
input [1:0] b;
input [1:0] cin;
output [1:0] s;
output [1:0] cout;
assign s[0]=(a[0]^b[0])^cin[0];
assign s[1]=(a[1]^b[1])^cin[1];
assign cout[0]=(a[0]&b[0])|
(a[0]^b[0])&cin[0];
assign cout[1]=(a[1]&b[1])|
(a[1]^b[1])&cin[1];
14
endmodule
cout :
SUM:
cout :
SUM 1:
SUM 2
3) For a 4 bit
full adder, write the
verilog code and verify the results with a test bench and then implement it
on trainer.
module la44(
input [3:0] a,
15
input [3:0] b,
input c,
output [3:0] s,
cout :
(without data
bus)
module la44(
input a,
input b,
input c,
input d,
input e,
input f,
input g,
inout h,
input i,
output s1,
output s2,
output s3,
output s4,
output cout
);
wire c1,c3,c2;
assign
s1=(a^b)^c;
16
assign c1=(a&b)|(a&b)&c;
assign s2=(d^e)^c1;
assign c2=(d&e)|(d&e)&c1;
assign s3=(f^g)^c2;
Vlsi lab exam final
SUM:
assign c3=(f&g)|(f&g)&c2;
assign s4=(h^i)^c3;
assign cout=(h&i)|(h&i)&c3;
endmodule
cout :
SUM 1:
SUM 2-4
Lab 05
Question1:
MICROWIND LAYOUTS
17
DSCH LAYOUTS
Lab 06
18
19
Lab07
XOR
XNOR
20
Lab 08
21
Lab 09
1.Implement all logic gates through if else condition and case method
CASE METHOD
module lab9(
input a,
input b,
output reg c,
input [7:0] sel
);
always @ (a or b or sel)
case (sel)
0 : c = a&b;
1 : c = a|b;
2 : c = a^b;
3 : c = ~(a&b);
4: c = ~(a|b);
5: c = ~(a^b);
6: c = ~(a);
7: c = ~(b);
endcase
endmodule
IF ELSEMETHOD
module task1(
input a,
input b,
input [3:0]sel,
output y
);
22
always @ (a or b or sel)
if (sel==0)
y=a&b;
else if (sel==1) y=a|b;
Vlsi lab exam final
else if (sel==2)
else if (sel==3)
else if (sel==4)
else if (sel==5)
else if (sel==6)
else if (sel==7)
Endmodule
y=a^b;
y=~(a&b);
y=~(a|b);
y=~(a^b);
y=~a;
y=~b;
8x1 MUX
1x8 DEMUX
module task2_mux(
input a,
input b,
input c,
input d,
input e,
input f,
input g,
input h,
input [7:0]sel,
output y );
always @ (a or b or c or d or e or f or
g or h or sel)
if (sel==0)
y=a;
else if (sel==1)
y=b;
else if (sel==2)
y=c;
else if (sel==3)
y=d;
else if (sel==4)
y=e;
else if (sel==5)
y=f;
else if (sel==6)
y=g;
else if (sel==7)
y=h;
endmodule
23
input [1:0] b;
output g;
output l;
output e;
reg g,l,e;
always @ (a or b)
if (a>b)
begin g=1;l=0;e=0; end
else if (a==b)
begin g=0;l=0;e=1; end
else
begin g=0;l=1;e=0; end
Endmodule
4. As a junior engineer in Car Audio division you have been tasked
to design a four-segment light emitting diode (LED) barograph
meter that graphically displays the voltage output by the audio
amplifier. Your engineering team supervisor informs you that
the voltage coming from the cars audio amplifier varies from 0
to 5V and that you must power your circuit directly from the
12V car battery. He suggests you use the circuit shown in Figure
as a model for your design. Further design constraints use 3
LEDs to display the lower voltage levels and 1 LED to display
the highest voltage level.
module lab99(a, b , g, e, l,f);
input [3:0] a;
input b;
output g;
output l;
output e;
output f;
reg g,l,e,f;
always @ (a or b)
if(b==1)
begin
if (a[0]==b)
begin g=1;l=0;e=0;f=0; end
else if (a[1]==b)
begin g=1;l=1;e=0;f=0; end
else if (a[2]==b)
begin g=1;l=1;e=1;f=0; end
else if (a[3]==b)
begin g=1;l=1;e=1;f=1; end
else
24
begin g=0;l=0;e=0;f=0; end
end
Endmodule
Lab 10
1. Design BCD to seven segments Decoder in reverse order.
module abc(a, b, c);
input [3:0] a;
output [7:0] b;
output [3:0] c;
reg b;
reg c;
always @(a)
begin
case(a)
4'b1111: begin b<=8'b01000000; end
4'b1110: begin b<=8'b01111001; end
4'b1101: begin b<=8'b00100100; end
4'b1100: begin b<=8'b00110000; end
4'b1011: begin b<=8'b00011001; end
4'b1010: begin b<=8'b00010010; end
4'b1001: begin b<=8'b00000010; end
4'b1000: begin b<=8'b01111000; end
4'b0111: begin b<=8'b00000000; end
4'b0110: begin b<=8'b00010000; end
4'b0101: begin b<=8'b00001000; end
4'b0100: begin b<=8'b00000011; end
4'b0011: begin b<=8'b01000110; end
4'b0010: begin b<=8'b00100001; end
4'b0001: begin b<=8'b00000110; end
4'b0000: begin b<=8'b00001110; end
endcase
c<=4'b1110;
end
endmodule
25
input [3:0] q;
output [7:0] a;
output [3:0] anode;
reg[7:0]a;
reg[3:0]anode;
always@(q)
begin
case(q)
4'b0000:begin a<=8'b01000000;end
4'b0001:begin a<=8'b00100100;end
4'b0010:begin a<=8'b00011001;end
4'b0011:begin a<=8'b00000010;end
4'b0100:begin a<=8'b00000000;end
4'b0101:begin a<=8'b00001000;end
4'b0110:begin a<=8'b01000110;end
4'b0111:begin a<=8'b00000110;end
endcase
anode<=4'b1110;
end
endmodule
3. To count in odd order.
Endmodule
Lab 11
Write the VERILOG code for Decimal-to-BCD encoder, verify the result with test
bench and implement the logic on trainer.
10'b00001xxxxx
10'b0001xxxxxx
10'b001xxxxxxx
10'b01xxxxxxxx
10'b1xxxxxxxxx
endcase
endmodule
:
:
:
:
:
code = 5;
code = 6;
code = 7;
code = 8;
code = 9;
EXAMPLE 1
8'b1xxxxxxx :
endcase
Endmodule
code = 7;
Lab 13
1) Implement up/down counter on trainer.
DOWN COUNTER
0: a=8'b01000000;
1: a=8'b01111001;
2: a=8'b00100100;
3: a=8'b00110000;
4: a=8'b00011001;
5: a=8'b00010010;
6: a=8'b00000010;
7: a=8'b01111000;
8: a=8'b00000000;
9: a=8'b00010000;
endcase
Endmodule
EXAMPLE
13: a=8'b00100001;
14: a=8'b00000110;
15: a=8'b00001110;
endcase
endmodule
Lab14
1. Implement 2 input logic gates [and, or, nand, nor, xor, xnor].Show its timing
diagram and implement on trainer.
2 INPUT
AND GATE
OR GATE
NAND GATE
NOR GATE
XOR GATE
XNOR GATE
assign c[6]=!a;
assign c[7]=!b;
endmodule
2. Implement 4 input logic gates [and, or, nand, nor, xor, xnor].Show its timing
diagram and implement on trainer.
4 INPUT
AND GATE
OR
NAND
NOR
XOR
XNOR
33
Lab 12
EXAMPLE
else
begin
q <= data;
end
Endmodule
1) Implement JK flip flop using if else statement and case method also specify
truth table, schematic.
37