Chapter 4: Memory Built-In

Built In
Self Test
Self-Test

Jin Fu Li
Jin-Fu
Dept. of Electrical Engineering
National Central University
Jhongli, Taiwan

Outline

ROM BIST
RAM BIST
Serial BIST for RAMs
Processor
Processor-Based
Based RAM BIST
RAM BISTs in SOCs
References

EE, National Central University

Jin-Fu Li

Introduction
Characteristics of todays SOC designs
Typically more than 30 embedded memories on a

chip
hi
Memories scattered around the device rather than
concentrated in one location
Different types and sizes of memories
Memories doubly embedded inside embedded cores
Test access to these memories from only a few chip
I/O pins
p

Built-in self-test (BIST) is considered the best

solution for testing embedded memories within
SOCs
It offers a simple and low-cost
low cost means without

significantly impacting performance

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General BIST Architecture

Test

Circuit Under Test

Response

Generator

(CUT)

Verification

Test Controller

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ROM Functional Block Diagram

Inputs
Buffer

NOR/NAND

Decoder

(ROM Array)

Buffer
Outputs
O t t
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An Example of ROM BIST

Counter

ROM

MISR

Controller
Go/No-Go

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Status

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Typical RAM BIST Architecture

Normal I/Os

Test Collar
C

T t Controller
Test
C t ll

Test Pattern
Generator

RAM

Go/No-Go
Comparator

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RAM BIST

In general, two BIST approaches have been

proposed for the RAMs
FSM-based RAM BIST
ROM-based RAM BIST

Controller

Generate control signals to the test pattern

generator & the memory under test

Test pattern generator (TPG)

Generate the required test patterns and Read/Write

signals
g

Comparator

Evaluate the response

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ROM-Based RAM BIST

The features of ROM-based BIST scheme

The ROM stores test procedures for generating test

patterns
Self-test is executed by using BIST circuits controlled
by the microprogram ROM
A wide range of test capabilities due to ROM
programming
p
g
g flexibility
y

The BIST circuits consists of the following

functional blocks

Microprogram ROM to store the test procedure

Program counter which controls the microprogram

ROM
TPG
Comparator
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ROM-Based RAM BIST Architecture

Normal I/Os

E d
End

Mi
Microprogram
Test Collar

ROM

TPG

RAM

Go/No-Go
Comparator

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10

March-9N Test Procedure & Microcodes

M h 9N
March-9N:
STEP

OPERATION
CLEAR
WRITE(D), INC AC, IF AC=MAX THEN INC PC
READ(D)
WRITE(D), INC AC, IF AC=MAX THEN INC PC ELSE DEC PC
READ(D))
READ(D
WRITE(D), INC AC, IF AC=MAX THEN INC PC ELSE DEC PC
DEC AC
READ(D)
WRITE(D) DEC AC
WRITE(D),
AC, IF AC=0 THEN INC PC ELSE DEC PC
READ(D)
WRITE(D), DEC AC, IF AC=0 THEN INC PC ELSE DEC PC
STOP

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IF AC=MAX/0
ELSE DEC PC
INCREMENT AC
DECREMENT AC
EXCLUSIVE OR
INVERT/NORMAL
COMPARE/MASK
WRITE/READ
CLEAR
TEST END
Jin-Fu Li

MICROCODE
0000000010
1010000100
0000000100
1110010100
0000011000
1110000100
0001000000
0000001000
1101010100
0000011000
1101000100
0000000001

11

FSM-Based RAM BIST

Normal I/Os

E d
End

Test Collar

FSM

TPG

RAM

Go/No-Go
Comparator

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12

FSM-Based RAM BIST

A example
An
l off the
h state di
diagram off controller
ll

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W0

S0

R0

S1

W1

S2

R1

S3

W0

S4

R0

S5

W1

S4

End

S4
Jin-Fu Li

NOT last address?

NOT last address?

NOT last address?

NOT last address?

13

Programmable RAM BIST

A example
An
l off the
h programmable
bl RAM BIST
Normal I/Os

BRS
BGO

Con
ntroller

BSC

TGO
ENA
DONE

Test Collar
C

BSI

T
TPG
& Compar
C
rator

CMD

RAM

CLK
BNS

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14

FSM State Diagram of the Controller

Idle

BRS=1
BSC=1

DONE=1

Shift
Shift_cmd
d
BSC=0

Get_cmd

Apply

ENA=1

DONE=0

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15

Programmability
The programmability
Th
bili can b
be achieved
hi
db
by using
i
test command
The test command format

U/D

OP

Data background

U/D: ascending/descending address

sequence
OP: test operations

For
o example,
e a p e, wa,
a, rawa,
a a , rawara,
a a a, warawara,
a a a a , etc.

Data backgrounds

The width
Th
idth off each
h field
fi ld affects
ff t the
th
programmability of the BIST design
For
F example,
l if 4 bit
bits are used
d ffor OP
OP, th
then only
l 16

possible test operations

can be generated
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16

FSM State Diagram of the TPG

ENA=0

Idle
ENA=1

Init

DONE/GO

Null=1
Null=0

Ifetch
Exec
Dfetch
No-Go

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Error=1

Compare

Error=0

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17

Serial BIST

Todays telecommunication ICs often have a

variety if multiport memories on one chip

Typical RAM BISTs

evaluate all the bits of a

memory word in parallel as it is read

We can encounter significant problems when

applying these BIST schemes to chips that have

multiple embedded RAMs of varying sizes and

port configurations

The area cost of these BIST designs would be

unacceptably high

One better solution is a serial BIST technique

To
T share
h
BIST d
design
i
among severall RAM
RAMs

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18

Benefits of Serial BIST

Only a small amount of additional circuitry is

required

Only a few lines are needed to connect the RAM

to the test controller

Several RAM blocks easilyy share the BIST

controller hardware

The serial
serial-access
access mode does not compromise
the RAM cycle time

Existing
E i ti memory d
designs
i
d
do nott need
d any
modification to use the serial interface

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19

Serial-Data-Path Connection
Row de
ecoder

Ci

Ci+1

Column decoder

Latch

Latch

Write
Read
BIST on

To next test input

or serial input

From previous output

or serial input

Ii
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Oi
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Ii+1

Oi+1
20

Serial Shift Operation

An example of serial shift operations for the

match element (R0W1)

Time Operation Serial

in

0
11

010

00

00

000

1
X
1

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00

000

000
0
X

Word
content

Serial
out

R0

W1

R0

W1

R0

W1

R0

W1

Jin-Fu Li

21

Serial March (SMarch)

Assume that a RAM has W words, and each

word contains C bits

A Read operation is denoted by R0, R1, or Rx,

depending on the expected value at the serial

output (x=dot care)

For a write operation

operation, the terms W0 or W1 are
used and only the serial input is forced to the
value indicated

The SMarch modified from March C- is as

f llc ( RxW 0 ) C ( R 0, W 0 ) C ; ( R 0, W 1) C ( R1, W 1) C
follows

( R1, W 0 ) C ( R 0 , W 0 ) C ; ( R 0 , W 1) C ( R1, W 1) C

( R1, W 0 ) C ( R 0 , W 0 ) C ; ( R 0 , W 0 ) C ( R 0 , W 0 ) C
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22

Serial BIST Architecture

BIST GO Done

Counters

SO
Control
Data out
Data in
Address

Timing

Controller

generator

SI

lsb

msb

C-1

Multiplexer

Multiplexer
C

Address

Data in

Multiplexer
C

Data out

Control

RAM (W words of C bits)

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23

Sharing BIST in Daisy-Chain Style

BIST GO Done

Counters

Timing

Controller
SO

generator
g

SI

Add
Address

R d/W it
Read/Write

Test Collar

Test Collar

Test Collar

RAM1

RAM2

RAM3

Serial Interface

Serial Interface

Serial Interface

SI

SI

SI

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SO

SO
Jin-Fu Li

SO
24

Sharing BIST in Parallel Style

BIST

GO

Done

DeMux

C
Counters
t

SO
SI
Controller

Address

Timing
g
generator
Read/Write

Test Collar

Test Collar

Test Collar

RAM1

RAM2

RAM3

Serial Interface

Serial Interface

Serial Interface

SI

SI

SI

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SO

SO
Jin-Fu Li

SO
25

BIST Using Data Decoding/Encoding

n
m wire

n
e
m wire

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26

Processor-Based RAM BIST

Normal I/Os

Test Collar

Processor

TPG

RAM

Go/No-Go
Comparator

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27

NTHU Processor-Programmable BIST

ADDR_cpu

ADDR
ADDR_bist

DATAO
DATAO_sys

DATAO
DATAO_bist

Embedded
CPU

Clock_cpu

BIST core

Ctrl_bist

Ctrl_cpu

DATAI_cpu

DATAI_bist

On-chip
bus

Mux_sel

DATAI_sys

Embedded
Memory

control

DATAI

Source: Prof. C. W. Wu, NTHU

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28

NTHU Processor-Programmable BIST

BIST core

DATAO_cpu
DATAO_bist
RBG

ADDR_cpu Address

decorder

RAL

L
Lowest/highest
t/hi h t addr
dd

RAH

REA

RME

RFLAG

RIR

RED

Address
counter

ADDR_bist

Up/down

Controller

Read/Write
Control

Match/unmatch

DATAI_bist

Comparator

DATAI sys
DATAI_sys

Data background

Source: Prof. C. W. Wu, NTHU

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29

NTHU Processor-Programmable BIST

Data registers
Register
RBG

Function
Store background data

RAL

Store lowest address

RAH

Store highest address

RME

Store current March element

RIR

Instruction register of BIST circuit

RFLAG

Status register of BIST circuit

RED

Erroneous response of defective cell

REA

Address of defective cell

Source: Prof. C. W. Wu, NTHU

EE, National Central University

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30

NTHU Processor-Programmable BIST

BIST procedure

Source: Prof. C. W. Wu, NTHU

Test program write data background to RBG

Test program write lowest/highest address to RAL/RAH

Performed by
test program

Test program write March instructions to RME

Test program write START to RIR

(Wa)

(Ra,Wa)

(Ra,Wa)

(Ra,Wa)

Compare
Data error

Performed by
BIST circuit

(Ra,Wa)

yes

No
No

(Ra)

Write ERROR to RFLAG

Write error response to RED
Write faulty addr to REA

March element
complete

yes
Write FINISH to RFLAG
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Test program
take over
31

SOC Testing

A typical SOC chip

ADC

FPGA
Wrapper

CPU

UDL

Flash Memoryy

DSP
Sink

Source

TAM

Test Access Mechanism (TAM)

MPEG

SRAM

SRAM

DRAM

Source: Y. Zorian, et al.-ITC98

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32

SOC Test Access

ADC

FPGA
Wrapper

CPU

UDL

Off-chip Source/Sink

Flash
Memory

1. Pins determine bandwidth

2. More TAM area
3. Requires expensive ATE

DSP
Sink
TAM

TAM

Source
MPEG

SRAM

SRAM

DRAM

ADC

Flash

Wrapper

On chip Source/Sink
On-chip
1. Close to Core-under-test
2 Less TAM area
2.
3. BIST IP area
4. Requires lightweight ATE

FPGA

UDL

CPU

Memory

DSP
Sink

Source

Sink

Source

MPEG

SRAM

SRAM

DRAM

Source: Y. Zorian and E.J. Marinissen

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33

1500 Scalable Test Architecture

Source

User Defined Parallel TAM

TAM-in

TAM-out

TAM-in

1500 Wrapper
W
Fin

WSI

Core1
WIR

Sink
TAM-out

1500 Wrapper
W
Fout

Fin

WSO

WSI

CoreN
WIR

Fout

WSO

WIP
User-Defined
Test Controller

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34

1500 Test Wrapper

Test stimuli

WPI
W
WBR

W
WBR

Functional

Core

WPO Test response

Functional

data

data
WBY
WSI

WIR

WSO

WSC

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35

Memories in SOCs
FPGA

ADC

Flash Memory
CPU

UDL

DSP

DRAM
SRAM

SRAM

SRAM

BIST

BIST

MPEG

N BIST memory cores

Non-BIST
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SRAM
BIST

SRAM

DRAM
BIST

BIST
BIST-ready
d memory cores
Jin-Fu Li

36

RAM BIST in SOCs

Memory cores in an SOC can be categorized

into two types in term of testability
BIST-ready memory cores
Non-BIST memory cores

An SOC can contain tens or even hundreds of

memory
e o y cores
co es

Although a BIST usually have only about 8

controlling pins
The total BIST controlling pins is huge if each BISTready memory cores has its own BIST controlling pins

The BIST controlling pins should be shared

One solution is using
g memory
y BIST interface

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37

Sharing BIST Controlling Pins

ADC

FPGA
Flash Memory

CPU

UDL

DSP
DRAM

SRAM

SRAM
BIST

SRAM

MBI
MBI

MPEG

BIST
MBI
MBI

BIST

BIST

SRAM

DRAM

SRAM

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38

Memory BIST Interface (MBI)

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39

Memory BIST Interface (MBI)

Instruction Register

Store the instructions

RUN_BIST, RUN_DIAGN, EXPORT_STATUS, TAM_CONTROL

Bypass
yp
Register
g

It is selected if the corresponding memory core is not

tested

Monitor Register

Monitor
o to the
t e error
e o flag
ag ((indicating
d cat g whether
et e a memory
e oy

fault is detected or not)

Status Register

Record the key status values, such as Fail output from

the BIST

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40

Testing Multiple Memories with MBI

Using RUN_BIST instruction, we can test multiple

memory cores concurrently
When one or more BIST circuits detect faults, the primary

MSO_N will be high after N-K clock cycles if the concurrent

output of the (K+1) through the N memory cores are fault free

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41

Sharing BIST Hardware

BIST controlling signals
TPG &
BIST Controller

Comparator

ll
BIST C
Collar

BIST C
Collar
ll

ll
BIST C
Collar

RAM 1

RAM 2

RAM N

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42

RAM BIST Compiler

S
Source:
P
Prof.
f C.
C W
W. Wu,
W NTHU
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43

1500-Compilant BIST

Wrapper

T
TAP
Con
ntroller

TAP
P

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BIST

Jin-Fu Li

RAM

44

Programmable BISD for RAMs in SOCs

General test architecture

ATE
SOC

TAP controller
TAM

Wrapper
Processor + Test Program Memory

Embedded Memory Core

S
Source:
A
Appello
ll D
D., et. al.l ITC03
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45

Programmable BISD for RAMs in SOCs

Test Processor

Processor
Wrapper
P1500
Instructions

Control
Unit

P1500
Output Data

Memory
Adapter

Test Program

Address Bus
Data Bus
g
Control Signals

S
Source:
A
Appello
ll D
D., et. al.l ITC03
EE, National Central University

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46

Programmable BISD for RAMs in SOCs

Control Unit

Manage the test program execution

Include an Instruction Register (IR) and

Program Counter (PC)

The control unit allows the correct update of
some registers located in Memory Adapter
This part simplifies the processor reuse in
different applications without the need for any
re-design

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47

Programmable BISD for RAMs in SOCs

Memory Adapter
Control Address registers
g
(Current
(
_address))
Control Memory registers
Current_data
Received_data
R
i d d t

Control Test registers

Dbg
g_index,, Step,
p, Direction flag,
g, and Timer registers
g

Result registers

Status, Error, and Result registers

Some constant value registers

Add_Max, Add_Min, DataBackGround, Dbg_max

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48

Programmable BISD for RAMs in SOCs

Processor instruction set

M
Meaning
i

I t ti
Instruction
SET_ADD
RST_ADD
STORE_DBG
INV_DBG

Current_address Add_Max
Direction flag BACKWARD
Current_address Add_Min
g FORWARD
Direction flag
Current_data DataBackGround[Dbg_index]
Dbg_index Dbg_index+1
Current_data NOT (Current_data)

READ

Current data Memory[Current_address]

Current_data
Memory[Current address]

WRITE

Memory[Current_address] Current_data
Source: Appello D., et. al. ITC03

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49

Programmable BISD for RAMs in SOCs

Wrapper
WSI

WRCK

ShiftWR
UpdateWR
CaptureWR
SelectWIR

W
D
R

W
I
R
W
B
Y

Processor

Test
Program

W
B
R

Me
emory

TAP controller
c

WRSTN

W
C
D
R

CORE

WSO

Wrapper
Source: Appello D., et. al. ITC03
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50

Summary

ROM BIST has been presented

p
ROM-based and FSM-based RAM BIST have
been introduced

Serial BIST methodology for embedded

memories
i h
has also
l presented
t d

BIST approaches
pp
for testing
g multiple
p RAMs in an
SOC have also been addressed

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51

References

[1] A. K. Sharma,Semiconductor memories technology, testing, and

reliability,
li bilit IEEE P
Press, 1997
1997.
[2] B. Nadeau-Dostie, A. Silburt, and V. K. Agarwal,Serial interfacing for
embedded-memory testing, IEEE D&T, pp.52-63, apr. 1990.
[3] C. W. Wu,VLSI testing & design for testability II: Memory built-in selftest, http://larc.ee.nthu.edu.tw/~cww/
[4]C. H. Tsai and C.-W.
[4]C.-H.
C. W. Wu, ``Processor-programmable
Processor programmable memory BIST for
bus-connected embedded memories'', in Proc. Asia and South Pacific
Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2001, pp. 325-330
[5]C.-W
[5]C
W. Wang,
Wang C
C.-F
F. Wu,
Wu JJ.-F
F. Li,
Li C
C.-W
W. Wu,
Wu T
T. Teng,
Teng K
K. Chiu,
Chiu and H.
H -P
P. Lin
Lin, ``A
A
built-in self-test and self-diagnosis scheme for embedded SRAM'', in Proc.
9th IEEE Asian Test Symp. (ATS),Taipei, Dec. 2000, pp. 45-50
[6]D. Appello,
[6]D
Appello F
F. Corno
Corno, M.
M Giovinetto,
Giovinetto M
M. Rebaudengo
Rebaudengo, and M
M. S
S. Reorda
Reorda,A
A
P1500 compliant BIST-Based approach ro embedded RAM diagnosis,
pp.97-102, MTDT, 2001.
[7]J. F
[7]J
F. Li
Li, H
H. JJ. H
Huang, JJ. B
B. Ch
Chen, C.
C P.
P Su,
S C.
C W.
W Wu,
W C.
C Cheng,
Ch
S.
S I.
I Chen,
Ch
C.
C Y.
Y
Hwang, and H. P. Lin,A hierarchical test methodology for systems on chip,
IEEE Micro, pp. 69-81, Sep./Oct., 2002.
[8]S. Mourad and Y. Zorian,Principles off Testing Electronic Systems, John
Wiley & Sons, 2000.

EE, National Central University

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