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Comparator Kenmartin
Comparator Kenmartin
Ken Martin
Dept. of Elec. and Comp. Eng.
University of Toronto
Toronto, Canada M5S 1A4
martin@eecg.toronto.edu
(416) 978-6695
Comparators
Using an Op-Amp for a Comparator
Can use an uncompensated op-amp for a comparator.
This comparator has a resolution limited to the input-offset-voltage of the op-amp
on the order of 2mV to 5mV for typical MOS processes.
In many applications, this would be inadequate.
V in
Vout
An alternative architecture which can resolve signals with accuracies much less
than the input-offset-voltages of op-amps is shown below.
1'
2
Sr
V in
1
Vout
Bottom Plate
During 1 the bottom plate of the capacitor C (i.e. the left side of capacitor C) is
connected to ground and the top plate is connected to the inverting input of the
op-amp. At the same time, the output of the op-amp is also connected to the
inverting input of the op-amp by closing switch S r .
During the comparison phase, the reset switch, S r , is turned off, and the top plate
of the capacitor is connected to the input voltage. If the input signal is greater
than zero, the output of the op-amp will saturate negative; if the input signal is
less than zero, the output of the op-amp will saturate positive. These two cases
are easily resolved and stored using a simple digital latch.
The limitations of this approach become apparent when one considers non-ideal
op-amps, having finite gains, and needing compensation in order to be stable
during the reset phase.
For example, consider the case where a 0.5mV signal must be resolved. After
comparison, the output of the op-amp should have a 5V difference between the
cases when the input signal is -0.25mV and +0.25mV. This means the gain of the
op-amp must be at least 10,000. Thus, the open-loop time constant of the
comparator will be on the order of 10 4 ta . This limits the clock frequency to
about 500kHz which is normally unacceptably slow.
During the comparison time, the compensation capacitor should be disconnected
as shown below.
Vin
Vin
Q1
1
Cc
Vout
(1)
(2)
(3)
(4)
(5)
Clock-Feedthrough Errors
Perhaps the major limitation on the resolution of comparators is due to what is
called clock-feedthrough.
This error is due to transistor channel-charge flow when transistors turn off.
When they turn off, there are two mechanisms whereby charge errors occur. The
first is due to the channel charge which must flow out from the channel region of
the transistor to the drain and the source junctions. The channel charge of a
transistor having zero V DS is given by
Q CH = W 3 L 3 C V eff = W 3 L 3 C ox ( V GS V t )
(6)
ox
Another, usually somewhat smaller charge, unless V eff is very small, is due to
the overlap capacitance between the gate and the junctions.
Shown below is the comparator using n-channel switches and parasitic capacitors
to model the overall charge efffects when transistors turn off.
'1
2
C3a
C 1a
C3b
C1b
Q1
Vin
V'
V''
Q3
Vout
C2a
Q2
C2b
The comparator of
shown.
Consider first when Q 3 turns off. If the clock waveform is very fast, the channel
charge due to Q 3 will flow equally out through both junctions [Shieh/87].
The charge that goes to the output node of the op-amp will have very little effect
other than causing a temporary glitch.
However, the charge that goes to the inverting-input node of the op-amp will
cause the voltage across C to change which introduces an error. Since this charge
is negative, for an n-channel transistor, the node voltage V will go negative. The
voltage change due to the channel charge is given by
Q ch
V eff3 C ox W 3 L 3
( V DD V tn )C ox W 3 L 3
V = ---------- = --------------------------------------- = --------------------------------------------------------(7)
2C
2C
2C
since
the
effective
gate-source
voltage
of
Q3
is
given
by
(8)
Input-Offset-Voltage Cancellation
Another source of error is due to the input-offset voltage of the op-amp.
In switched-capacitor comparators, such as that shown above, it is not a problem
as it is stored onto the capacitor during the reset phase as shown below.
During 1:
1'
C
Sr
Voff
Vout
Voff
Voff
During 2:
2
V in + Voff
1'
Sr
V in
Vout
Voff
Voff
Not only does this technique eliminate input-offset-voltage errors, but it also
minimizes errors caused by low-frequency 1/f noise which can be quite large in
CMOS ICs.
1'
Q3a
Vin
Vout
Q3b
1'
Ideally, when the comparator is taken out of reset mode, the clock-feedthrough of
reset switch Q 3a will match the clock-feedthrough of Q 3b . The only errors now
will be due to mismatches in the clock-feedthrough of the two switches which
will be at least ten times smaller, typically, than in the single-ended case.
Normally, comparators are always designed as fully differential, although we will
often show them as single-ended to simplify schematics.
A third alternative, that can be used along with fully-differential design
techniques, is to realize a multi-stage comparator where the clock-feedthrough of
the first stage is stored on coupling capacitors between the first and second stage,
thereby eliminating its effect. Also, the clock feed-through of the second stage
can be stored on the coupling capacitors between the second and the third stages,
etc. A single-ended version is shown below.
Consider the time when 1' goes low and the switch of the first stage has charge
injection. When 1' goes low, Q 1 will inject charge into both the inverting input
and the output of the first stage. The charge injected at the first stage output will
only cause a temporary glitch there. The charge injected at the inverting input
1'
Vin 2
C1
1
1''
C2
OA1
1'''
C3
OA2
Vout
OA3
1
1'
1''
1'''
2
will cause this node to go negative. The amount this node voltage will be in the
range of tens of millivolts or so. After the inverting input goes negative, the
output of the first stage will go positive by an amount equal to the negative
transition of the inverting input multiplied by the first stages gain. However, at
this time 1'' is still high. Therefore, the second-stage is still being reset.
Therefore, C 2 is charged up to whatever the error caused by the clockfeedthrough of the first stage is. This eliminates its effect. In a similar manner,
when 1'' turns off and the second-stage goes from closed-loop reset mode to
open-loop comparison mode, the third stage is still in reset mode and the clockfeedthrough of the second stage is stored on coupling capacitor C 3 . Finally,
when the third stage turns off, its clock feedthrough is not cancelled. However,
the error it causes in resolving an input voltage to all three stages is equal to the
voltage transition at the inverting input of the third stage divided by the negative
of the gains of the first two stages. (i.e. This is the input voltage needed to cancel
the effect of the clock-feedthrough of the third stage coming out of reset mode.)
Latched Comparators
Modern comparators will have 1-3 gain stages followed by a track-and-latch
stage. The track-and-latch stage operates as an amplifier during 1 and then is
reconfigured into a positive-feedback latch during 2 .
Latch-Mode Time-Constant
Consider two inverting amplifiers connected in a positive-feedback loop.
Vy
Vx
Vy
CL
RL
RL
CL
Vx
AV
-------V x
RL
We have
AV
dV x V x
-------V y = C L ---------- -------
RL
dt
R L
(9)
AV
dV y V y
-------V x = C L ---------- -------
RL
dt
R L
(10)
and
10
dV x
---------- + V x = A V V y
dt
(11)
dV y
---------- + V y = A V V x
dt
(12)
and
(13)
AV 1
--------------t
-
(14)
where V 0 is the initial voltage difference at the beginning of the latch phase.
Thus, the voltage difference increases exponentially in time with a time-constant
given by
RL CL
CL
(15)
11
(16)
(17)
where K 2 might be between 0.5 and 1. Substituting (16) and (17) into (15) gives
K1 L 2
L2
ltch = ------ ----------------- = K 3 ----------------K 2 n V eff
n V eff
(18)
where K 3 might be between 2 and 4. Note that (18) implies that ltch is
dependant primarily on the technology and is not very dependant on the design
(assuming a reasonable design is used that maximizes V eff and minimizes C L ).
Note also the similarity between (18) and (4), the equation for the time-constant
of a cascade of gain stages. For a given technology, (18) is very useful in
determining a rough estimate for the maximum clock frequency of a latch-andtrack comparator.
If it is necessary for a voltage difference of V logic to be obtained for succeeding
logic circuitry to safely recognize the correct output value, then through the use
(14), the time necessary for this to happen is given by
C L V logic
V logic
L2
T ltch = --------- ln ------------------ = K 3 ----------------- ln ------------------
G m V 0
n V eff V 0
This analysis is the basis for understanding Comparator Metastability.
12
(19)
Q5a
Q4a Q4b
Q5b
Vltch
Vltch
Vout+
V2a
Vin+
Vltch
Vin-
V1a
V2b
Q3a
Q3b
Vltch
Vout-
V1b
Q1b
Q1a
Preamplifier Stage
Q2aQ2b
Track-and-Latch Stage
The preamplifier (or preamplifiers) are required to obtain higher resolution and to
minimize the effects of flash-back. The output of the preamplifier, although
larger than the comparator input, is still much smaller than the voltage levels
needed to drive digital circuitry. The track-and-latch stage then amplifies this
signal further during the track-phase, and then also during the latch-phase when
the positive feedback is enabled which regenerates the analog signal into a fullscale digital signal. The use of the track-and-latch stage minimizes the total
number of gain stages required, even when good resolution is needed, and, thus,
is faster than the multi-stage approach just described.
Flash-back denotes the charge transfer either into or out of the inputs when the
track-and-latch stage goes from track-mode to latch-mode. It is caused by the
charge needed to turn the transistors in the positive feedback circuitry on, and by
the charge that needs to be removed in order to turn transistors in the tracking
circuitry off. Without having a preamplifier or buffer, this flash-back will go into
the driving circuitry causing very large glitches, especially in the case when the
impedance seen looking into the two inputs is not perfectly matched.
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Vout
Vin
Trk
Preamp
Gain Stage
Positive Feedback
comparator actually has the positive feedback of the second stage always enabled.
In track mode, when the two diode-connected transistors of the gain-stage are
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enabled, the gain around the positive-feedback loop is less than one and the
circuit is stable. The combination of the diode-connected transistors of the gain
stage and the transistors of the positive-feedback loop act as a moderately large
impedance giving gain from the preamplifier stage to the track-and-latch stage.
The diode-connected loads of the preamplifier stage give a limited amount of gain
in order to maximize speed, while still buffering the flash-back from the input
circuitry.
A third example is shown below. . [Norsworthy/89]. This design also uses diode-
Latch
Vout
Latch
Preamp
Positive Feedback
A two-stage comparator from [Norsworthy/89].
connected loads in order to keep all nodes relatively low impedance (similar to
current-mode circuit-design techniques), thereby keeping all node time constants
small and giving fast operation. This design also uses pre-charging to eliminate
any memory from the previous decision. For example, the positive-feedback stage
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First-Stage Common-Mode
Feedback
1
2
Vin
C1A
1
2
C1B
First SC Gain Stage
C2A
Positive Feedback
Stage
Trk
Trk
16
1
1
1
Trk
The clock waveforms required by the comparator of .
eliminates any input offset voltages form both the first and second stages by using
capacitive coupling. It also has common-mode feedback circuitry for the first
preamplifier stage which allows for input signals having large common-mode
signals. Unlike in fully-differential op-amps, the linearity of the common-mode
feedback circuitry in fully-differential comparators is non-critical as whenever
large signals are present (and the common-mode feedback circuitry becomes nonlinear) there is no ambiguity in resolving the sign of the input signal. Measured
(but unpublished) performance of this circuit resulted in a 0.1mV resolution at a
2MHz clock frequency, despite a very old 5m technology. The performance
measured was limited by the test set-up rather than the circuitry.
A fifth example, realized in a BiCMOS technology, that exhibited very good
performance, was described in [Razavi/92]. Indeed, at the time of publication,
this comparator is one of the better BiCMOS designs to date. It is based on the
realization that it not necessary to reset the first stage and the input-offset errors
of the first stage can still be eliminated by resetting the right side of the coupling
capacitors between the first stage and the second stage, based on the assumption
that the gain of the first stage is not too large [Poujois, 1978] [Vittoz, 1985]. A
simplified schematic of this comparator is shown in . During reset phase, the
inputs to the preamplifier are connected directly to ground (or a reference
voltage), while the outputs of the coupling capacitors are connected to ground as
well. This stores any offset voltages of the first stage on the capacitors. When the
comparator is taken out of reset phase, then the effect of the clock-feedthrough of
S 5 and S 6 on the input resolution is divided by the gain of the first stage. In the
realization described in [Razavi/92], the first stage was a BiCMOS preamplifier
consisting of MOS source followers followed by a bipolar differential amplifier
and emitter-follower output buffers as is shown in . Notice that the circuit
operates between ground and a negative voltage supply. Note also that the
switches are realized using p-channel transistors. The track-and-latch stage of
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S1
Vin
S3 1
S5
PositiveFeedback
Latch
1
S2
1
S4
Vout
S6 1
Vout-
Vout+
Vin+
Vin1
[Razavi/92] has both a bipolar latch and a CMOS latch as is shown in . During
the reset phase, 1 is low and 2 is high, X 1 and Y 1 are connected to ground
through switches M 1 and M 2, C 3 is discharged to the minus supply through M 11,
and X 2 and Y 2 are discharged to the minus supply through M 9 and M 10. Also, at
this time, M 3 and M 4 are off. Next, 1 goes high which leaves X 1 and Y 1 floating
and connects the inputs of the preamplifier to its input signal. After a short delay,
which is needed for the transient response of the preamplifier, 2 goes low, which
turns on M 12 thereby activating the positive feedback action of Q 5 and Q 6. This
develops a differential voltage between X 1 and Y 1 of about 200mv, since C 3 is
about 1/5 the size of C 1 and C 2. The offset of this bipolar latch is quite small,
typically on the order of one millivolt or less. Also, note that, when activated, the
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X1
M1 M2
Y1
Vin+
VinC1
C2
Q5
M12
Q6
M3
C3
M4
M5
M11
M6
X2
Y2
Vout+
Vout2
2
M9
M7
M8
M10
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References
W. Colleran and A. Abidi, A 10-b, 75-MHz Two-Stage Pipelined Bipolar A/D Converter, IEEE J. of Solid-State
Circuits, Vol. 28, No. 12, pp. 1187-1199, Dec. 1993.
J. Fernandes, S. Miller, M. Mallison, and G. Miller, A 14-bit 10-s Subranging A/D Converter with S/H,IEEE J.
of Solid-State Circuits, vol. 24, No. 6, pp 1485-1491, Dec. 1989.
D.G. Haigh and B. Singh, A Switching Scheme for Switched-Capacitor Filters which Reduces Effect of Parasitic
Capacitances Associated with with Control Terminals, Proc. IEEE Int. Symp. on Circuits and Systems, vol. 2, pp.
586-589, Jun. 1983.
R.H. Krambeck, C. Lee, and H.S. Law, High-Speed Compact Circuits with CMOS,IEEE J. of Solid-State
Circuits, Vol. 17, No. 3, pp. 614-619, Jun. 1982.
K. Martin, Improved Circuits for the Realization of Switched-Capacitor Filters, IEEE Trans. Circuits and
Systems, Vol. CAS-27, No. 4, pp. 237-244, April 1980.
K. Martin, L. Ozcolak, Y.S. Lee and G.C. Temes, A Differential Switched-Capacitor Amplifier, IEEE J. SolidState Circuits, SC-22, No. 1, pp. 104-106, Feb. 1987.
K. Martin, New Clock-Feedthrough Cancellation Technique for Analog MOS Switched-Capacitor, Elctron.
Lett., no. 18, 1992.
A. Matsuzawa, et. al., A 10b 30MHz Two-Step Parallel BiCMOS ADC with Internal S/H, IEEE Intern. SolidState Circuits Conf., pp. 162-163, Feb. 1990.
J. McCreary and P.R. Gray, All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques-Part 1,
IEEE J. of Solid-State Circuits, vol. SC-10, pp. 371-379, Dec. 1975.
G. Miller, M. Timko, H.S. Lee, E. Nestler, M. Mueck, and P. Ferguson, An 18b 10s Self-Calibrating ADC,
IEEE Intern. Solid-State Circuits Conf., pp. 168-169, Feb. 1990.
S. Norsworthy, I. Post, and S. Fetterman, A 14-bit 80-KHz Sigma-Delta A/D Converter: Modeling, Design, and
Performance Evaluation, IEEE J. of Solid-State Circuits, vol. 24, No. 2, pp. 256-267, Apr. 1989.
R. Poujois and J. Borel, A Low Drift Fully Integrated MOSFET Operational Amplifier, IEEE J. of Solid-State
Circuits, Vol. SC-13, pp. 499-503, Aug. 1978.
B. Razavi and B. Wooley, Design Techniques for High-Speed, High-Resolution Comparators, IEEE J. of SolidState Circuits, vol. 27, No. 12, pp 1916-1926, Dec. 1992.
D. Robertson, P. Real, and C. Mangelsdorf, A Wideband 10-bit 20Msps Pipelined ADC using Current-Mode
Signals, IEEE Intern. Solid-State Circuits Conf., pp. 160-161, Feb. 1990.
J. Shieh, M. Patil, and B.L. Sheu, Measurement and Analysis of Charge Injection in MOS Analog Switches,
IEEE J. of Solid-State Circuits, vol. 22, No. 2. pp 277-281, Apr. 87.
K. Sone, Y. Nishida, and N. Nakadai, A 10-b 100-Msample/s Pipelined Subranging BiCMOS ADC, IEEE J. of
Solid-State Circuits, Vol. 28, No. 12, pp. 1180-1186, Dec. 1993.
B. Song, H.S. Lee, and M. Tompsett, IEEE J. of Solid-State Circuits, vol. 25, No. 6. pp. 1328-1338, Dec. 1990.
E. J. Swanson, Method and Circuitry of Decreasing the Recovery Time of an MOS Differential Voltage
Comparator, U.S. patent 5247210, Sept. 1993.
K. Tan, et. al., Error-Correction Techniques for High-Performance Differential A/D COnverters, IEEE J. of
Solid-State Circuits, Vol. 25, No. 6, pp. 1318-1327, Dec. 1990.
T.L. Tewksbury, H.S. Lee, and G. Miller, The Effects of Oxide Traps on the Large-Signal Transient Response of
Analog MOS Circuits, IEEE J. of Solid-State Circuits, Vol. 24, No. 2, pp. 542-543, April 1989.
20
E.A. Vittoz, Dynamic Analog Techniques, in Design of MOS VLSI Circuits for Telecommunications, ed. Y.
Tsividis and P. Antognetti, Prentice Hall, 1985.
P. Voerenkamp and J. Verdaasdonk, A 10b 50MS/s Pipelined ADC, IEEE Intern. Solid-State Circuits Conf., pp.
32-33, Feb. 1992.
R. Van de Plassce and P. Baltus, An 8-bit 100-MHz Full-Nyquist Analog-to-Digital Converter, IEEE J. of SolidState Circuits, Vol. 23, No. 6, pp. 1334-1344.
T. Wakimoto, Y. Akazawa, and S. Konaka, Si Bipolar 2-GHz 6-bit Flash A/D Conversion LSI, IEEE J. of SolidState Circuits, Vol. 23, No. 6, pp. 1345-1350, Dec. 1988.
A. Yukawa, A CMOS 8-Bit High-Speed A/D Converter IC, IEEE J. of Solid-State Circuits, Sc-20, No. 3, pp.
775-779, June 1985.
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