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Computer Hardware Requirements For Real-Time Applications: I. Central Processing Unit
Computer Hardware Requirements For Real-Time Applications: I. Central Processing Unit
HARDWARE REQUIREMENTS
COMPUTER
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GPR
ALU
CU
DATA
ADDRESS
CONTROL
Main Memory
I/O Peripherals
Peripherals
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Single commands to carry out multiple operations.
NUMBER OF REGISTERS
INFORMATION TRANSFER RATES: The transfer rate is the ability
to carry out operations in parallel with the processing of data, and
the ability to communicate with a large range of devices and is
very important factor in process control.
INTERRUPT STRUCTURE: it should be flexible, efficient and
multi-level in nature.
ii. Memory:
The computer memory can be divided into two main categories:
a. Fast access storage(primary memory)
b. Auxiliary storage (secondary memory)
Contains data, programs and results which are currently used by the
CPU.
The different types of memories are:
RAM (random access memory read/write)
ROM (read-only memory),
PROM (programmable read-only memory)
EPROM (electronically programmable read-only memory)
FLASH
The above memories store critical code or predefined functions.
b. Auxiliary storage:
They provide bulk storage for programs or data which are required
infrequently at a much lower cost than fast access memory.
The limitation is longer access time and the need for interface boards
and software to connect them to the CPU.
Operate asynchronously to the CPU.
NOTE:
A. Generally the ROMs are used for memory protection and to prevent loss of
programs.
B. Alternative to ROM is the use of memory mapping techniques that trap
instructions which attempt to store in a protected area.
iii.
Input/output devices:
Various types of devices are connected to the processor and each has its own data transfer rates.
The I/O system of most control computers can be divided into three sections:
a) Process I/O;
b) Operator I/O;
c) Computer I/O.
iv.
Bus:
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3. MICROCONTROLLERS:
Microcomputers have all the components necessary for a complete
computer on a single chip.
A typical single-chip device, microcontroller is as shown in Figure (3.2).
Oscillator
Hardware
Timers
CPU
Interrupt
Controller
EPROM
Serial
Communicatio
n Controller
RAM
I/O Ports
External Bus
4. SPECIALIZED PROCESSORS:
The main reasons for using special purpose processors are:
a. Safety-critical applications
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An alternate to the SIMD and MISD architectures was the MIMD architecture
which has separate instruction and data paths. The same is illustrated in fig
(3.6). An example of MIMD architecture is the INMOS transputer.
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Specific applications such as speech processing, telecommunications, radar and hi-fi systems
require that the bandwidth of the signals be processed at a very high processing speed.
And for thus purpose special purpose integrated circuits optimized to meet the signal processing
requirements are used.
DSPs typically use fixed point arithmetic and the instruction set contains
instructions for manipulating complex numbers.
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Read Operation:
The computer places the address of the register onto the
address bus and is decoded by the decoding circuit. The
address decoder sends a SELECT signal to the register.
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Note:
1. The digital input interface in fig (3.7) enumerates a system in which the
plant provides the data only when the processor prompts.
2. There are advanced systems in which the plants interrupt the processor
when the data is ready for transfer.
Output Interface:
Digital output requires a register or a latch to hold the data output from the
computer, as shown in fig (3.9).
The data in the register must not change when the data on the data bus
changes, but rather should change only when the specific register is
addressed.
The ENABLE signal from the processor indicates the device that the data is
available on the data bus and can be read.
The register output is a set of logic levels, typically 0 to + 5 V
NOTE: The digital input and output interfaces described above can be used to
accept BCD data from instruments.
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As is shown in fig (3.10) analog-to digital converters (ADCs) include samplehold circuit.
To read data from the analog input interface, the processor issues a SAMPLE
signal.
After the sampling process is over, quantization process commences.
After the conversion process is complete the ADC sends a CONVERSION
COMPLETE signal to the processor.
The ADCs are not cost effective; hence multiplexers are used to interface
multiple devices to the processor.
NOTE: 1. If the signals are in the volt range then solid state devices are used for
multiplexers.
2. If the signals are in the mill volt range then mercury wetted reed relays
are used in place multiplexers.
Note: Reed Relays:
A reed relay has a set of contacts inside a vacuum or inert gas filled glass tube,
which protects the contacts against atmospheric corrosion. The contacts are closed
by a magnetic field generated when current passes through a coil around the glass
tube. Reed relays are capable of faster switching speeds than larger types of relays,
but have low switch current and voltage ratings.
Mercury wetted reed relays:
A mercury-wetted reed relay is a form of reed relay in which the contacts are wetted
with mercury. Such relays are used to switch low-voltage signals (one volt or less)
because of their low contact resistance, or for high-speed counting and timing
applications where the mercury eliminates contact bounce. Mercury wetted relays
are position-sensitive and must be mounted vertically to work properly. Because of
the toxicity and expense of liquid mercury, these relays are rarely specified for new
equipment.
input interface
Output Interface:
It requires the conversion of digital signals into analog signals.
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c. Pulse Interfaces:
Input and Output Interface:
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d. Real-Time Clock:
Definition: It is an auxiliary device used in computer control applications,
and consists of a pulse generator with a precise controlled frequency.
Generally the frequency can be sourced from either the ac supply line or from
an external hardware circuit- fixed frequency pulse generator.
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The real time clock decrements a counter and when it reaches zero,
generates an interrupt and reloads the count value.
The Interrupt activates the real-time clock software.
The interval at which the timer generates an interrupt, and hence the
precision of the clock, is controlled by the count value loaded into the
hardware timer.
Disadvantage:
If the precision of the real time clock is high, then the CPU will spend a
large amount of time servicing the clock and will not be able to perform '
any other activity.
In real-time clock based on the use of an interval timer and interruptdriven software, the clock stops when the power is lost and on restart the
current value of real time has to be loaded.
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iii.
iv.
v.
vi.
vii.
COMPUTER
Manual override
Hardware failure indication
Debugging aids
Operating systems
Power failure warning
Context Switching:
An interrupt can occur during any part of the execution of a program.
Due care should be taken such that temporary information in the CPU
registers called the context, should not be overwritten during the execution of
the ISR.
When there is an interrupt the following vital steps are taken by the processor
after the execution of the current instruction:
i.
Save all the CPU registers-0program status word, registers and
address of the next instruction in the program counter (PC).
ii.
Load new context to switch to a new function.
The above steps are known as the context switching.
The methods commonly used for context switching are:
i.
Store the contents of the registers in a specified area of memory.
ii.
Store the registers on the memory stack.
iii.
Use of an auxiliary set of registers exclusively for context switching.
The following steps are followed after the execution of the ISR:
i.
Before return from the ISR, retrieve the previously saved status word,
registers and other context parameters.
ii.
Retrieve into the PC the saved PC from wherever it is stored.
iii.
Execute the remaining part of the function, which was interrupted.
Interrupt input mechanism:
A simple form of interrupt input is as shown in Figure 3.16.
In between each instruction the CPU checks the IRQ line.
If it is active, an interrupt is present and the interrupt service routine is
entered; if it is not active the next instruction is fetched and the cycle
repeats.
A common arrangement is to have two interrupt lines as shown in Figure
3.17:
IRQ: can be enabled and disabled using software
Non-mask able interrupts (NMI): cannot be turned off by
software
The number of interrupts can be increased by means of an OR gate.
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finally, when the printer ISR finishes, a '.return is made to the main program
(8).
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7. COMMUNICATIONS:
With the development of distributed computer systems there is a wide spread
demand for communication between the devices and the computers. The
same can be illustrated as in figure.3.21.
At the plant level communications involve parallel analog and digital signal
transmission techniques since the distances over which communication is
required are small and high-speed communication is usually required.
At the higher levels serial communication methods are used. Since,
communication distances extend beyond a few hundred yards, the use of
parallel cabling rapidly becomes cumbersome and costly.
Analog systems are generally limited to short distances as they are prone to
noises, especially in an industrial environment.
The use of parallel digital transmission provides high data transfer rates but
is expensive in terms of cabling and interface circuitry and again is normally
only used over short distances or when very high rates of transfer are
required.
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ii.
Quantity
(a) Character by character
(b) Block
iii.
Distance
(a) Local
(b) Remote (wide area)
iv.
Code
(a) ASCII
(b) Other
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Synchronous communication
In synchronous transmission systems the clock signal for the timing of the
data transfer is provided solely by the transmitter and is sent to the receiver
even when no data is being transmitted. When data is transmitted it is
superimposed on the clock signal.
There is no need to transmit extra bits to enable the receiver clock to
synchronize with the transmitter and hence the effective data transmission
rate for a given speed of line is higher.
The disadvantage is that the interface circuitry is more complex and hence
more expensive. The use of synchronous transmission does not avoid the
need for a transmission protocol.
The advantage of block transmission is that a much higher ratio of data bits
to control bits can be obtained.
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ii.
Star: it has a central switching node to which all other nodes are connected
by a bidirectional link. Data sent to the central switch can be forwarded either
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to all other nodes, or only to a specified node. Drawback is that if the central
node fails then the network also fails. It is as shown in fig 3.25.
iii.
iv.
Hierarchy: The system is similar to star network, but instead of one central
switching node, many of the nodes act as switches. It is as shown in fig 3.26.
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v.
COMPUTER
i.
ii.
8. STANDARD INTERFACES:
There are many companies which cater to the needs of computers for real
time systems, and they develop individual standards for interface of devices
and computers.
The drawback is that the standards supported by particular manufacturers
are not compatible with each other; hence a change of computer
necessitates a redesign of the interface.
The first attempt to develop independent standard was made by the British
Standards Institution (BS 4421, 1969).
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Drawback of the system is that the standard is limited to the concept of how
the devices should interconnect and the standard does not define the
hardware.
A general purpose interface bus (GPIB) was developed by the Hewlett
Packard Company in the early 1970s for connecting laboratory instruments to
a computer. The system was adopted by the IEEE and standardized as the
IEEE 488 bus system.
The ISO (International Organisation for Standardisation) have developed a
standard protocol system in the Open Systems Interconnection (OS I)
model. This is a layered (hierarchical) model with seven layers running from
the basic physical connection to the highest application protocol. The general
structure is illustrated in Figure 3.29. The layers can be described as shown in
Table 3.1.
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)==(=)==(=)==(=)==(=)==(=)==(=)==(=)==(=)==(=)==(
WATCH YOUR CHARACTER, FOR IT BECOMES YOUR DESTINY!!
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QUESTION BANK
1. Draw a schematic diagram of a general purpose computer and explain each
block in detail.
2. Draw a diagram representing a single chip microcomputer and compare the
same with general purpose computer.
3. What are reasons contributing for the development and usage of specialized
processors?
4. Explain in detail any 2 specialized processors.
5. With relevant block diagram compare (i)SISD (ii) MISD (iii) SIMD (iv) MIMD
6. Classify the devices that are interconnected on to a processor based on the
nature of the signal
7. With a block diagram and timing diagram explain the use of digital interface
as an input device.
8. With a block diagram and timing diagram explain the use of digital interface
as an output device.
9. With appropriate block diagrams explain the use of analog interface as input
and output devices.
10.Enumerate in detail the pulse interface to processor and types of pulses and
their interface.
11.What is real time clock and distinguish it from a general clock.
12.Write short notes on :
i)
Polling
ii)
Interrupts
iii)
iv)
v)
vi)
vii)
viii)
DMA
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ASSIGNMENT
1. Why is memory protection important in real time systems? What methods
can be used to provide memory protection?
2. A large valve controlling the flow of steam is operated by a dc motor. The
motor controller has two inputs:
i.
ii.
Fully open=0V
ii.
Fully closed=5V.
Show how this valve could be interfaced to a computer controlling the process.
3. A turbine flow meter generates pulses proportional to the flow rate of a liquid.
What methods can be used to interface the device to a computer?
4. The clock on a computer generates an interrupt every 20msec. Draw a
flowchart for the ISR. The routine has to keep a 24hour clock in hours,
minutes and seconds.
5. 20 analog signals from a plant have to be processed (sampled and digitized)
every 1sec. the ADC and multiplexer which is available can operate in 2
modes: automatic scan and computer controlled scan. In the automatic scan
mode. On receipt of a start signal the converter cycles through each channel
in turn. The data corresponding to the channel sampled is available for
0.96ms. The signal not-ready is asserted during the conversion period and
this indicates that the data is changing and should not read be read by the
computer. The timing is as shown in fig 3.30. In mode2 under computer
controlled scanning, the convertor holds the data for each channel sampled
until it receives a command from the computer to start the sampling of next
channel. To speed up the operation the multiplexer is switched to the next
channel once the current channel has been sampled and before the computer
reads the data for the current channel. The convertor can be reset to start
from channel1 by asserting a signal reset. The timing of this mode of
operation is shown in fig 3.30. Consider the ways in which (a) polling (b)
interrupt methods can be used to interface the convertor to a computer.
Discuss in detail the advantages and disadvantages of each method.
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)==(=)==(=)==(=)==(=)==(=)==(=)==(=)==(=)==(=)==(
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