ComputerArchitecture:PartIV

FirstSemester2013
DepartmentofComputerScience
FacultyofScience
ChiangMaiUniversity
 Outline
BusandMemoryTransfers
Arithmetic Microoperations
ArithmeticMicrooperations
LogicMicrooperations
ErrorDetectionCodes

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 Bus and Memory Transfers
BusandMemoryTransfers
A
Anefficientschemefortransferringinformation
ffi i t h f t f i i f ti
betweenregistersinamultipleregister
configurationisacommonbussystem.
Abusstructureconsistsofasetofcommonlines,
A bus structure consists of a set of common lines,
oneforeachbitofaregister,throughwhich
binary information is transferred one at a time
binaryinformationistransferredoneatatime.
Controlsignalsdeterminewhichregisteris
selectedbythebusduringeachparticular
registertransfer.
g
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 Bus system for four registers
Bussystemforfourregisters
Eachregisterhasfourbits,numbered0through3.
g , g
Thebusconsistsoffour4x1multiplexerseach
having four data inputs, 0 through 3, and two
havingfourdatainputs,0through3,andtwo
selectioninputs,S1 andS0.
Weuselabelstoshowtheconnectionsfromthe
We use labels to show the connections from the
outputsoftheregisterstotheinputsofthe
multiplexers.
multiplexers
Thediagramshowthatthebitsinthesame
significant position in each register are connected
significantpositionineachregisterareconnected
tothedatainputsofonemultiplexertoformone
line of the bus
lineofthebus.
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Bussystemforfourregisters

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 Bus selection
Busselection
The
ThetwoselectionlinesS
two selection lines S1 andS
and S0 areconnected
are connected
totheselectioninputsofallfourmultiplexers.
WhenS
h 1S0 =00,the0datainputsofallfour
h d f ll f
multiplexersareselectedandappliedtothe
outputsthatformthebus.
Thiscausesthebuslinestoreceivethecontent
This causes the bus lines to receive the content
ofregisterAsincetheoutputsofthisregisterare
connectedtothe0datainputsofthe
t d t th 0 d t i t f th
multiplexers.
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Function Table for Bus
FunctionTableforBus

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 ThreeState Bus Buffers
ThreeStateBusBuffers
Itisdistinguishedfromanormalbufferbyhaving
b h
bothanormalinputandacontrolinput.
l d l
Thecontrolinputdeterminestheoutputstate.
Whenthecontrolinputisequalto1,theoutputis
enabledandthegatebehaveslikeany
g y
conventionalbuffer,withtheoutputequaltothe
normalinput.
Whenthecontrolinputis0,theoutputisdisabled
andthegategoestoahighimpedancestateofa
g g g p
threestategateprovidesaspecialfeaturenot
availableinothergates.
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Graphic symbols for threestate buffer
Graphicsymbolsforthreestatebuffer

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 Bus line with three statebuffers
Buslinewiththreestatebuffers
Theoutputsoffourbuffersareconnected
g g
togethertoformasinglebusline.
Thecontrolinputstothebuffersdetermine
which of the four normal inputs will
whichofthefournormalinputswill
communicatewiththebusline.
Nomorethanonebuffermaybeintheactive
state at any given time.
stateatanygiventime.

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Bus line with three statebuffers
Buslinewiththreestatebuffers

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 Arithmetic Microoperations
ArithmeticMicrooperations
Arithmeticmicrooperationsperform
p
arithmeticoperationsonnumericdatastored
inregisters.
Thebasicarithmeticmicrooperationsare
The basic arithmetic microoperations are
addition,subtraction,increment,decrement,
andshift.
hf

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Arithmetic Microoperations
ArithmeticMicrooperations

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 Binary Adder
BinaryAdder
Thedigitalcircuitthatgeneratesthe
y
arithmeticsumoftwobinarynumbersofanyy
lengthiscalledabinaryadder.
Thebinaryadderisconstructedwithfull
The binary adder is constructed with full
addercircuitsconnectedincascade,withthe
outputcarryfromonefulladderconnectedto
f f ll
theinputcarryofthenextfulladder.

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 4bit binary adder
4bitbinaryadder

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 4bitaddersubtractor
WhenM=0thecircuitisandadderandwhenM=1the
circuitbecomesasubtractor.
EachexclusiveORgatereceivesinputMandoneofthe
inputs of B
inputsofB.
WhenM=0,wehaveBexORwith0equaltoB.
ThefulladdersreceivethevalueofB,theinputcarryis0,
andthecircuitperformsAplusB.
WhenM=1,wehaveBexORwith1=BandC0 =1.
p p
TheBinputsareallcomplementedanda1isadded
throughtheinputcarry.
ThecircuitperformstheoperationA
The circuit performs the operation A B. B
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4bit addersubtractor
4bitaddersubtractor

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 4bit binary incrementer
4bitbinaryincrementer
One
Oneoftheinputstotheleastsignificanthalf
of the inputs to the least significant half
adderisconnectedtologic1andtheotherinput
is connected to the least significant bit of the
isconnectedtotheleastsignificantbitofthe
numbertobeincremented.
Theoutputcarryfromonehalfadderisconnected
The output carry from one halfadder is connected
tooneoftheinputsofthenexthigherorderhalf
adder.
adder
ThecircuitreceivesthefourbitsfromA0 through
A3,addsonetoit.Andgeneratestheincremented
adds one to it And generates the incremented
outputsinS0 throughS3.

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4bit binary incrementer
4bitbinaryincrementer

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 4bit arithmetic circuit
4bitarithmeticcircuit
Ithasfourfulladdercircuitsthatconstitute
h f f ll dd i i h i
the4bitadderandfourmultiplexersfor
choosingdifferentoperations.
Therearetwo4bitinputsAandBanda4bit
p
outputD.
ThefourinputsfromAgodirectlytotheX
The four inputs from A go directly to the X
inputsofthebinaryadder.
EachofthefourinputsfromBareconnected
E h f th f i t f B t d
tothedatainputsofthemultiplexers.
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 4bit arithmetic circuit
4bitarithmeticcircuit
Th
Themultiplexersdatainputsalsoreceivethe
lti l d t i t l i th
complementofB.
Theothertwodatainputsareconnectedtologic
The other two data inputs are connected to logic
0andlogic1.
Thefourmultiplexersarecontrolledbytwo
The four multiplexers are controlled by two
selectioninputs,S1 andS0.
TheinputcarryC
The input carry Cin goestothecarryinputofthe
goes to the carry input of the
FAntheleastsignificantposition.
Theothercarriesareconnectedfromonestage
The other carries are connected from one stage
tothenext.

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4bit arithmetic circuit
4bitarithmeticcircuit

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 Arithmetic Circuit Function Table
ArithmeticCircuitFunctionTable
Theoutputofthebinaryadderiscalculatedfrom
thefollowingarithmeticsum:
D=A+Y+Cin
whereAisthe4bitbinarynumberattheXinputs
andYisthe4bitbinarynumberattheYinputsof
y p
thebinaryadder.Cin istheinputcarry,whichcanbe
equalto0or1.
BycontrollingthevalueofYwiththetwoselection
p
inputsS1andS0andmakingC g in equalto0or1,it
q ,
ispossibletogeneratetheeightarithmetic
microoperations.
p
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Arithmetic Circuit Function Table
ArithmeticCircuitFunctionTable

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 List of Logic Microoperations
ListofLogicMicrooperations
Thereare16differentlogicoperationsthat
h diff l i i h
canbeperformedwithtwobinaryvariables.
Theycanbedeterminedfromallpossible
y
truthtablesobtainedwithtwobinary
variablesasshowninslidenumber26.
Inthistable,eachofthe16columnsF
In this table each of the 16 columns F0
throughF15 representsatruthtableofone
possible Boolean function for the two
possibleBooleanfunctionforthetwo
variablesxandy.

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Truth Tables for 16 Functions of Two Variables
TruthTablesfor16FunctionsofTwoVariables

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 Sixteen Logic Microoperations
SixteenLogicMicrooperations
The16logicmicrooperationsarederivedfrom
h l i i i d i df
thesefunctionsbyreplacingvariablexbythe
binarycontentofregisterAandvariableyby
thebinarycontentofregisterB.
Thefirstcolumnrepresentarelationship
y
betweentwobinaryvariablesxandy.y
Thelogicmicrooperationslistedinthesecond
column represent a relationship between the
columnrepresentarelationshipbetweenthe
binarycontentoftworegistersAandB.

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Sixteen Logic Microoperations
SixteenLogicMicrooperations

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 One stage of logic circuit
Onestageoflogiccircuit
Itconsistsoffourgatesandamultiplexer.
i ff d li l
Eachofthefourlogicoperationsisgenerated
g p g
throughagatethatperformstherequired
g
logic.
Theoutputsofthegatesareappliedtothe
data inputs of the multiplexer
datainputsofthemultiplexer.
ThetwoselectioninputsS1 andS0 chooseone
ofthedatainputsofthemultiplexerand
f th d t i t f th lti l d
directitsvaluetotheoutput.

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One stage of logic circuit
Onestageoflogiccircuit

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 Error Detection Codes
ErrorDetectionCodes
Themostcommonerrordetectioncodeused
h d i d d
istheparitybit.
Aparitybitisanextrabitincludedwitha
y g
binarymessagetomakethetotalnumberof
1seitheroddoreven.
TheP(odd)ischosentomakethesumofall
The P (odd) is chosen to make the sum of all
1s(inallfurbits)odd.
TheP(even)bitischosentomakethesumof
Th P ( ) bit i h t k th f
all1seven.
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 Parity Bit Generation
ParityBitGeneration

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Error detection with odd parity bit
Errordetectionwithoddparitybit
ThiscircuitconsistsofoneexclusiveORand
hi i i i f l i d
oneexclusiveNORgate.
SinceP(even)istheexclusiveORofx,y,z,and
( ) p ( ),
P(odd)isthecomplementofP(even),itis
necessarytoemployanexclusiveNORgatefor
p
theneededcomplementation.
Themessageandtheoddparitybitare
transmitted to their destination where they
transmittedtotheirdestinationwherethey
areappliedtoaparitychecker.

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Error detection with odd parity bit
Errordetectionwithoddparitybit
Anerrorhasoccurredduringtransmissionofthe
h dd i i i f h
parityofthefourbitsreceivediseven,sincethe
bi
binaryinformationtransmittedwasoriginally
i f ti t itt d i i ll
odd.
Theoutputoftheparitycheckerwouldbe1
whenanerroroccurs,thatis,whenthenumber
of1sinthefourinputsiseven.
f 1 i h f i i
SincetheexclusiveORfunctionofthefourinputs
isanoddfunction,weagainneedtocomplement
theoutputbyusinganexclusiveNORgate.

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Error detection with odd parity bit
Errordetectionwithoddparitybit

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 Reference
M.MorisMano,ComputerSystem
Architecture,3rd ed.NJ:PrenticeHall,1992.

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