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    Using Verilog-A To Simplify A SPICE Netlist: Application Note

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    Prince Abhishek
    Verilog-A provides an alternative way to describe analog circuits compared to SPICE netlists. It uses a C-like syntax that can simplify circuit descriptions and reduce simulation time. SmartSpice and Harmony support Verilog-A models. Examples show converting an RC circuit and CMOS inverter from SPICE to equivalent Verilog-A modules.

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    Using Verilog-A To Simplify A SPICE Netlist: Application Note

    Uploaded by

    Prince Abhishek
    24 views2 pages
    Verilog-A provides an alternative way to describe analog circuits compared to SPICE netlists. It uses a C-like syntax that can simplify circuit descriptions and reduce simulation time. SmartSpice and Harmony support Verilog-A models. Examples show converting an RC circuit and CMOS inverter from SPICE to equivalent Verilog-A modules.

    Original Description:

    verilog HDL

    Original Title

    1-004_Verilog-A

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    Verilog-A provides an alternative way to describe analog circuits compared to SPICE netlists. It uses a C-like syntax that can simplify circuit descriptions and reduce simulation time. SmartSpice and Harmony support Verilog-A models. Examples show converting an RC circuit and CMOS inverter from SPICE to equivalent Verilog-A modules.

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    24 views2 pages

    Using Verilog-A To Simplify A SPICE Netlist: Application Note

    Uploaded by

    Prince Abhishek
    Verilog-A provides an alternative way to describe analog circuits compared to SPICE netlists. It uses a C-like syntax that can simplify circuit descriptions and reduce simulation time. SmartSpice and Harmony support Verilog-A models. Examples show converting an RC circuit and CMOS inverter from SPICE to equivalent Verilog-A modules.

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    of 2

    Application Note

    Using Verilog-A to
    Simplify a SPICE Netlist
    The SPICE netlist format is often a complex way of SPICE: Verilog-A
    describing a circuit topology.
    *RC Circuit // RC Circuit
    The Verilog-A language provides designers with R1 in out 10k module RC(in, out);
    an alternative method for describing analog circuit C1 out gnd 10u inout in;
    blocks. With Verilog-A rich C like syntax and clear inout out;
    growth path, Verilog-A is a suitable successor to a electrical in;
    method of describing circuit topologies.
    electrical out;
    The Verilog-A language is supported by both SmartSpice ground gnd;
    and Harmony. In SmartSpice, the number of equations
    to solve a circuit condition can be simplified by replac- resistor #(.r(10k)) r1 (in, out);
    ing certain netlist blocks with Verilog-A equivalent capacitor #(.c(10u)) c1 (out, gnd);
    netlists and therefore reducing simulation time. When endmodule
    SmartSpice encounters an active device it must solve
    a larger number of equations to determine the transis-
    tor terminal currents and then use them to solve for the Example 2: A CMOS Inverter
    currents in the circuit. By using Verilog-A description a
    single calculation step gives the currents for the circuit
    thus avoiding the expensive computation. Verilog-A
    description allows savings in calculation complexity,
    system resources and the simulation time.

    The following examples show how to represent a SPICE


    netlist as a Verilog-A module.

    Example 1: An RC Circuit

    Application Note 1-004 Page 1


    An Inverter SPICE Verilog-A Equivalent Pulse Generator Description Using
    Netlist Netlist Verilog-A Netlist

    *CMOS Inverter //CMOS Inverter include discipline.h


    MP1 out in vdd vdd module INVERTER(in, out);
    + pch L=1u W=32u input in; module pwlgen (pwlOut);
    MN1 out in gnd gnd output out; inout pwlOut;
    + nch L=1u W=16u electrical pwlOut;
    electrical in; ground gnd;
    V1 in gnd electrical out;
    + pwl( 0, 0, 10e-6, 5 ) ground gnd; vsource #(.pwl ([0,0 10e-6, 5]) vpwlgen() (pwlOut, gnd);

    .model nch NMOS PM#(.1(1e-6),.w(32e-6)) endmodule


    + level=49 mp1(out,in,vdd,vdd);
    .model pch PMOS NM#(.1(1e-6),.w(16e-6)) Toplevel Testbench
    + level=49 mn1(out,in,gnd,gnd); include discipline.h

    .tran 1n 100u timescale 1ns/1ns


    endmodule
    .save v(in) v(out)
    .end
    module testbend();

    electrical in;
    electrical out;

    pwlgen pwlgen1 (in);


    rc rc1 (in, out);

    endmodule

    Figure 1. Transient simulation of a pulsed inverter in Harmony of - original SPICE netlist and Verilog-A equivalent netlist show
    identical results.

    Page 2 Application Note 1-004

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