SPI (Serial Peripheral Interface) l mt dng giao thc truyn ni tip c dng giao

tip vi cc thit b ngoi vi(EEPROM,SDcard) v cc vi iu khin khc.

7.1 Gii thiu v SPI SPI (Serial Peripheral Interface) l mt dng giao thc truyn ni tip
c dng giao tip vi cc thit b ngoi vi(EEPROM,SDcard) v cc vi iu khin
khc. 7.2 Ch SPI trong vi iu khin PIC Giao tip SPI c hin thc qua 4 chn ca vi
iu khin:
SDI( Serial Data In ): Tn hiu ni tip c a vo vi iu khin
SDO( Serial Data Out): Tn hiu ni tip t vi iu khin i ra
CLK(Clock): xung clock to ra bi master
SS(Slave Select): tch cc mc thp, dng chn slave truyn d liu

Hnh 7-1 S khi ca SPI

7.2.1 Cc thanh ghi iu khin SPI Ch SPI c iu khin bng 4 thanh ghi sau MSSP
Control Register 1 (SSPCON1)
 MSSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer Register(SSPBUF)
MSSP Shift Register(SSPSR) thanh ghi ny khng c truy xut bi ngi dng Hai thanh
ghi SSPCON1 v SSPSTAT l hai thanh ghi iu khin, cn than ghi SSPSR l thanh ghi dng
dch d liu ra/vo vi iu khin, SSPBUF l thanh ghi dng c d liu t ngoi vo
hoc ghi d liu truyn ra ngoi. ch nhn, 2 thanh SSPBUF v SSPSR l 1 b buffer
i, khi d liu t ngoi truyn vo c lu y trong SSPSR(8 bits) th d liu ny c
truyn ti thanh ghi SSPBUF ngi dng ly ra. Cn ch truyn th khi d liu c
ghi vo thanh ghi SSPBUF th cng lc d liu cng c ghi vo thanh ghi SSPSR dch
ra ngoi.

2.7.2.1 Thanh ghi SSPSTAT

Bit 7: SMP Sample bit

SPI Master mode
1 = d liu vo s c ly cui chu k xung clock
0 = d liu vo s c ly gia chu k cung clock
SPI Slave mode
SMP phi c gn bng 0 Bit 6: CKE SPI Clock Select bit Bit 0: BF BuFffer Full Status
bit(dnh cho qu trnh nhn)
1 = qu trnh nhn hon thnh, SSPBUF y
0 = qu trnh nhn ang thc hin, SSPBUF trng 2.7.2.1 Thanh ghi SSPCON1

Bit 7: WCOL Write Collision Detect bit(ch dng ch truyn tn hiu)

1 = thanh ghi SSPBUF c ghi d liu trong khi d liu c truyn cha ht
0 = khng c ng Bit 6: SSPOV Receive Overflow Indicator bit(dng ch nhn tn
hiu)
1 = c d liu mi nhn v ghi ln thanh ghi SSPBUF trong khi d liu trc
cha c c.
0 = d liu khng b ghi Bit 5: SSPEN Synchronous Serial Port Enable bit
1 = bt ch SPI v cc chn SDI, SDO, SCK, SS c cu hnh tng ng.
0 = tt ch SPI Bit 4: CKP Clock Polarity Select bit
1 = thit lp trng thi rnh khi xung clock mc cao
0 = thit lp trng thi rnh khi xung clock mc thp Bit 3-0: SSPM3:SSPM0 Synchronous
Serial Port Mode Select bit
0101 = ch slave, clock = chn SCK, tt chc nng ca chn SS
0100 = ch slave, clock = chn SCK, bt chc nng ca chn SS
0011 = ch master, clock = tn s ca timer 2 /2
0010 = ch master, clock = Fosc / 64
0001 = ch master, clock = Fosc / 16
0000 = ch master, clock = Fosc / 4 7.2.2 Cu hnh SPI cu hnh ch SPI cho vi iu
khin PIC ta s dng cc bit SSPCON1<5:0> v SSPSTAT<7:6>, khi cu hnh cc bit ny SPI
ca PIC s c cu hnh ch master hoc slave, cung clock cho SPI, v thit lp vic
nhn d liu xy ra cnh ln hoc xung ca xung clock. Thanh ghi SSPSR c chc nng
dch d liu ra v vo vi iu khin v lun l bit trng s cao trc. trong ch truyn,
thanh ghi SSPBUF s ch cho n khi thanh ghi SSPSR sn sng nhn d liu ri mi ghi d
liu ln thanh ghi SSPSR, nu c hnh ng ghi d liu vo thanh ghi SSPBUF trong lc d
liu truyn cha xong th hnh ng c b qua v bit WCOL c bt ln bo hiu c
xy ra ng . trong ch nhn, sau khi SSPSR nhn 8 bit d liu s c chuyn
n thanh ghi SSPBUF v bit BF c bt ln bo hiu, nu d liu trc c lu
trong thanh ghi SSPBUF cha c c m li c thm d liu mi th d liu mi s ghi
ln d liu c v bit SSPOV c bt ln.

Hnh 7-2 Kt ni SPI master/slave

Hm cu hnh ch SPI master cho vi iu khin PIC

Code:
void init_spi_master(void) {
SSPSTATbits.CKE = 1; // when CKP = 0,CKE = 0 transmit data on falling clock,CKE = 1
transmit data on rising clock // when CKP = 1,CKE = 1 transmit data on rising clock,CKE = 1
transmit data on falling clock
SSPCON1bits.CKP = 1; // CKP=0 data first,second is clock; CKP=1 clock first,second is data
SSPCON1bits.SSPEN = 1; // enable SPI master
SSPCON1bits.SSPM0 = 0; //
SSPCON1bits.SSPM1 = 0; //
SSPCON1bits.SSPM2 = 0; //
SSPCON1bits.SSPM3 = 0; // preacaler 1:4 }