CALCON11
National Conference on
Electrical, Electronics and Computer Engineering
A comparative study of CMOS and CPL 1-bit
Full Adders with particular Emphasis on
Shannon based Full-Adder
Prof. P.K. Sinha Roy
Dept. of Electronics and Communication Eng.
Institute of Engineering and Management
Kolkata, India
pksinharoy@yahoo.co.in
Sarosij Adak
M.Tech in Electronics and Communication Eng.
Institute of Engineering and Management
Kolkata, India
Sarosij_adak@rediffmail.com
Abstract Arithmetic operations are used extensively in
most of VLSI application of digital signal processing and
microprocessors. The 1-bit full-adder is the building block of these
operation modules. Its performance study is thus of crucial
importance. Full CMOS realization of a 1-bit full-adder is power
efficient but involves large capacitance and consumes large area.
Using complementary pass transistor logic (CPL) the power
efficiency is preserved, but the area and capacitance are drastically
reduced. A comparative study of these two configurations are
made and it is concluded that CPL, though appears more power
efficient and use lesser no of components than CMOS,
consideration of complementary I/O and level restoration makes
the CMOS configuration superior . In a recent work use of
Shannon decomposition was supposed to provide a marginal
improvement in both area and capacitance over the CPL
configuration, but a detailed study shows the claim, made here,
cannot be supported. Further a Spice simulation of a level restorer
for a CPL gate is made and the results are included.
Keywords Full adder, Mirror adder, CPL full adder, Shannon
based full adder, Level restorer.
I. INTRODUCTION
Addition is the basic building block of arithmetic operation.
Naturally it is the basic speed limiting unit. Therefore,
optimization of the adder is very important. Low power VLSI
design features are: high circuit speed, less area and low
transistor count and less power dissipation. Conventional adders
use full CMOS configuration and consumes negligible power
but involves large capacitance and consumes large
area. .Complementary pass transistor logic (CPL) are power
efficient comparable to full CMOS, but the area and capacitance
are drastically reduced. However CPL circuits use
complementary I/O and also level restoration of the output has
to be provided. A comparative study of CMOS and CPL 1-bit
[Paper ID - B021] 04,05/11 CALCON11
Soumen Biswas
M.Tech in Electronics and Communication Eng.
Institute of Engineering and Management
Kolkata, India
phoenix.soumen@gmail.com
Biswajit Roy
M.Tech in Electronics and Communication Eng.
Institute of Engineering and Management
Kolkata, India
bubu.barsha@gmail.com
Full Adders are made here with particular emphasis on a
recently published work on a circuit using Shannon Expansion.
In a recent work Shannon Decomposition Technique is used
on CPL network to provide some improvement in both area and
capacitance. This has been discussed in Section III and the
claim of lesser no of transistors and improvement in speed over
conventional CPL circuits could not be supported. Performance
characteristics of CMOS CPL and Modified Shannon (CPL)
gates are given in Section IV. It also contains the reported
results of investigation of CMOS and CPL gate circuits at
Integrated Systems of Laboratory, Switzerland, Zurich in 1994.
II. COMPLEMENTARY PASS TRANSISTOR LOGIC
Complementary Pass Transistor Logic (CPL) consists of
Complementary inputs/outputs, an NMOS pass-transistor
network and CMOS output inverters. Additionally a PMOS
latch is used to decrease static power consumption and for
swing restoration as opposed to the conventional pull up
function.
High Level of pass transistor output nodes is degraded by
the threshold voltage of nMOS transistor, output signal have to
be restored by CMOS inverters.
A. Algorithm for CPL implementation of Logic function:
Cover the Karnaugh-map with largest possible cubes
(overlapping allowed) .
Express the value of function in each cube in terms of
input signals.
Assign one branch transistor(s)b to each of the cubes
and connect all the branches to one common node,
which is output of nMOS pass-transistor network.
Complementary function can be implemented from the same
circuit structure by applying Complementarity principle as
given below. By applying duality principle, a dual function is
synthesized.
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 CALCON11
National Conference on
Electrical, Electronics and Computer Engineering

1) Complementary Principle : Using the same Circuit 2) Disadvantages:

topology, with Pass signals inverted, dual logic function is
constructed in CPL .
2) Duality Principle: Using the same Circuit topology,
with gate signals inverted, dual logic function is constructed .
Following pairs of basic functions are dual:
o AND-OR (and vice-versa)
o NAND-NOR (and vice-versa)
o XOR-XNOR are self dual (dual to itself)
Proof of complementary principle is trivial since the pass
variables are directly passed from inputs to the outputs, so for
obtaining complementary function an inversion of pass
variables is needed.
nMOS transistors pass a weak 1, though they pass a
strong 0 .
For a chain of nMOS transistors in the nMOS network
swing-reduction becomes prohibitive, and has to be
restored
III. SHANNON BASED FULL ADDER
A. Shannon Theorem:
Shannon expansion of Boolean Functions is based on the
idea that Boolean functions can be reduced by means of the
identity:
F = x . Fx + x . Fx
Where F is any function and Fx and Fx are positive and
negative Shannon cofactors of F , respectively. A positive
Shannon cofactor of a function F with respect to variable x is
defined as that function with all xs set to 1. A negative
Shannon cofactor is the same, but sets all xs to 0.
Shannon expansion can be written as for n variables.
F(X1, X2, .....Xn)=X1.f(1,X2,....Xn) + X1. F(0,X2,...Xn)

B. Full Adder Cell:

In case of a 1-bit full-adder, basic logic equations are-
S= A B Ci .(i)

Co= AB + BCi +ACi .....(ii)

Fig. 1 Construction of dual logic function Applying Shannons expansion on 1st of the above two
equations[Eqn.(A) we have:
Proof of duality principle follows from De Morgan rules and it
is illustrated on the example how OR gate can be obtained from ..................(iii)
AND gate in Fig.1.
( since x 0 = x, and x 1 = x )
B. CPL Full Adder: Circuit Representation of the above equations (i) & (ii)
using pass transistor logic is given below in Fig.1 & Fig.2
respectively.

IV. PAGE STYLE

Fig. 2 Circuit Diagram of CPL Full Adder

Here, transistor count= 32, the transistor widths are given in

LAMBDA unit

C. Advantages and Disadvantages of CPL: Fig.3 Shannon Based Full Adder

1) Advantages: Transistor count= 12+6 = 18, including three inverters in

Fewer transistors are needed leading to lesser area. Sum part.
Smaller transistors and smaller capacitances making it
faster than CMOS.

[Paper ID - B021] 04,05/11 CALCON11 283

 CALCON11
National Conference on
Electrical, Electronics and Computer Engineering

1) Modified 1-bit Full Adder circuit: A modification of C. Results of Investigation at ISL:

the above circuit is reported in [1] where expression for Carry is
written in a form as
.(iv)
As is observed, the circuit consists of 12 transistors in the sum
part and only 2 transistors in the carry part, thus reducing the
transistor count to 14 only.
A systematic investigation on the performances of CMOS
and CPL circuits was made at the Integrated System Laboratory,
Swiss Federal Institute of Technology, CH-8092 Zurich,
Switzerland in 1994.
The first set of comparisons was done on various simple and
complex gates under realistic circuit arrangements and
simulation conditions. Circuits were designed at the transistor-
level in a standard 0.6 m process technology and simulated
using Hspice at 3.3V, 27_C, and estimated diffusion and wiring
capacitances. Transistors were sized carefully by hand with the
objective of minimal PT (power-delay) product.
Transistor size used is = 0.3m. We include the results of
investigation here for some gate networks using CMOS and
CPL devices.

TABLE I
Fig. 4 Modified Shannon based Adder COMPARISON BETWEEN GATE-TYPES
Transistor = (8+6) = 14 Cell Logic Delay Power PT #
Type Style (ns) (W) (norm.) trans.
IV. COMPARISON OF THE THREE ADDER CONFIGURATIONS FA CMOS 1.94 65 1.00 28
CPL 1.17 97 0.90 32
A. Modified Shannon based Full Adder: NAND2 CMOS 0.67 37 1.00 4
The modified Shannon based Full-adder as shown in Fig.2 CPL 1.17 65 3.09 10
AND4 CMOS 1.09 44 1.00 12
consists of only 14 transistors but has the following drawbacks:
CPL 1.48 98 3.02 18
In conventional form the delay in the carry path is AOI/OAI CMOS 1.17 41 1.00 6
minimized and Co is used as an input to the sum, S CPL 1.12 80 1.89 14
output. But here partial output of the sum circuit has MUX2 CMOS 0.93 46 1.00 8
been used as an input to the carry circuit. CPL 1.24 57 1.66 10
The inverter in the Sum circuit puts an additional delay MUX4 CMOS 1.39 62 1.00 18
in the I/O path which results in glitch due to unequal CPL 1.55 66 1.19 18
XOR2 CMOS 1.27 38 1.00 8
delay in the different data paths.
CPL 1.29 59 1.58 10
In CPL circuits, the output of an NMOS gate becomes
Vdd VTn when a high level input is applied to the
drain. No steps have been suggested for remedying this V. LEVEL RESTORATION
affect.
Using the above facts in consideration the circuit using
full CPL with complementary input and
output( required for Level Restoration) appears
desirable though its transistors count is larger.
B. Full CMOS and CPL Full-Adder:
Full CMOS adders use large number of transistors (28
in Full CMOS & 24 in Mirror adder : both PMOS and
NMOS but has negligible static power consumption.
However use of large number of transistors results Fig. 5 Level restoration
in larger gate and junction capacitances producing
large propagation delay. In this Fig.5 we see that a PMOS (MP1) is connected in a
Complementary Pass transistor logic (CPL) uses feedback path. The gate of the PMOS (MP1) device is
almost exclusively (barring 2 PMOS transistors for connected to the output of the inverter, its drain connected to
level restoration) NMOS transistors thus providing the input of the inverter and the source to VDD. If input A
small input capacitance reducing propagation delay. makes a 0 to VDD transition and a PWL is given at B(node 2)
CPL has an added advantage in the fast differential then Mn1 only charges up node X to VDD-VTO. This is,
stage and good output driving capability (output however, enough to switch the output of the inverter low,
inverter) making the implementation of complex gates turning on the feedback device MP1 and pulling node X to
(e.g. full-adders) very efficient. VDD. In this way the loss of VTO at node X is restored with
Large number of nodes and transistors and the two the help of the level restorer MP1.
inversion levels result in relatively inefficient CPL
implementations of simple gates.
Pull-up PMOS transistors are necessary for swing
restoration.
Larger short-circuit currents and higher wiring
overhead (dual-rail signals) compared to CMOS also
increase power consumption.

[Paper ID - B021] 04,05/11 CALCON11 284

 CALCON11
National Conference on
Electrical, Electronics and Computer Engineering
Fig. 6 NOMS switch using Level restorer
The problem is overcome which is found in the NMOS switch
using Level Restorer. In the output voltage there is no loss of
VTO.
Fig. 7 NMOS Switch using Level Restorer:(when restorer MP1 not working)
[Paper ID - B021] 04,05/11 CALCON11
VI. CONCLUSIONS AND FUTURE SCOPE WORKS
The Advantages of high functionality with few pass-
transistors and of small input capacitances in the CPL style are
partially undone by the need for swing restoration circuitry,
dual-rail encoding, and the resulting wiring overhead, which
becomes a crucial factor in deep submicron. The present
investigation compares the performance of CMOS and CPL
Full-adders with particular reference to a recently published
work on a Full-adder using Shannon Decomposition and further
simplification. The latter circuit is studied in detail but the
absence of complementary output, level restoration and unequal
delay in data- path are some of the disadvantages which
considerably undo the advantage of lesser number of transistors.
The work can be extended further by using SPICE
SIMULATIONS for a complete Full-adder and investigating in
detail the advantages and disadvantages of 1-bit Full-adder
using the above three configurations.
REFERENCES
[1] K.Nehru, Dr.A.Shanmugam, S.Deepa and R.Priyadarshini, "A Shannon
Based Low Power Adder Cell for Neural Network Training," International
Journal of Engineering and Technology vol. 2, no. 3, pp. 258-262, 2010.
[2] Dejan Markovic, Borivoje Nikolic and Vijon G. Oklobdzija, Fellow, IEEE,
PROC. 22nd INTENATIONAL CONFERENCE OF MICRO ELECTRONICS
(MIEL 2000) , VOL2, SERBIA, 14-17 MAY, 2000
[3] R. Zimmermann and W. Fichtner, "Low-Power Logic Styles: CMOS
Versus Pass-Transistor Logic", IEEE Journal of Solid-State Circuits, vol.
32, no. 7, pp. 1079-1090, July 1997.
[4] R. Zimmermann and R. Gupta, "Low-Power Logic Styles : CMOS vs CPL",
in Proc. 22nd European Solid-State Circuits Conference (ESSCIRC'96),
Neuchtel, Switzerland, Sept. 1996, pp. 112-115.
[5] CMOS Digital Integrated circuits- Analysis and Design
Third Edition by Sung-Mo(Steve) Kang, University of California at Santa
Curz &Yusuf Leblebici, Swiss Federal Institute of Technology- Lausanne
285