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HP Compaq nx7010 COMPAL LA-1701R2 (1) (1) .0 PDF
HP Compaq nx7010 COMPAL LA-1701R2 (1) (1) .0 PDF
HP Compaq nx7010 COMPAL LA-1701R2 (1) (1) .0 PDF
1 1
Compal confidential 2
Schematics Document
Mobile Banias uFCBGA/uFCPGA with Intel
ODEM_MCH+ICH4-M core logic
3
2003-07-09 3
REV:2.0
4 4
Compal confidential
File Name : LA-1701 Fan Control
page 4
Mobile Banias Thermal Sensor Clock Generator
uFCBGA-479/uFCPGA-478 CPU ADM1032AR ICS 950810
page 4,5
1
page 4 page 12 1
Memory BUS(DDR)
DDR-SO-DIMM X2
Intel ODEM MCH-M BANK 0, 1, 2, 3 page 9,10,11
USB2.0
USB conn
page 27
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
H_D#[0..63]
H_D#[0..63] <6>
H_A#[3..31]
<6> H_A#[3..31]
U9A
H_A#3
H_A#4
P4
U4
A3# Banias D0# A19
A25
H_D#0
H_D#1
ITP700FLEX FOR BANIAS +VCCP +VCCP
H_A#5 A4# D1# H_D#2 +VCCP
V3 A5# D2# A22
H_A#6 R3 B21 H_D#3 JP29 C145
A6# D3#
2
H_A#7 V2 A24 H_D#4 ITP_TDI 1 27 1 2
H_A#8 A7# D4# H_D#5 ITP_TMS TDI VTT0 R104 R149
W1 A8# D5# B26 2 TMS VTT1 28
H_A#9 T4 A21 H_D#6 ITP_TCK 5 26 @0.1U_0402_16V7K 54.9_0402_1% @54.9_0402_1%
H_A#10 A9# D6# H_D#7 ITP_TDO_R TCK VTAP
W2 A10# D7# B20 7 TDO
H_A#11 Y4 C20 H_D#8 ITP_TRST# 3 25 R138 ITP_DBRESET#
H_A#12 A11# D8# H_D#9 TRST# DBR# @0_0402_5%
1
Y1 A12# D9# B24 24
H_A#13 H_D#10 RESETITP# DBA# H_CPURST#
U1 A13# D10# D24 12 2 1RESETITP# ITP_TDO 2 1 ITP_TDO_R
4 H_A#14 H_D#11 RESET# ITP_BPM#0 4
AA3 A14# D11# E24 23
H_A#15 H_D#12 ITP_TCK BPM#0 ITP_BPM#1 R119 R153
Y3 A15# D12# C26 11 21
H_A#16 H_D#13 FBO BPM#1 ITP_BPM#2 22.6_0402_1% @22.6_0402_1%
AA2 A16# D13# B23 19
H_A#17 H_D#14 CLK_CPU_ITP# BPM#2 ITP_BPM#3
AF4 A17# D14# E23 8 17
H_A#18 H_D#15 CLK_CPU_ITP BCLK# BPM#3 ITP_BPM#4
AC4 A18# D15# C25 9 15
H_A#19 H_D#16 BCLK BPM#4 ITP_BPM#5
AC7 A19# D16# H23 13
H_A#20 H_D#17 BPM#5 +VCCP
AC3 A20# D17# G25 10
H_A#21 H_D#18 GND0
AD3 A21# D18# L23 14
H_A#22 H_D#19 GND1 ITP_TMS ITP_TRST#
AE4 A22# D19# M26 16 4 1 2 1 2
H_A#23 H_D#20 GND2 NC1 R135 39.2_0603_1% R129 680_0402_5%
AD2 A23# D20# H24 18 6
H_A#24 H_D#21 GND3 NC2 ITP_TDI ITP_TCK
AB4 A24# D21# F25 20 1 2 1 2
H_A#25 H_D#22 GND4 R134 150_0402_1% R154 27.4_0402_1%
AC6 A25# ADDR GROUP DATA GROUP D22# G24 22
GND5
H_A#26 AD5 J23 H_D#23
H_A#27 A26# D23# H_D#24
AE2 A27# D24# M23
H_A#28 AD6 J25 H_D#25 @ITP700-FLEXCON
H_REQ#[0..4] H_A#29 A28# D25# H_D#26
<6> H_REQ#[0:4] AF3 A29# D26# L26
H_A#30 AE1 N24 H_D#27
H_A#31 A30# D27# H_D#28
AF1 A31# D28# M25
H26 H_D#29
H_REQ#0 D29# H_D#30
R2 N25
H_REQ#1
H_REQ#2
P3
T2
REQ0#
REQ1#
D30#
D31# K25
Y26
H_D#31
H_D#32
Thermal Sensor ADM1032AR
H_REQ#3 REQ2# D32# H_D#33
P1 REQ3# D33# AA24
H_REQ#4 T1 T25 H_D#34 +3VS
REQ4# D34# H_D#35
D35# U23
U3 V23 H_D#36
<6> H_ADSTB#0 ADSTB0# D36#
AE5 R24 H_D#37
<6> H_ADSTB#1 ADSTB1# D37#
R26 H_D#38 W=15mil
R137 0_0402_5% D38# H_D#39
D39# R23 2
1 2 CLK_CPUITP A16 AA23 H_D#40 C131
<12> CLK_CPU_ITP ITP_CLK0 D40#
R136 1 20_0402_5% CLK_CPUITP# A15 U26 H_D#41
<12> CLK_CPU_ITP# ITP_CLK1 D41#
V24 H_D#42
D42#
1
3 H_D#43 1 0.1U_0402_10V6K 3
<12> CLK_CPU_BCLK B15 BCLK0 D43# U25
B14 HOST CLK V26 H_D#44 R114
<12> CLK_CPU_BCLK# BCLK1 D44#
Y23 H_D#45 U13
D45# H_D#46 @10K_0402_5%
D46# AA26 1 VDD SCLK 8 EC_SMC_2 <29>
Y25 H_D#47 1
D47# H_D#48 C129 H_THERMDA
2
<6> H_ADS# N2 ADS# D48# AB25 2 7 EC_SMD_2 <29>
H_D#49 D+ SDATA
<6> H_BNR# L1 BNR# D49# AC23
J3 AB24 H_D#50 2200P_0402_25V7K H_THERMDC 3 6
<6> H_BPRI# BPRI# D50# 2 D- ALERT#
N4 AC20 H_D#51
<6> H_BR0# BR0# D51#
L4 AC22 H_D#52 4 5
<6> H_DEFER# DEFER# D52# H_D#53 THERM# GND
<6> H_DRDY# H2 DRDY# D53# AC25
K3 AD23 H_D#54
<6> H_HIT# HIT# D54# H_D#55 ADM1032AR_SOP8
<6> H_HITM#
K4 HITM# CONTROL GROUP D55# AE22
1 2 H_IERR# A4 AF23 H_D#56
+VCCP R112 IERR# D56# H_D#57
<6> H_LOCK# J2 LOCK# D57# AD24 Address:1001_100X
56_0402_5% H_CPURST# B11 AF20 H_D#58
<6> H_CPURST# RESET# D58# H_D#59
D59# AE21
AD21 H_D#60
H_RS#0 D60# H_D#61
<6> H_RS#0 H1 RS0# D61# AF25
H_RS#1 K1 AF22 H_D#62
<6> H_RS#1 RS1# D62#
H_RS#2 L2 AF26 H_D#63
<6> H_RS#2 RS2# D63#
M3
<6> H_TRDY# TRDY#
D25
Fan Control circuit
DINV0# H_DINV#0 <6>
DINV1# J26 H_DINV#1 <6>
ITP_BPM#0 C8 T24
BPM0# DINV2# H_DINV#2 <6> +5VS
ITP_BPM#1 B8 AD20 +12VS
BPM1# DINV3# H_DINV#3 <6>
ITP_BPM#2 A9 BPM2#
+3VALW 1 R110 2 ITP_BPM#3 C9 BPM3#
150_0402_5% C23
DSTBN0# H_DSTBN#0 <6>
ITP_DBRESET# R1111 2 0_0402_5% A7 K24 2
<16> ITP_DBRESET# DBR# DSTBN1# H_DSTBN#1 <6>
M2 W25 C140
2 <6> H_DBSY# DBSY# DSTBN2# H_DSTBN#2 <6> 2
<7,15> H_DPSLP# B7 DPSLP# DSTBN3# AE24 H_DSTBN#3 <6>
C19 C22 0.1U_0402_10V6K
<7> H_DPWR# DPWR# DSTBP0# H_DSTBP#0 <6> 1
ITP_BPM#4 A10 L24
PRDY# DSTBP1# H_DSTBP#1 <6>
1
2
5
6
1 2 ITP_BPM#5 B10 MISC W24
+VCCP PREQ# DSTBP2# H_DSTBP#2 <6>
5
R121 H_PROCHOT# B17 AE25 U14 D Q23
PROCHOT# DSTBP3# H_DSTBP#3 <6>
330_0402_5% 1 G
P
<29> EN_FAN1 +
H_CPUPWRGD E4 4 FAN1_ON 3
<15> H_CPUPWRGD PWRGOOD O
H_CPUSLP# A6 3 S SI3456DV-T1_TSOP6
<15> H_CPUSLP# SLP# -
G
ITP_TCK A13 +5VS
ITP_TDI TCK
LM321MF_SOT23-5
4
C12 TDI
ITP_TDO H_A20M#
2
A12 TDO A20M# C2 H_A20M# <15>
R105 @1K_0402_5% TEST1 C5 D3 1
TEST1 FERR# H_FERR# <15>
1
R107 @1K_0402_5% TEST2 F23 A3 H_IGNNE#
TEST2 IGNNE# H_IGNNE# <15>
ITP_TMS C11 B5 H_INIT# C448 C427 R341
TMS INIT# H_INIT# <15>
ITP_TRST# B13 D1 H_INTR 1 2 @10000P 10K_0402_5%
TRST# LINT0/INTR H_INTR <15> 2
D4 H_NMI
LINT1/NMI H_NMI <15>
@2200P_0603_16V7K
THERMAL H_STPCLK# JP15
2
STPCLK# C6 H_STPCLK# <15>
H_THERMDA B18 B4 H_SMI# 1 2 FAN1_VOUT
H_THERMDC THERMDA DIODE SMI# H_SMI# <15>
R340 7.32K_0603_1% 1
A18 THERMDC <29> FANSPEED1 2
1
H_THERMTRIP# C17 LEGACY CPU 1
THERMTRIP# 3
2
D23 C422 1
R342 RB751V_SOD323 10U_1206_10V4Z C439 53398-0310
mFCBGA479 13K_0603_1%
+3VALW 2 @10000P
MAINPWON <35,37,42> 2
2
R101
1
1
330_0402_5% C
1 2 2 Q20
+VCCP
2
B @2SC2411K_SOT23
R124 1 2 E
2
330_0402_5%
3
1 R120 C139 1
+VCCP 1U_0603_10V6K
1K_0402_5%
1
2 R102
MMBT3904_SOT23 56 _0402_1% H_THERMTRIP#
Q21 R109
3
H_PROCHOT# Title
1
2 1 2
330_0402_5% INTEL CPU BANIAS (1 of 2)
MMBT3904_SOT23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
3
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 4 of 49
A B C D E
A B C D E
+CPU_CORE
U9B +CPU_CORE U9C
R290 @54.9_0402_1%
1 2 VCCSENSE AE7 A2 F20 T26
VSSSENSE AF6 VCCSENSE VSS VCC VSS
1 2 VSSSENSE VSS A5 1 1 1 1 F22 VCC VSS U2
R288 @54.9_0402_1% A8 G5 U6
VSS + C280 + C281 + C110 + C62 VCC VSS
VSS A11 G21 VCC VSS U22
+CPU_VCCA F26 A14 220U_D2_2VM 220U_D2_2VM 220U_D2_2VM 220U_D2_2VM H6 U24
1 VCCA0 VSS VCC VSS 1
B1 VCCA1 VSS A17 H22 VCC VSS V1
2 2 2 2
1 R79 2 N1 A20 J5 V4
+1.8VS VCCA2 VSS VCC VSS
AC26 VCCA3 VSS A23 J21 VCC VSS V5
0_1206_5% A26 K22 V21
VSS VCC VSS
+VCCP P23 VCCQ0 VSS B3 U5 VCC VSS V25
W4 B6 V6 W3
VCCQ1 VSS +CPU_CORE VCC VSS
VSS B9 V22 VCC VSS W6
B12 W5 W22
D10 VCCP
Banias VSS
VSS B16
10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K W21
VCC
VCC
VSS
VSS W23
D12 B19 Y6 W26
D14
VCCP
VCCP
VSS
VSS B22
1
C67
1
C68
1
C69
1
C70
1
C71
1
C82
1
C88
Y22
VCC
VCC
Banias VSS
VSS Y2
D16 VCCP VSS B25 AA5 VCC VSS Y5
E11 C1 10U_1206_6.3V7K AA7 Y21
VCCP VSS 2 2 2 2 2 2 2 VCC VSS
E13 VCCP VSS C4 AA9 VCC VSS Y24
E15 C7 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K AA11 AA1
VCCP VSS VCC VSS
F10 VCCP VSS C10 AA13 VCC VSS AA4
F12 VCCP VSS C13 AA15 VCC VSS AA6
F14 C15 +CPU_CORE AA17 AA8
VCCP VSS VCC VSS
F16 VCCP VSS C18 AA19 VCC VSS AA10
K6 C21 10U_1206_6.3V7K 10U_1206_6.3V7K 10U_1206_6.3V7K AA21 AA12
VCCP VSS VCC VSS
L5 C24 1 1 1 1 1 1 1 AB6 AA14
10U_1206_6.3V7K
R57 R56 R296 R293 1 1 1 1 1 1 1 1
mFCBGA479 mFCBGA479
27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1% C64 C126 C356 C362 C127 C72 C98 C92
0.01U_0402_16V7K 10U_1206_6.3V7K
2 2 2 2 2 2 2 2
2
+VCCP
H_RS#[0..2] H_D#[0..63]
<4> H_RS#[0..2] H_D#[0..63] <4>
H_A#[3..31] HUB_PD[0..10]
<4> H_A#[3..31] HUB_PD[0:10] <15>
U12B
H_REQ#[0..4] AGP_AD[0..31]
<4> H_REQ#[0..4]
U12A
<13> AGP_AD[0..31]
<13> AGP_CBE#[0..3]
AGP_C/BE#[0..3] AGP_AD0 R27 GAD0
Odem HI_0 P25 HUB_PD0
AGP_AD1 R28 P24 HUB_PD1
AGP_SBA[0..7] AGP_AD2 GAD1 HI_1 HUB_PD2
T25 N27
H_A#3 U6 HA#3
Odem HD#0 AA2 H_D#0
<13> AGP_SBA[0..7]
AGP_AD3
AGP_AD4
R25
T26
GAD2
GAD3
GAD4
HI_2
HI_3
HI_4
P23
M26
HUB_PD3
HUB_PD4
H_A#4 T5 AB5 H_D#1 +VCCP AGP_AD5 T27 M25 HUB_PD5
H_A#5 HA#4 HD#1 H_D#2 AGP_AD6 GAD5 HI_5 HUB_PD6
R2 HA#5 HD#2 AA5 U27 GAD6 HI_6 L28
D H_A#6 H_D#3 AGP_AD7 HUB_PD7 D
U3 HA#6 HD#3 AB3 U28 GAD7 HI_7 L27
H_A#7 H_D#4 AGP_AD8 HUB_PD8
R3 HA#7 HD#4 AB4 V26 GAD8 HUB HI_8 M27
1
H_A#8 P7 AC5 H_D#5 1 AGP_AD9 V27 N28 HUB_PD9
H_A#9 HA#8 HD#5 H_D#6 C334 R303 AGP_AD10 GAD9 HI_9 HUB_PD10
T3 HA#9 HD#6 AA3 T23 GAD10 HI_10 M24
H_A#10 P4 AA6 H_D#7 301_0402_1% AGP_AD11 U23
H_A#11 HA#10 HD#7 H_D#8 0.1U_0402_10V6K AGP_AD12 GAD11
P3 HA#11 HD#8 AE3 T24 GAD12 HI_STB N25 HUB_PSTRB <15>
H_A#12 P5 AB7 H_D#9 2 AGP_AD13 U24 N24
HA#12 HD#9 GAD13 HI_STB# HUB_PSTRB# <15>
H_A#13 H_D#10 H_SWNG1 AGP_AD14
2
R6 HA#13 HD#10 AE5 U25 GAD14
H_A#14 N2 AF3 H_D#11 AGP_AD15 V24 P27 HUB_RCOMP 1 2
HA#14 HD#11 GAD15 HLRCOMP +1.8VS
1
H_A#15 N5 AC6 H_D#12 AGP_AD16 Y27 R315 36.5_0402_1%
H_A#16 HA#15 HD#12 H_D#13 R299 AGP_AD17 GAD16
N3 HA#16 HD#13 AC3 Y26 GAD17 HI_REF P26 HUB_VREF
H_A#17 J3 AF4 H_D#14 150_0402_1% AGP_AD18 AA28
H_A#18 HA#17 HD#14 H_D#15 AGP_AD19 GAD18
M3 HA#18 HD#15 AE2 AB25 GAD19 1
H_A#19 M4 AG4 H_D#16 AGP_AD20 AB27
H_A#20 HA#19 HD#16 H_D#17 AGP_AD21 GAD20 C379
2
M5 HA#20 HD#17 AG2 AA27 GAD21
H_A#21 L5 AE7 H_D#18 +VCCP AGP_AD22 AB26 AB9 0.01U_0402_16V7K
H_A#22 HA#21 HD#18 H_D#19 AGP_AD23 GAD22 VSS91 2
K3 HA#22 HD#19 AE8 Y23 GAD23 VSS92 AD10
H_A#23 J2 AH2 H_D#20 AGP_AD24 AB23 AF9
H_A#24 HA#23 HD#20 H_D#21 AGP_AD25 GAD24 VSS93
N6 HA#24 HD#21 AC7 AA24 GAD25 VSS94 AJ9
1
H_A#25 L6 AG3 H_D#22 1 AGP_AD26 AA25 A7
H_A#26 HA#25 HD#22 H_D#23 C330 R304 AGP_AD27 GAD26 VSS95
L2 HA#26 HD#23 AD7 AB24 GAD27 VSS96 F8
H_A#27 K5 AH7 H_D#24 301_0402_1% AGP_AD28 AC25 J7
H_A#28 HA#27 HD#24 H_D#25 0.1U_0402_10V6K AGP_AD29 GAD28 VSS97
L3 HA#28 HD#25 AE6 AC24 GAD29 VSS98 L8
H_A#29 L7 AC8 H_D#26 2 AGP_AD30 AC22 N8
H_A#30 HA#29 HD#26 H_D#27 H_SWNG0 AGP_AD31 GAD30 VSS99 +1.5VS
2
K4 HA#30 HD#27 AG8 AD24 GAD31 VSS100 R8
H_A#31 H_D#28
J5 HA#31 HOST HD#28 AG7 VSS101 U8
1
AH3 H_D#29 W8
HD#29 VSS102
1
C AF8 H_D#30 R306 AGP_C/BE#0 V25 AA8 C
HD#30 H_D#31 150_0402_1% AGP_C/BE#1 GCBE#0 VSS103
HD#31 AH5 V23 GCBE#1 VSS104 AD8
H_REQ#0 U2 AC11 H_D#32 AGP_C/BE#2 Y25 AF7 R287
H_REQ#1 HREQ#0 HD#32 H_D#33 AGP_C/BE#3 AA23 GCBE#2 VSS105 @1K_0402_5%
T7 HREQ#1 HD#33 AC12 GCBE#3 VSS106 AJ7
H_REQ#2 H_D#34
2
R7 HREQ#2 HD#34 AE9 VSS107 D5
H_REQ#3 H_D#35 AGP_ST2
2
H_REQ#4
U5
T4
HREQ#3
HREQ#4
HD#35
HD#36
AC10
AE10 H_D#36
<13> AGP_FRAME# Y24 GFRAME#
AGP VSS108
VSS109
F6
H6
AD9 H_D#37 W28 K6
HD#37 <13> AGP_DEVSEL# GDEVSEL# VSS110 +1.5VS
AG9 H_D#38 W27 M6
HD#38 <13> AGP_IRDY# GIRDY# VSS111
R5 AC9 H_D#39 W24 P6
<4> H_ADSTB#0 HADSTB#0 HD#39 <13> AGP_TRDY# GTRDY# VSS112
N7 AE12 H_D#40 W23 T6
<4> H_ADSTB#1 HADSTB#1 HD#40 <13> AGP_STOP# GSTOP# VSS113
1
AF10 H_D#41 W25 V6
HD#41 <13> AGP_PAR GPAR VSS114
AG11 H_D#42 AG24 Y6
HD#42 H_D#43 <13> AGP_REQ# GREQ# VSS115 R291
<12> CLK_MCH_BCLK#
<12> CLK_MCH_BCLK
K8
J8
BCLK#
BCLK
HD#43
HD#44
AG10
AH11 H_D#44
<13> AGP_GNT# AH25 GGNT# GND VSS116
VSS117
AB6
AD6 @1K_0402_5%
AG12 H_D#45 AF5
HD#45 H_D#46 VSS118 AGP_ST1
2
HD#46 AE13 VSS119 AJ5
U7 AF12 H_D#47 R24 A3
<4> H_ADS# ADS# HD#47 <13> AGP_ADSTB0 AD_STB0 VSS120
1
V4 AG13 H_D#48 R23 J4
<4> H_TRDY# HTRDY# HD#48 <13> AGP_ADSTB0# AD_STB#0 VSS121
W2 AH13 H_D#49 AC27 L4
<4> H_DRDY# DRDY# HD#49 <13> AGP_ADSTB1 AD_STB1 VSS122
Y4 AC14 H_D#50 AC28 N4 R292
<4> H_DEFER# DEFER# HD#50 <13> AGP_ADSTB1# AD_STB#1 VSS123
Y3 AF14 H_D#51 R4 @1K_0402_5%
<4> H_HITM# HITM# HD#51 VSS124
Y5 AG14 H_D#52 U4
<4> H_HIT# HIT# HD#52 VSS125
H_D#53 AGP_SBA0
2
<4> H_LOCK# W3 HLOCK# HD#53 AE14 AH28 SBA0 VSS126 W4
V7 AG15 H_D#54 AGP_SBA1 AH27 AA4
<4> H_BR0# BR0# HD#54 SBA1 VSS127
V3 AG16 H_D#55 AGP_SBA2 AG28 AC4
<4> H_BNR# BNR# HD#55 SBA2 VSS128
Y7 AG17 H_D#56 AGP_SBA3 AG27 AE4 ST1 ST2 MCH STRAP
<4> H_BPRI# BPRI# HD#56 H_D#57 AGP_SBA4 SBA3 VSS129
<4> H_DBSY# V5 DBSY# HD#57 AH15 AE28 SBA4 VSS130 AJ3
B H_RS#0 W7 AC17 H_D#58 AGP_SBA5 AE27 E1 X 1 DDR B
H_RS#1 RS#0 HD#58 H_D#59 +VCCP AGP_SBA6 SBA5 VSS131
W5 RS#1 HD#59 AF16 AE24 SBA6 VSS132 J1
H_RS#2 W6 AE15 H_D#60 AGP_SBA7 AE25 L1 0 X TEST MODE
RS#2 HD#60 H_D#61 SBA7 VSS133
HD#61 AH17 VSS134 N1
1
1
<4> H_DSTBP#3 AC16 HDSTBP#3 HSWNG0 AA7 H_SWNG0 1
<4> H_DINV#0 AD5 DBI#0
AG5 AC13 H_RCOMP1 C340 R308
<4> H_DINV#1 DBI#1 HRCOMP1
AH9 AC2 H_RCOMP0 0.1U_0402_16V4Z 1K_0402_1%
<4> H_DINV#2 DBI#2 HRCOMP0 2
<4> H_DINV#3 AD15 DBI#3
2
1
RG82P4300M_FCBGA593 +AGPREF
2
R55 R302 R314
1
27.4_0402_1% 27.4_0402_1% @22_0402_5%
RG82P4300M_FCBGA593 Note: R305
Placement R308,R305 1K_0402_1%
A A
1
21 close to MCH
C381
2
@10P_0402_50V8K
2
Compal Electronics, Inc.
Title
ODEM(1/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-1701 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, July 09, 2003 Sheet 6 of 49
5 4 3 2 1
5 4 3 2 1
DDR_SDQ[0..63]
<9> DDR_SDQ[0..63]
DDR_SDQS[0..8]
<9> DDR_SDQS[0..8]
U12C
DDR_CB[0..7]
<9> DDR_CB[0..7]
A
NOTE:1.M_RCV# max 2Via RG82P4300M_FCBGA593 A
2.G15 to Via max=40mils
3.G14 to Via max=40mils
4.Via to Via must = 100mils +-5mils
Title
Compal Electronics, Inc.
ICH4-M(2/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 7 of 49
5 4 3 2 1
5 4 3 2 1
U12D
+2.5V
+1.5VS
R29
VCCAGP0
Odem VSS0
E29 22U_1206_10V4Z 0.1U_0402_16V4Z
W29 J29 1 1 1 1 1 1 1 1
VCCAGP1 VSS1
AC29 N29
VCCAGP2 VSS2 C563 + C401 + C138 C400 C398 C399 C408 C434
AG29 U29
VCCAGP3 VSS3 0.1U_0402_16V4Z
U26 AA29
VCCAGP4 VSS4 100U_6.3V_M 150U_D2_6.3VM 2 2 2 2 2 2
AA26 AE29
VCCAGP5 VSS5 2 2
D AE26 A27 D
VCCAGP6 VSS6 22U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
AJ25 K27
VCCAGP7 VSS7
AD23 AJ27
VCCAGP8 VSS8
AF23 E26
VCCAGP9 VSS9
R22 G26
VCCAGP10 VSS10 +2.5V
U22 J26
VCCAGP11 VSS11
W22 L26
VCCAGP12 VSS12 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
AA22 R26
VCCAGP13 VSS13
AB21 W26 1 1 1 1 1 1 1 1 1 1 1 1
VCCAGP14 VSS14
AD21 AC26
VCCAGP15 VSS15 C411 C433 C417 C410 C409 C416 C413 C419 C406 C402 C432 C418
AF25
VSS16 0.1U_0402_16V4Z
A23
VSS17 2 2 2 2 2 2 2 2 2 2 2 2
F24
VSS18 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
L24
VSS19
P17 M23
+1.2VS VCC0 VSS20
N16 AC23
VCC1 VSS21
P15 AH23
VCC2 VSS22 +1.8VS
R16 D21
VCC3 VSS23
T15 H21
VCC4 VSS24 0.1U_0402_16V4Z
U16 J22
VCC5 VSS25
N14 L22 1 1 1 1
VCC6 VSS26
P13 N22
VCC7 VSS27 C395 C383 C396 C384
R14 T22
VCC8 VSS28 10U_1206_10V4Z 0.1U_0402_16V4Z
U14 V22
VCC9 VSS29 2 2 2 2
Y22
VSS30 0.1U_0402_16V4Z
AB22
VSS31
+1.8VS L29 AC21
VCCHL0 VSS32
L25 AD22
VCCHL1 VSS33
N26 AF21
VCCHL2 VSS34
N23 AG22
VCCHL3 VSS35
M22 AH21
VCCHL4 VSS36 +1.5VS
C A19 C
VSS37
F20
VSS38 10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
H19
+VCCP AG23
VCCP0
POWER GND VSS39
VSS40
AB19 1
AJ23 AC20 1 1 1 1 1 1 1 1
VCCP1 VSS41 C344 + C361
AE21 AD19
VCCP2 VSS42 150U_D2_6.3VM C373 C371 C345 C336 C321 C316 C306
AG21 AE20
VCCP3 VSS43 0.1U_0402_16V4Z
AJ21 AF19
VCCP4 VSS44 2 2 2 2 2 2 2 2 2
AB20 AG20
VCCP5 VSS45 10U_1206_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
AC19 AH19
VCCP6 VSS46
AD20 D17
VCCP7 VSS47
AE19 H17
VCCP8 VSS48
AF20 N17
VCCP9 VSS49
AG19 R17
VCCP10 VSS50 +1.2VS
AJ19 U17
VCCP11 VSS51
AB18 AB17
VCCP12 VSS52 150U_D2_6.3VM 0.22U_0603_10V7K 0.01U_0402_16V7K
AD18 AC18
VCCP13 VSS53
AF18 AE18 1 1
VCCP14 VSS54
AB14 AF17 1 1 1 1 1 1
VCCP15 VSS55 C301 + +
AB10 AG18
VCCP16 VSS56 150U_D2_6.3VM C366 C347 C353 C380 C374 C393 C394
M8 AJ17
VCCP17 VSS57 0.047U_0603_16V7K
T8 A15
VCCP18 VSS58 2 2 2 2 2 2 2 2
AB8 F15
VCCP19 VSS59 2.2U_0805_10V6K 0.015U_0402_16V7K 0.022U_0603_16V7K
H15
VSS60
N15
VSS61
+2.5V C29 P16
VCCSM0 VSS62
G29 R15
VCCSM1 VSS63
A25 T16
VCCSM2 VSS64 +VCCP
D25 U15
VCCSM3 VSS65
K26 AB15
VCCSM4 VSS66 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
D23 AD16
VCCSM5 VSS67
B H24 AF15 1 B
VCCSM6 VSS68
K24 AJ15 1 1 1 1 1 1 1 1
VCCSM7 VSS69 C357 +
L23 D13
VCCSM8 VSS70 150U_D2_6.3VM C305 C311 C315 C338 C320 C310 C337 C367
A21 E14
VCCSM9 VSS71 0.1U_0402_16V4Z
F22 H13
VCCSM10 VSS72 2 2 2 2 2 2 2 2 2
H22 N13
VCCSM11 VSS73 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
K22 P14
VCCSM12 VSS74
D19 R13
VCCSM13 VSS75
H20 T14
VCCSM14 VSS76
A17 U13
VCCSM15 VSS77
F18 AB13
VCCSM16 VSS78
H18 AD14
VCCSM17 VSS79
D15 AF13
VCCSM18 VSS80
F16 AJ13
VCCSM19 VSS81
H16 A11
VCCSM20 VSS82
A13 F12
VCCSM21 VSS83
F14 H11
VCCSM22 VSS84
H14 AB11
VCCSM23 VSS85
D11 AD12
VCCSM24 VSS86
H12 AF11
VCCSM25 VSS87
A9 AJ11
VCCSM26 VSS88
F10 D9
VCCSM27 VSS89
H10 H9
VCCSM28 VSS90
D7
VCCSM29
H8
VCCSM30
K7 G16
VCCSM31 RSVD3
A5 G10
VCCSM32 RSVD4
E5 G9
VCCSM33 RSVD5
H5 H7
VCCSM34 RSVD6
J6 G2
VCCSM35 RSVD7
C1 G3
+1.8VS VCCSM36 RSVD8
A G1 H3 A
VCCSM37 RSVD9
R327
T17 H4 1 2 +2.5V
VCCGA ETS#
10K_0603_0.5%
T13
VCCHA
1 1
C368
0.1U_0402_16V4Z
C382
10U_1206_10V4Z RG82P4300M_FCBGA593 Title
Compal Electronics, Inc.
2 2
ODEM(3/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,
INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COM PETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE
NFORMATION
I IT CONTAINS LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENTOF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet of
8 49
5 4 3 2 1
5 4 3 2 1
10_4P2R_0404_5%
RP49
DDR_MMA8 1 4 DDR_F_SMA8
DDR_MMA6 2 3 DDR_F_SMA6
10_4P2R_0404_5%
Title
Compal Electronics, Inc.
RP51 DDR-SODIMM SLOT1
DDR_SWE# 1 4 DDR_F_SWE#
<7,10> DDR_SWE# THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
DDR_MMA3 2 3 DDR_F_SMA3
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
10_4P2R_0404_5%
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 9 of 49
5 4 3 2 1
A B C D E
+2.5V +2.5V
+1.25VS_SDREF_R
JP22
+1.25VS +1.25VS 1 2 1 2
VREF VREF R343 0_0805_5% +SDREF
3 VSS VSS 4 1
RP67 DDR_DQ4 5 6 DDR_DQ5
DDR_MMA10 DDR_DQ6 DQ0 DQ4 DDR_DQ0 C234
RP110 RP86 8 1 7 8
DDR_DQ6 DDR_DQ40 DDR_SBS1 DQ1 DQ5 0.1U_0402_16V4Z
1 4 4 1 7 2 DDR_SBS1 <7,9> 9 VDD VDD 10
DDR_DQ0 2 3 3 2 DDR_DQ44 6 3 DDR_SBS0 DDR_DQS0 11 12 2
DDR_SBS0 <7,9> DQS0 DM0
5 4 DDR_SRAS# DDR_DQ1 13 14 DDR_DQ3
56_4P2R_0404_5% 56_4P2R_0404_5% DQ2 DQ6
15 VSS VSS 16
56 _8P4R_0804_5% DDR_DQ2 17 18 DDR_DQ7
RP94 DDR_DQ8 DQ3 DQ7 DDR_DQ13
RP108 RP85 19 20
1 DDR_DQ2 DDR_DQ45 DDR_MMA7 DQ8 DQ12 1
1 4 4 1 8 1 21 VDD VDD 22
DDR_DQ7 2 3 3 2 DDR_DQ41 7 2 DDR_MMA6 DDR_DQ12 23 24 DDR_DQ9
DDR_MMA5 DDR_DQS1 DQ9 DQ13
6 3 25 DQS1 DM1 26
56_4P2R_0404_5% 56_4P2R_0404_5% 5 4 DDR_MMA4 27 28
DDR_DQ14 VSS VSS DDR_DQ15 DDR_SDQ[0..63]
29 DQ10 DQ14 30 DDR_SDQ[0..63] <7,9>
RP111 RP84 56 _8P4R_0804_5% DDR_DQ11 31 32 DDR_DQ10
DDR_DQ4 DDR_DQ43 RP95 DQ11 DQ15 DDR_DQ[0..63]
1 4 4 1 33 VDD VDD 34 DDR_DQ[0..63] <9>
DDR_DQ5 2 3 3 2 DDR_DQ42 8 1 DDR_MMA12 35 36
<7> DDR_CLK3 CK0 VDD
7 2 DDR_MMA11 37 38
<7> DDR_CLK3# CK0# VSS
56_4P2R_0404_5% 56_4P2R_0404_5% 6 3 DDR_MMA9 39 40
DDR_MMA8 VSS VSS DDR_DQS[0..8]
5 4 DDR_DQS[0..8] <9>
RP109 RP83
DDR_DQ1 1 4 4 1 DDR_DQ46 56 _8P4R_0804_5% DDR_DQ16 41 42 DDR_DQ20 DDR_SDQS[0..8]
DQ16 DQ20 DDR_SDQS[0..8] <7,9>
DDR_DQ3 2 3 3 2 DDR_DQ47 RP93 DDR_DQ17 43 44 DDR_DQ21
DDR_MMA3 DQ17 DQ21
8 1 45 VDD VDD 46
56_4P2R_0404_5% 56_4P2R_0404_5% 7 2 DDR_MMA2 DDR_DQS2 47 48 DDR_CB[0..7]
DQS2 DM2 DDR_CB[0..7] <7,9>
6 3 DDR_MMA1 DDR_DQ22 49 50 DDR_DQ18
DDR_MMA0 DQ18 DQ22 DDR_F_CB[0..7]
RP104 RP81 5 4 51 52 DDR_F_CB[0..7] <9>
DDR_DQ10 DDR_DQ55 DDR_DQ23 VSS VSS DDR_DQ19
1 4 4 1 53 DQ19 DQ23 54
DDR_DQ11 2 3 3 2 DDR_DQ48 56 _8P4R_0804_5% DDR_DQ24 55 56 DDR_DQ25
DQ24 DQ28
57 VDD VDD 58
56_4P2R_0404_5% 56_4P2R_0404_5% DDR_DQ29 59 60 DDR_DQ28
RP66 DDR_DQS3 DQ25 DQ29 DDR_MMA[0..12]
61 DQS3 DM3 62 DDR_MMA[0..12] <7,9>
RP105 RP82 4 1 DDR_CKE0 63 64
DDR_CKE0 <7,9> VSS VSS
DDR_DQ15 1 4 4 1 DDR_DQ49 3 2 DDR_CKE1 DDR_DQ26 65 66 DDR_DQ27
DDR_CKE1 <7,9> DQ26 DQ30
DDR_DQ14 2 3 3 2 DDR_DQ52 DDR_DQ30 67 68 DDR_DQ31
56_4P2R_0404_5% DQ27 DQ31
69 VDD VDD 70
56_4P2R_0404_5% 56_4P2R_0404_5% DDR_F_CB0 71 72 DDR_F_CB4
DDR_F_CB1 CB0 CB4 DDR_F_CB5
RP65 73 74
DDR_CKE2 CB1 CB5
RP107 RP80 4 1 75 76
DDR_DQ13 DDR_DQ50 DDR_CKE3 DDR_DQS8 VSS VSS
1 4 4 1 3 2 77 DQS8 DM8 78
DDR_DQ8 2 3 3 2 DDR_DQ53 DDR_F_CB2 79 80 DDR_F_CB6
2 56_4P2R_0404_5% CB2 CB6 2
81 VDD VDD 82
56_4P2R_0404_5% 56_4P2R_0404_5% DDR_F_CB3 83 84 DDR_F_CB7
CB3 CB7
RP68 85 86
DDR_SWE# DU DU/RESET#
RP106 RP79 4 1 87 88
DDR_DQ9 DDR_DQ51 DDR_SCAS# VSS VSS
1 4 4 1 3 2 <7> DDR_CLK5 89 CK2 VSS 90
DDR_DQ12 2 3 3 2 DDR_DQ54 91 92
<7> DDR_CLK5# CK2# VDD
56_4P2R_0404_5% 93 94
56_4P2R_0404_5% 56_4P2R_0404_5% DDR_CKE3 VDD VDD DDR_CKE2
<7> DDR_CKE3 95 CKE1 CKE0 96 DDR_CKE2 <7>
RP91 97 98
DDR_SCS#2 DDR_MMA12 DU/A13 DU/BA2 DDR_MMA11
RP103 RP78 4 1 99 100
DDR_DQ16 DDR_DQ58 DDR_SCS#3 DDR_MMA9 A12 A11 DDR_MMA8
1 4 4 1 3 2 101 A9 A8 102
DDR_DQ20 2 3 3 2 DDR_DQ63 103 104
56_4P2R_0404_5% DDR_MMA7 VSS VSS DDR_MMA6
105 A7 A6 106
56_4P2R_0404_5% 56_4P2R_0404_5% DDR_MMA5 107 108 DDR_MMA4
DDR_MMA3 A5 A4 DDR_MMA2
RP92 109 110
DDR_SCS#1 DDR_MMA1 A3 A2 DDR_MMA0
RP100 RP76 4 1 DDR_SCS#1 <7,9> 111 112
DDR_DQ23 DDR_DQ56 DDR_SCS#0 A1 A0
1 4 4 1 3 2 DDR_SCS#0 <7,9> 113 VDD VDD 114
DDR_DQ19 2 3 3 2 DDR_DQ62 DDR_MMA10 115 116 DDR_SBS1
56_4P2R_0404_5% DDR_SBS0 A10/AP BA1 DDR_SRAS#
117 BA0 RAS# 118 DDR_SRAS# <7,9>
56_4P2R_0404_5% 56_4P2R_0404_5% DDR_SWE# 119 120 DDR_SCAS#
<7,9> DDR_SWE# WE# CAS# DDR_SCAS# <7,9>
RP61 DDR_SCS#2 121 122 DDR_SCS#3
<7> DDR_SCS#2 S0# S1# DDR_SCS#3 <7>
RP102 RP77 4 1 DDR_F_CB0 123 124
DDR_DQ17 DDR_DQ59 DDR_F_CB4 DU DU
1 4 4 1 3 2 125 VSS VSS 126
DDR_DQ21 2 3 3 2 DDR_DQ57 DDR_DQ32 127 128 DDR_DQ37
56_4P2R_0404_5% DDR_DQ36 DQ32 DQ36 DDR_DQ33
129 DQ33 DQ37 130
56_4P2R_0404_5% 56_4P2R_0404_5% 131 132
DDR_DQS4 VDD VDD
133 DQS4 DM4 134
RP101 RP75 RP63 DDR_DQ38 135 136 DDR_DQ34
DDR_DQ22 DDR_DQ60 DDR_F_CB2 DQ34 DQ38
1 4 4 1 4 1 137 VSS VSS 138
DDR_DQ18 2 3 3 2 DDR_DQ61 3 2 DDR_F_CB6 DDR_DQ39 139 140 DDR_DQ35
DDR_DQ44 DQ35 DQ39 DDR_DQ40
141 DQ40 DQ44 142
56_4P2R_0404_5% 56_4P2R_0404_5% 56_4P2R_0404_5% 143 144
3 DDR_DQ41 VDD VDD DDR_DQ45 3
145 DQ41 DQ45 146
RP98 DDR_DQS5 147 148
DDR_DQ28 R228 2 DQS5 DM5
1 4 1 56_0402_5%DDR_DQS0 RP62 149 VSS VSS 150
DDR_DQ29 2 3 R229 2 1 56_0402_5%DDR_DQS1 4 1 DDR_F_CB1 DDR_DQ42 151 152 DDR_DQ43
DDR_F_CB5 DDR_DQ47 DQ42 DQ46 DDR_DQ46
3 2 153 DQ43 DQ47 154
56_4P2R_0404_5% 155 156
56_4P2R_0404_5% VDD VDD
157 VDD CK1# 158 DDR_CLK4# <7>
RP99 159 160 DDR_CLK4 <7>
DDR_DQ25 R230 2 VSS CK1
1 4 1 56_0402_5%DDR_DQS2 161 VSS VSS 162
DDR_DQ24 2 3 R231 2 1 56_0402_5%DDR_DQS3 RP64 DDR_DQ52 163 164 DDR_DQ49
DDR_F_CB3 DDR_DQ48 DQ48 DQ52 DDR_DQ55
4 1 165 DQ49 DQ53 166
56_4P2R_0404_5% 3 2 DDR_F_CB7 167 168
DDR_DQS6 VDD VDD
169 DQS6 DM6 170
RP97 56_4P2R_0404_5% DDR_DQ53 171 172 DDR_DQ50
DDR_DQ27 R232 2 DQ50 DQ54
1 4 1 56_0402_5%DDR_DQS4 173 VSS VSS 174
DDR_DQ26 2 3 R233 2 1 56_0402_5%DDR_DQS5 DDR_DQ54 175 176 DDR_DQ51
DDR_DQ63 DQ51 DQ55 DDR_DQ58
177 DQ56 DQ60 178
56_4P2R_0404_5% 179 180
DDR_DQ57 VDD VDD DDR_DQ59
181 DQ57 DQ61 182
RP96 DDR_DQS7 183 184
DDR_DQ30 R234 2 DQS7 DM7
1 4 1 56_0402_5%DDR_DQS6 185 VSS VSS 186
DDR_DQ31 2 3 R235 2 1 56_0402_5%DDR_DQS7 DDR_DQ62 187 188 DDR_DQ56
DDR_DQ61 DQ58 DQ62 DDR_DQ60
189 DQ59 DQ63 190
56_4P2R_0404_5% 191 192
VDD VDD
<9,12,15> SMB_DATA 193 SDA SA0 194 +3VS
RP88 <9,12,15> SMB_CLK 195 196
DDR_DQ38 R236 1 SCL SA1
1 4 2 56_0402_5%DDR_DQS8 197 198
DDR_DQ34 +3VS VDD_SPD SA2
2 3 199 VDD_ID DU 200
56_4P2R_0404_5%
RP87 AMP11376408_STANDARD5.2
DDR_DQ35 1 4
4 DDR_DQ39 2 3 4
56_4P2R_0404_5% DIMM1
RP90
DDR_DQ32 1 4
DDR_DQ37 2 3
56_4P2R_0404_5%
DDR_DQ33
RP89
Title
Compal Electronics, Inc.
1 4
DDR_DQ36 2 3 DDR-SODIMM SLOT1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
56_4P2R_0404_5%
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 10 of 49
A B C D E
A B C D E
Layout note :
Distribute as close as possible
to DDR-SODIMM.
+2.5V
1 1 1 1 1 1 1 1 1 1 1
1 1
C223 C224 C225 C226 C227 C229 C228 C230 C231 C502 C503
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2
+2.5V +2.5V
1 1 1 1 1 1 1 1
C504 C497 C498 C499 C500 C501 + +
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C221 C505
2 2 2 2 2 2 150U_D2_6.3VM 150U_D2_6.3VM
2 2
Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V
2 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C546 C545 C544 C543 C542 C541 C540 C539 C538 C536
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C535 C534 C533 C531 C240 C530 C529 C528 C527 C526
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C525 C524 C523 C522 C521 C520 C519 C518 C517 C515
3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 3
2 2 2 2 2 2 2 2 2 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C514 C241 C512 C511 C510 C242 C508 C507 C236 C237
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2
+1.25VS
1 1 1 1 1 1 1 1 1 1
C537 C238 C239 C243 C244 C245 C246 C247 C516 C513
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2
+1.25VS
4 4
1 1 1 1
C248 C249 C509 C532
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2
Title
Compal Electronics, Inc.
DDR SODIMM Decoupling
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 11 of 49
A B C D E
A B C D E F G H
Clock Generator
SEL2 SEL1 SEL0 CPUCLKC[0..2] CPUCLKT[0..2] +3VS L13 +3V_CLK
CHB2012U121_0805
0 0 0 166.67 166.67 1 2 Width=40 mils 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0 0 1 100.00 100.00 1 1 1 1 1 1 1 1 1
0 1 0 200.00 200.00 C192 C186 C166 C144 C181 C462 C471 C465 C464
10U_1206_10V4Z
2 2 2 2 2 2 2 2 2
0 1 1 133.33 133.33
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1
14
19
32
37
46
50
1
8
U18
VDD_REF
VDD_48MHZ
VDD_PCI_0
VDD_PCI_1
VDD_3V66_0
VDD_3V66_1
VDD_CPU_0
VDD_CPU_1
C151 L14 +3VS
@10P_0402_50V8K CHB2012U121_0805
+3VS +3VS 1 2 XTALIN 2 26 +3V_VDD 1 2
XTAL_IN VDDA
1
1 1
Y2
1
14.318MHZ_16PF_DSX840GA C187 C191
R133 R140 10U_1206_10V4Z
@1K_0402_5% 1K_0402_5% 2 2
2
1 2 XTALOUT 3 27
C154 XTAL_OUT VSSA 0.1U_0402_16V4Z
@1K_0402_5% @10P_0402_50V8K CLK_BCLK
2
2
45 1 2 CLK_CPU_BCLK <4>
R139 2 CPUCLKT2 R169
1 54
SEL0 33_0402_5% R170
1 2 55 49.9_0402_1%
SEL1
R132 1 2 40 1 2
R366 1K_0402_5% SEL2
1K_0402_5% 1 2
R172 R173 49.9_0402_1%
33_0402_5%
25 44 CLK_BCLK# 1 2
<16,29> SLP_S1# PWR_DWN# CPU_CLKC2 CLK_CPU_BCLK# <4>
34
<16> STP_PCI# PCI_STOP# CLK_MCH
53 49 1 2 CLK_MCH_BCLK <6>
<16,41> STP_CPU# CPU_STOP# CPUCLKT1 R160
<41> CLKEN# 33_0402_5% R161
1 49.9_0402_1%
2
+3VS 1 2 28 1 2
R198 10K_0402_5% VTT_PWRGD# R166 R167 49.9_0402_1%
33_0402_5%
48 CLK_MCH# 1 2
CPUCLKC1 CLK_MCH_BCLK# <6>
1
2 D 2
+3VS 1 2 43 MULT0
2 Q29 R362 10K_0402_5% 52 CLK_ITP 1 2
<16,32,41> VGATE CPUCLKT0 CLK_CPU_ITP <4>
G @2N7002 1N_SOT23
R150 R151
S 49.9_0402_1%
33_0402_5%
3
<9,10,15> SMB_DATA 29 1 2
SDATA
<9,10,15> SMB_CLK 30 1 2
SCLK R155 R156 49.9_0402_1%
33_0402_5%
51 CLK_ITP# 1 2
CPUCLKC0 CLK_CPU_ITP# <4>
33
3V66_0
35 24
3V66_1/VCH_CLK 3V66_5
1 1 C184
C177 @10P_0402_50V8K
15
20
31
36
41
47
@10P_0402_50V8K @10P_0402_50V8K
2 2
C180
@10P_0402_50V8K
4 4
Title
Compal Electronics, Inc.
Clock Generator
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 12 of 49
A B C D E F G H
5 4 3 2 1
AGP_SBA[0..7] AGP_AD[0..31]
AGP CONN <6> AGP_SBA[0..7]
AGP_CBE#[0..3]
<6> AGP_AD[0..31]
AGP_ST[0..2]
<6> AGP_CBE#[0..3] <6> AGP_ST[0..2]
FOXCONN-100P FOXCONN-100P
1 1 1 1
B B
+12VALW C302 C111 C94 C89
LCD POWER CIRCUIT LCDVDD +3VS 2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
R16 3 1
LCDVDD +12VALW 100K_0402_5%
Q8
SI2302DS 1N_SOT23
G
0.047U_0402_16V4Z
1
2
1
R14 R15 1 1 1 1
100_0402_5% 100K_0402_5%
R17 C25 C28 C27 C24
4.7U_0805_10V4Z 4.7U_0805_10V4Z
2 2 2 2 +3VS
12
D D
1
Q7 2 2
1
2N7002 1N_SOT23 G G 150K_0402_5% 0.1U_0402_16V7K
S S Q5 R52
2N7002 1N_SOT23 4.7K_0402_5%
3
3
1
D10
DISPOFF#
2
<29> BKOFF# 1 2
RB751V_SOD323
ENAVDD 2 22K
1
Q6 D
22K
ENABLT# 2 Q15
DTC124EK_SOT23 <29> ENABLT# 2N7002 1N_SOT23
G
S
3
A A
Title
Compal Electronics, Inc.
AGP & LCD CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 13 of 49
5 4 3 2 1
A B C D E
CRT Connector
D1 D2 D3 +3VS +5VS +RCRT_VCC CRTVDD
DAN217_SOT23 DAN217_SOT23 DAN217_SOT23
D16
1
F1 2 1 W=40mils
POLYSWITCH_1A RB411D_SOT23
1 1
1
C255
0.1U_0402_16V7K
3
2
JP1
CRT-15P
6
<13,29,33> MSEN# 11
1 2 RED_L 1
<13,33> RED
L22 7
FCM2012C-800_0805 12
GREEN_L +3VS
<13,33> GREEN 1 2 2
L21 8 CRTVDD CRTVDD
FCM2012C-800_0805 13
1 2 BLUE_L 3
<13,33> BLUE
L20 9
1
FCM2012C-800_0805 14
1
2
@22P_0402_25V8K
2
75_0402_1% 75_0402_1%
1 2 D_HSYNC_L Q1
+5VS
L19 FBM-L10-160808-300LM-T 1 3
S
1 DDCDATA <13>
C573
BSN20_SOT23
0.1U_0402_16V4Z D_VSYNC_L
14
1 2
G
1
2
2 2
1 3
S
P
OE
DDCCLK <13>
1
<13> HSYNC 2 A Y 3 1 1 1
C3 C5 C6 BSN20_SOT23
G
R255 R254
G
R269
SN74AHCT126PWR_TSSOP14 @10K_0402_5% @10K_0402_5% 10P_0402_50V8K 10P_0402_50V8K 100P_0402_50V8J
2
1 1 1 2
2 2 2 +3VS
7
10K_0402_5%
C52 C257
2
2
D_VSYNC <33>
68P_0402_50V8K 68P_0402_50V8K
+5VS CRTVDD D_HSYNC <33> 2 2
14
D_DDCCLK <33>
4
U43B
P
OE
SN74AHCT126PWR_TSSOP14
7
Unused GATE
+5VS +5VS
TV-Out Connector
14
10
14
13
U43C U43D
P
OE
OE
D14 D13 D15 +3VS 9 8 12 11
A Y A Y
DAN217_SOT23 DAN217_SOT23 DAN217_SOT23
G
1
1
SN74AHCT126PWR_TSSOP14 SN74AHCT126PWR_TSSOP14
7
3 3
2
3
FM2 FM1 FM3 FM5 FM4 FM6
1 1 1 1 1 1
CF2 CF9 CF3 CF10 CF8 CF12 CF16 CF14 CF5 CF6
1 1 1 1 1 1 1 1 1 1
47P_0402_50V8J S-Video
1 2 LUMA_CL H1 H2 H18 H16 H3 H22 H17 H14 H19 H21
<13,33> LUMA
L1 FCM1608C-121T_0603 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1 2 C12 JP3
47P_0402_50V8J
1
CRMA_CL 2
1
<13,33> CRMA 1 2 3
L3 FCM1608C-121T_0603
4
1 2 C11 5
47P_0402_50V8J H11 H8 H9 H13 H12 H7 H10 H4 H5 H15
6 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
COMPS_CL 7
<13,33> COMPS 1 2
L2 FCM1608C-121T_0603 S CONN._SUYIN
1
1
1 1 1 1 1 1
R7 R8 R6 C14 C15 C13 C256 C8 C7
75_0402_1% 150P_0402_50V8J 150P_0402_50V8J 270P_0402_50V7K 270P_0402_50V7K H23 H6 H20 H24 H25 H26
2 2 2 2 2 2 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
2
4 4
75_0402_1% 75_0402_1% 150P_0402_50V8J 270P_0402_50V7K
1
Compal Electronics, Inc.
Title
CRT & TVout Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 14 of 49
A B C D E
A B C D
U8A
PCI_AD0 H5 AD0
ICH4 INTRUDER# W6 INTRUDER#
<19,20,21,25> PCI_AD[0..31] PCI_AD[0..31] PCI_AD1 J3 AC3 SMLINK0
PCI_AD2 AD1 SMLINK0 SMLINK1
H3 AD2 SMLINK1 AB1
PCI_AD3 SMB_CLK
PCI_AD4
K1
G5
AD3 SM I/F SMB_CLK AC4
AB4 SMB_DATA
SMB_CLK <9,10,12> +1.8VS
AD4 SMB_DATA SMB_DATA <9,10,12>
PCI_AD5 J4 AA5 GPI11
PCI_AD6 AD5 SMB_ALERT#/GPI11
H4 AD6
PCI_AD7 J5 AD7
1
1 PCI_AD8 K2 1
PCI_AD9 AD8 HUB_VREF
G2 AD9 A20GATE Y22 GATEA20 <29>
CLK_PCI_ICH PCI_AD10 L1 AB23
AD10 A20M# H_A20M# <4>
PCI_AD11 G4 U23 R122
AD11 DPSLP# H_DPSLP# <4,7>
1
2
H2 AD13 IGNNE# W21 H_IGNNE# <4>
PCI_AD14 L3 V22
AD14 INIT# H_INIT# <4>
1
10_0402_5% PCI_AD15
PCI_AD16
F5
F4
AD15 CPU I/F INTR AB22
V21
H_INTR <4> 1 1 1
AD16 NMI H_NMI <4> C444
PCI_AD17 R123 C453 C141
2
2
E3 AD20 SMI# W23 H_SMI# <4>
2 PCI_AD21 0.01U_0402_16V7K
N3 AD21 STPCLK# V23 H_STPCLK# <4>
PCI_AD22 E4
PCI_AD23 AD22
M5 AD23 Note:
PCI_AD24 E2 R122,R123 placement
CLK_ICH_66M PCI_AD25 AD24 HUB_PD0
P1 L19
PCI_AD26 E1
AD25 HI0
L20 HUB_PD1 HUB_PD[0..10] center of MCH and
AD26 HI1 HUB_PD[0..10] <6>
1
PCI I/F
AD31 HI6 HUB_PD7
2
1 HI7 R20
P23 HUB_PD8
C460 PCI_C/BE#0 HI8 HUB_PD9
<19,20,21,25> PCI_CBE#0 J2 C/BE#0 HI9 L22
@10P_0402_50V8K PCI_C/BE#1 HUB_PD10 R339
2 <19,20,21,25> PCI_CBE#1
PCI_C/BE#2
K4
M4
C/BE#1 HUB I/F HI10 N22
K21 1 2 @56_0402_5%
<19,20,21,25> PCI_CBE#2 C/BE#2 HI11
PCI_C/BE#3 N4
<19,20,21,25> PCI_CBE#3 C/BE#3
CLK66 T21 CLK_ICH_66M CLK_ICH_66M <12>
PCI_REQ#0 B1 +3VS
2 <20> PCI_REQ#0 REQ#0 2
PCI_REQ#1 A2 P21
<19> PCI_REQ#1 REQ#1 HI_STB HUB_PSTRB <6>
PCI_REQ#2 B3 N20
<21> PCI_REQ#2 REQ#2 HI_STB# HUB_PSTRB# <6>
PCI_REQ#3 C7 SMB_CLK 1 2
<25> PCI_REQ#3 REQ#3
PCI_REQ#4 B6 R23 HUB_RCOMP_ICH R373
<25> PCI_REQ#4 REQ#4 HICOMP
M23 10K_0402_5%
HUB_VREF HUB_VREF
PCI_GNT#0 C1 R22 SMB_DATA 1 2
<20> PCI_GNT#0 GNT#0 HUB_VSWING
PCI_GNT#1 E6 R372
<19> PCI_GNT#1 GNT#1
PCI_GNT#2 A7 10K_0402_5%
<21> PCI_GNT#2 GNT#2
PCI_GNT#3 B7 J19 APICCLK
<25> PCI_GNT#3 GNT#3 APICCLK
PCI_GNT#4 D6 H19 APICD0 +3VS
<25> PCI_GNT#4 GNT#4 APICD0
K20 APICD1
APICD1
Interrupt I/F
CLK_PCI_ICH P5 D5 PCI_PIRQA#
<12> CLK_PCI_ICH PCICLK PIRQA# PCI_PIRQA# <13,20>
C2 PCI_PIRQB# PD_IRQ14 1 2
PIRQB# PCI_PIRQB# <19>
PCI_FRAME# F1 B4 PCI_PIRQC# R370
<19,20,21,25> PCI_FRAME# FRAME# PIRQC# PCI_PIRQC# <21,25>
PCI_DEVSEL# M3 A3 PCI_PIRQD# 8.2K_0402_5%
<19,20,21,25> PCI_DEVSEL# DEVSEL# PIRQD# PCI_PIRQD# <25>
PCI_IRDY# L5 C8 PCI_PIRQE# SD_IRQ15 1 2
<19,20,21,25> PCI_IRDY# IRDY# PIRQE#/GPI2
G1 D7 PCI_PIRQF# R369
PCI Pullups <19,20,21,25> PCI_PAR
PCI_PERR# L4
PAR PIRQF#/GPI3
C3 PCI_PIRQG# 8.2K_0402_5%
<19,20,21,25> PCI_PERR# PERR# PIRQG#/GPI4
PCI_LOCK# M2 C4 PCI_PIRQH#
LOCK# PIRQH#/GPI5 PD_IRQ14
W2 PME# IRQ14 AC13 PD_IRQ14 <18>
PCIRST# U5 AA19 SD_IRQ15 RP74
<7,13,19,20,21,22,25,31> PCIRST# PCIRST# IRQ15 SD_IRQ15 <18>
RP9 PCI_SERR# K5 J22 SIRQ PCI_PIRQE# 1 8
<19,21,25> PCI_SERR# SERR# SERIRQ SIRQ <21,22,29,31>
PCI_PERR# 1 10 PCI_STOP# F3 PCI_PIRQF# 2 7
+3VS <19,20,21,25> PCI_STOP# STOP#
PCI_REQA# 2 9 PCI_PIRQA# PCI_TRDY# F2 PCI_PIRQG# 3 6
<19,20,21,25> PCI_TRDY# TRDY#
PCI_STOP# 3 8 PCI_PIRQB# D10 PCI_PIRQH# 4 5
PCI_SERR# PCI_REQ#4 PCI_REQA# EE_CS
4 7 B5 REQA#/GPI0 EEPROM I/F EE_IN D11
5 6 PCI_REQB# PCI_REQB# A6 A8 1 2 8.2K _8P4R_0804_5%
+3VS REQB#/GPI1/REQ5# EE_OUT
PIDERST# E8 C12
<18> PIDERST# GNTA#/GPO16 EE_SHCLK
8.2K_10P8R_1206_5% SIDERST# C5 R85
<18> SIDERST# GNTB#/GPO17/GNT5# @1K_0402_5%
LAN_RXD0 A10
LAN_RXD1 A9
3 RP11 A11 3
PCI_IRDY# +3VS LAN_RXD2
1 10 LAN_TXD0 B10
PCI_TRDY# 2 9 PCI_PIRQC# C10 +RTCVCC
PCI_DEVSEL# 3 8 PCI_PIRQD# LAN I/F LAN_TXD1
LAN_TXD2 A12
PCI_FRAME# 4 7 SIRQ C11 INTRUDER# 1 2
PCI_LOCK# LAN_CLK
+3VS 5 6 B11 R354
LAN_RSTSYNC 330K_0402_5%
LAN_RST# Y5 1 2
8.2K_10P8R_1206_5%
R356
10K_0402_5%
FW82801DBM_BGA421
+VCCP
H_FERR# 1 2
+3VS
R358
56_0402_5%
+3VS HUB_RCOMP_ICH 1 2
RP72 R131
5
OE#
3 6 PCI_REQ#2 PCIRST# 2 4
I O B_PCIRST# <18,29>
4 5 PCI_REQ#3
G
APICD1
SMLINK0 1 R374 2
2
4.7K_0402_5%
R338 R333 R332 SMLINK1 1 R376 2
1 2 10K_0402_5% 0_0402_5% 4.7K_0402_5%
4
R347 0_0402_5% R371 2 4
GPI11
1
1
10K_0402_5%
1 2 PIDERST# 10K_0402_5%
R322 @1K_0402_5%
Title
Compal Electronics, Inc.
ICH4-M(1/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 15 of 49
A B C D
A B C D
+3VS
D12
1 2 ATF_INT# 2 1
+3VS EC_THRM# <29>
1
R141
R345 10K_0402_5%
RB751V_SOD323
100K_0402_5%
U8B D27
2
2 1
<13> AGP_BUSY#
AGP_BUSY# R2
AGPBUSY#
ICH4 GPI7 R3 RB751V_SOD323
ACIN <29,33,35,37>
1 SYSRST# Y3 V4 EC_SMI# 1
PM_BATLOW# SYSRST# GPI8 SCI# EC_SMI# <29> C486 +3VALW
AB2 V5 SCI# <29>
<29> PM_BATLOW# C3_STAT# BATLOW# GPI12 EC_LID_OUT# @1U_0805_25V4Z
<13> C3_STAT# T3 C3_STAT# GPI13 W3 EC_LID_OUT# <29>
<19,21,22,25,29> PM_CLKRUN# AC2
PM_DPRSLPVR V20 CLKRUN# GPIO GPIO25 V2
W1
EC_FLASH# <30> 1 2
<41> PM_DPRSLPVR DPRSLPVR GPIO27
5
<29> PWRBTN_OUT# AA1 W4
PWRBTN# GPIO28
AB6 1 2 1
<32> PM_POK EC_RIOUT# PWROK +3VS R390 @10K_0402_5% SYSRST#
<29> EC_RIOUT# Y1 RI# 4
PM_RSMRST#
<21,29> PM_RSMRST# AA6
W18
RSMRST# PM AA13 PD_A0 <4> ITP_DBRESET# 2
<12,29> SLP_S1# SLP_S1# PDA0 PD_A0 <18>
<29,33> SLP_S3# Y4 AB13 PD_A1 U38
SLP_S3# PDA1 PD_A1 <18>
PD_A2 @74AHC1G08
3
<29> SLP_S4# Y2 SLP_S4# PDA2 W13 PD_A2 <18>
<29> SLP_S5# SLP_S5# AA2 Y13 PD_CS#1
SLP_S5# PDCS1# PD_CS#1 <18>
W19 AB14 PD_CS#3
<12,41> STP_CPU# STP_CPU# PDCS3# PD_CS#3 <18>
<12> STP_PCI# Y21 STP_PCI#
AA4 AA11 PD_DREQ 2 1
SUS_CLK PDDREQ PD_DREQ <18>
SUS_STAT# AB3 Y12 PD_DACK# R385 0_0402_5%
<13,30> SUS_STAT# SUS_STAT#/LPCPD# PDDACK# PD_DACK# <18>
ATF_INT# V1 AC12 PD_IOR# PD_D[0..15]
THRM# PDIOR# PD_IOR# <18> PD_D[0..15] <18>
W12 PD_IOW#
PDIOW# PD_IOW# <18>
AB12 PD_PIORDY
PIORDY PD_PIORDY <18>
+VCCP SD_D[0..15]
SD_D[0..15] <18>
J21 AB11 PD_D0
CPUPERF# SSMUXSEL PDD0 PD_D1
1 2 CPUPERF#
Y20
V19
CPUPERF# IST PDD1 AC11
Y10 PD_D2
R355 <12,32,41> VGATE VGATE/VRMPWRGD PDD2 PD_D3
PDD3 AA10
8.2K_0402_5% PD_D4
AC97_BITCLK B8
AC97 I/F PDD4 AA7
AB8 PD_D5
+3VS <23,25,28> AC97_BITCLK AC_BITCLK PDD5 PD_D6 CLK_ICH_14M
<23,25,28> AC97_RST# C13 AC_RST# PDD6 Y8
AC97_SDIN0 PD_D7
<23> AC97_SDIN0 D13 AC_SDATAIN0 IDE I/F PDD7 AA8
1
AC97_SDIN1 A13 AB9 PD_D8
PM_CLKRUN# <28> AC97_SDIN1 AC97_SDIN2 AC_SDATAIN1 PDD8 PD_D9
2 1 B13 Y9
R375 <25> AC97_SDIN2 ICH_AC_SDOUT AC_SDATAIN2 PDD9 PD_D10 R336
D9 AC_SDATAOUT PDD10 AC9
2 10K_0402_5% ICH_AC_SYNC PD_D11 @22_0402_5% 2
C9 AC_SYNC PDD11 W9
AB10 PD_D12
+3VS PDD12 PD_D13
2
PDD13 W10 1
LPC_AD0 T2 W11 PD_D14
<22,29,31> LPC_AD0 LPC_AD1 LPC_AD0 PDD14 PD_D15 C438
<22,29,31> LPC_AD1 R4 LPC_AD1 PDD15 Y11
1 2 SB_SPKR LPC_AD2 T4 @10P_0402_50V8K
R117 <22,29,31> LPC_AD2 LPC_AD3 LPC_AD2 SD_A0 2
@1K_0402_5% <22,29,31> LPC_AD3 LPC_DRQ#0
U2
U3
LPC_AD3 LPC I/F SDA0 AA20
AC20 SD_A1
SD_A0 <18>
<29,31> LPC_DRQ#0 LPC_DRQ#0 SDA1 SD_A1 <18>
+3VS <22> LPC_DRQ#1 LPC_DRQ#1 U4 AC21 SD_A2
LPC_DRQ#1 SDA2 SD_A2 <18>
LPC_FRAME# T5 AB21 SD_CS#1
<22,29,31> LPC_FRAME# LPC_FRAME# SDCS1# SD_CS#1 <18>
AC22 SD_CS#3
ICH_AC_SDOUT SDCS3# SD_CS#3 <18>
2 1 CLK_ICH_48M
R325 AB18 SD_DREQ
SDDREQ SD_DREQ <18>
1
@10K_0402_5% C20 AB19 SD_DACK#
+3VS <27> USB20P0+ USBP0+ SDDACK# SD_DACK# <18>
D20 Y18 SD_IOR# R331
<27> USB20P0- USBP0- SDIOR# SD_IOR# <18>
A21 AA18 SD_IOW# @22_0402_5%
<27> USB20P1+ USBP1+ SDIOW# SD_IOW# <18>
B21 AC19 SD_SIORDY
AGP_BUSY# <27> USB20P1- USBP1- SIORDY SD_SIORDY <18>
2 1 <33> USB20P2+ C18 USBP2+
R130 SD_D0
2
<33> USB20P2- D18 USBP2- SDD0 W17 1
10K_0402_5% A19 AB17 SD_D1
<33> USB20P3+ USBP3+ SDD1
B19 W16 SD_D2 C420
<33> USB20P3- USBP3- SDD2 @10P_0402_50V8K
C16 AC16 SD_D3
<27> USB20P4+ USBP4+ SDD3 2
+3VALW D16 W15 SD_D4
<27> USB20P4- USBP4- SDD4
A17 AB15 SD_D5
<28,31> USB20P5+ USBP5+ SDD5
RP73 SD_D6
<28,31> USB20P5- B17 USBP5- USB I/F SDD6 W14
AA14 SD_D7
OVCUR#1 SDD7 SD_D8
1 8 SDD8 Y14
2 7 OVCUR#2 OVCUR#0 B15 AC15 SD_D9
<27> OVCUR#0 OC#0 SDD9
3 6 OVCUR#3 OVCUR#1 C14 AA15 SD_D10
OVCUR#5 OVCUR#2 OC#1 SDD10 SD_D11
4 5 A15 OC#2 SDD11 Y15
OVCUR#3 B14 AB16 SD_D12
10K_8P4R_0804_5% OVCUR#4 OC#3 SDD12 SD_D13 +RTCVCC
<27> OVCUR#4 A14 OC#4 SDD13 Y16
3 OVCUR#5 D14 AA17 SD_D14 3
PM_RSMRST# OC#5 SDD14 SD_D15
2 1 SDD15 Y17
R368 10K_0402_5% USB_RBIAS A23 USB_RBIAS
2 R95 1 B23 USB_RBIAS# 1 2
2 1 PM_DPRSLPVR 1 R353
22.6_0402_1%
R446 @10K_0402_5% J23 CLK_ICH_14M 180K_0402_5%
CLK14 CLK_ICH_14M <12>
F19 CLK_ICH_48M 2 1 C461
CLK48 CLK_ICH_48M <12>
J20 0.1U_0402_16V4Z
GPIO32 RTC_RST# J2 2
G22 GPIO33 RTCRST# W7
VB0 F20 JOPEN
<13> VB0 GPIO34
VB1 VBIAS 2R_VBIAS 1
<13> VB1
VB2
G20
F21
GPIO35 CLOCK VBIAS Y6 1
R389
2
<13> VB2 GPIO36
BID0 H20 AC7 RTCX1 C481 1K_0402_5%
BID1 GPIO37 RTCX1 0.047U_0603_16V7K
F23 GPIO38
+3VS BID2 RTCX2
H22
G23
GPIO39 GPIO RTCX2 AC6 1
R196
2
GPIO40 10M_0603_5%
H21 GPIO41
F22 GPIO42 SPKR H23 SB_SPKR SB_SPKR <23>
1
E23 GPIO43 2 1 1 2 2 1
R337 R100 R106 W20 THRMTRIP# R384 R383
MISC THRMTRIP# THRMTRIP# <4>
2
1 X2 1 10M_0603_5% @22M_0603_5%
@0_0402_5% @0_0402_5% @0_0402_5% 32.768KHz_12.5P_CM155
C203 C190 R197
BID0 FW82801DBM_BGA421 15P_0402_50V8J 15P_0402_50V8J @2.4M_0603_1%
2
BID1 2 2
BID2
1
1
<23,25,28> AC97_SDOUT 1 2
1 1 R320
33_0402_5%
C391 C390
@22P_0402_50V8J @22P_0402_50V8J
2 2
Title
Compal Electronics, Inc.
ICH4-M(2/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 16 of 49
A B C D
A B C D E F G H
U8C +3VS
+3VS +1.5VALW +3VS
D22 VSS0
ICH4 VCC3.3_0 A5 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
E10 VSS1 VCC3.3_1 AC17 1 1 1 1 1 1 1 1 1 1
E14 VSS2 VCC3.3_2 AC8
E16 B2 C458 C435 C456 C446 C437 C436 C424 C426 C455 C451
VSS3 VCC3.3_3 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
E17 VSS4 VCC3.3_4 H18
E18 H6 2 2 2 2 2 2 2 2 2 2
VSS5 VCC3.3_5 0.1U_0402_16V7K 0.1U_0402_16V7K
E19 VSS6 VCC3.3_6 J1
E21 VSS7 VCC3.3_7 J18
E22 VSS8 VCC3.3_8 K6
1 F8 M10 +1.5VS 1
VSS9 VCC3.3_9 +1.5VS
G19 VSS10 VCC3.3_10 P12
G21 P6 +1.5VS
VSS11 VCC3.3_11
G3 VSS12 VCC3.3_12 U1 1 1
G6 VSS13 VCC3.3_13 V10 1 1
H1 V16 C442 C441 1 1
VSS14 VCC3.3_14 0.1U_0402_16V7K 0.1U_0402_16V7K C454 C443
J6 VSS15 VCC3.3_15 V18
+3VALW 2 2 C450 C457 0.1U_0402_16V7K 0.01U_0402_16V7K
K11 VSS16 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2
K13 VSS17 2 2
K19 VSS18 VCCSUS3.3_0 E11 VCC1.5 power place
K23 VSS19 VCCSUS3.3_1 F10
K3 VSS20 VCCSUS3.3_2 F15
+3VALW
VCCLAN1.5 power place VCCPLL power place
L10 VSS21 VCCSUS3.3_3 F16
L11 VSS22 VCCSUS3.3_4 F17
L12 F18 0.1U_0402_16V7K +1.8VS +VCCP
VSS23 VCCSUS3.3_5
L13 VSS24 VCCSUS3.3_6 K14 1 1 1
L14 VSS25 VCCSUS3.3_7 V7
L21 V8 C423 C459 C425 1 1 1
VSS26 VCCSUS3.3_8 0.1U_0402_16V7K 0.1U_0402_16V7K
M1 VSS27 VCCSUS3.3_9 V9 C449
2 2 2 C452 C445
M11 VSS28 0.1U_0402_16V7K 0.1U_0402_16V7K
M12 +1.5VS 0.1U_0402_16V7K
VSS29 2 2 2
M13
M20
VSS30 GND POWER K10
VSS31 VCC1.5_0
M22
N10
VSS32 VCC1.5_1 K12
K18
VCCHI power place
VSS33 VCC1.5_2
N11 VSS34 VCC1.5_3 K22
N12 VSS35 VCC1.5_4 P10
N13 VSS36 VCC1.5_5 T18
N14 VSS37 VCC1.5_6 U19
N19 VSS38 VCC1.5_7 V14
N21 +1.5VALW
VSS39
N23 VSS40
2 2
N5 VSS41 VCCSUS1.5_0 E12
P11 VSS42 VCCSUS1.5_1 E13
P13 VSS43 VCCSUS1.5_2 E20
P20 VSS44 VCCSUS1.5_3 F14
P22 VSS45 VCCSUS1.5_4 G18
P3 R6 +3VALW +5VALW +3VS +5VS
VSS46 VCCSUS1.5_5
R18 VSS47 VCCSUS1.5_6 T6
R21 VSS48 VCCSUS1.5_7 U6
1
R5 VSS49
T1 D19 R319 D20 R323
VSS50 VCC5REF 1K_0402_5% 1K_0402_5%
T19 VSS51 VCC5REF1 E7 1SS355_SOD323 1SS355_SOD323
T23 VSS52 VCC5REF2 V6
U20 VSS53 VCC5REFSUS VCC5REFSUS VCC5REF
2
V15 VSS54 VCC5REFSUS1 E15
V17 +1.8VS
VSS55
V3 VSS56 1 1
W22 VSS57 VCCHI_0 L23
W5 M14 C414 C415
VSS58 VCCHI_1 0.1U_0402_16V7K 0.1U_0402_16V7K
W8 VSS59 VCCHI_2 P18
2 2
Y19 VSS60 VCCHI_3 T22
Y7 +VCCP
VSS61
A16 VSS62
A18 VSS63 VCC_CPU_IO_0 AA23
A20 VSS64 VCC_CPU_IO_1 P14
A22 VSS65 VCC_CPU_IO_2 U18
A4 VSS66
AA12 VSS67
AA16 VSS68 VCCPLL C22 +1.5VS
AA22 VSS69
AA3 VSS70
AA9 VSS71 VCCRTC AB5 +RTCVCC
AB20 VSS72
3 AB7 3
VSS73
AC1 VSS74
AC10 VSS75 VCCLAN3.3_0 E9 +3VALW
AC14 VSS76 VCCLAN3.3_1 F9
AC18 VSS77
AC23 VSS78
AC5 F6 +RTCVCC RTCVREF
VSS79 VCCLAN1.5_0 +1.5VALW
B12 F7 D25
B16
B18
VSS80
VSS81
VSS82
VCCLAN1.5_1
1
R310
2 1
3
R445
BATT1.1
+ JP27
-
B20 2 BATT1.2 1 2 1 2
VSS83 100_0603_1% W=20mils
B22 VSS84 2
B9 DAN202U_SC70 511_0603_1%
VSS85 C467
C15 VSS86
C17 0.1U_0402_16V7K ML1220
VSS87 1
C19 VSS88
C21 VSS89
C23 VSS90
C6 VSS91
D1 VSS92
D12 VSS93
D15 VSS94
D17 VSS95
D19 VSS96
D21 VSS97
D23 VSS98
D4 VSS99
D8 VSS100
A1 VSS101
4 FW82801DBM_BGA421 4
Title
Compal Electronics, Inc.
ICH4-M(3/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 17 of 49
A B C D E F G H
5 4 3 2 1
+5VS
1 1 1 1
14
U40A
D B_PCIRST# 1 D
P
<15,29> B_PCIRST# I0
3 HD_RST# <16> PD_D[0..15] PD_D[0..15]
O
<15> PIDERST# 2
I1
G
74HCT08PW_TSSOP14
R397
7
1 2
JP25
@10K_0402_5%
HD_RST# 1 2
PD_D7 1 2 PD_D8
3 3 4 4
PD_D6 5 6 PD_D9
PD_D5 5 6 PD_D10
7 7 8 8
U40B PD_D4 9 10 PD_D11
PD_D3 9 10 PD_D12
<15> SIDERST# 4 11 12
I0 CD_RST# PD_D2 11 12 PD_D13
6 13 14
B_PCIRST# O PD_D1 13 14 PD_D14
5 I1 15 15 16 16
PD_D0 17 18 PD_D15
74HCT08PW_TSSOP14 17 18
19 20
PD_DREQ 19 20
<16> PD_DREQ 21 22
PD_IOW# 21 22
<16> PD_IOW# 23 24
PD_IOR# 23 24
<16> PD_IOR# 25 26
PD_PIORDY 25 26 PD_CSEL 1
<16> PD_PIORDY 27 27 28 28 2
PD_DACK# 29 30 R400 470_0402_5%
<16> PD_DACK# 29 30
U40C 1 2 <15> PD_IRQ14 PD_IRQ14 31 32
+3VS 31 32
HDD_LED# 9 R399 PD_A1 33 34
I0 <16> PD_A1 33 34
8 4.7K_0402_5% PD_A0 35 36 PD_A2
O DEV_LED# <28> <16> PD_A0 35 36 PD_A2 <16>
ODD_LED# 10 PD_CS#1 37 38 PD_CS#3
I1 <16> PD_CS#1 37 38 PD_CS#3 <16>
HDD_LED# 39 40
74HCT08PW_TSSOP14 39 40
+5VS 41 42 +5VS
41 42
+5VS 1 2 43 44
R398 100K_0402_5% 43 44
HDD CONN
C C
+5VS
1 1
1
C555 C554
C553 0.1U_0402_16V7K 1000P_0402_50V7K
10U_1206_16V4Z 2 2
2
Place component's closely IDE CONN.
SD_D[0..15]
<16> SD_D[0..15]
C235
2 1
B 10U_1206_6.3V6M CD_AGND B
2 1 CD_AGND <23>
R237 @10K_0402_5%
JP23
CDROM_L CDROM_R
<23> CDROM_L 1 2 CDROM_R <23>
CD_RST# 3 4 SD_D8
SD_D7 5 6 SD_D9
SD_D6 7 8 SD_D10
SD_D5 9 10 SD_D11
SD_D4 11 12 SD_D12
Unused GATE SD_D3
SD_D2
13
15
14
16
SD_D13
SD_D14
U40D SD_D1 17 18 SD_D15
SD_D0 19 20 SD_DREQ
12 I0 <16> SD_SIORDY 21 22 SD_DREQ <16>
11 SD_IOR#
O 23 24 SD_IOR# <16>
13 SD_IOW#
I1 <16> SD_IOW# 25 26
1 2 SD_DACK#
+3VS 27 28 SD_DACK# <16>
74HCT08PW_TSSOP14 R239 SD_IRQ15
<15> SD_IRQ15 29 30
4.7K_0402_5% <16> SD_A1 31 32
PDIAG# 1 R240 2 100K_0402_5%
+5VS
<16> SD_A0 33 34 SD_A2 <16>
SD_CS#1 SD_CS#3
<16> SD_CS#1 35 36 SD_CS#3 <16>
ODD_LED# W=80mils
37 38 +5VS
1 2 +5VS +5VS
+5VS R396 100K_0402_5% 39 40
+5VS 41 42 +5VS
43 44 2 1
R241 100K_0402_5%
R242 CD-ROM CONN.
470_0402_5%
A A
1
JP4
<33> RJ45_TXX+ RJ45_TXX+ 8 13
Q32 TX+ NC
SI2301DS_SOT23 <33> RJ45_TXX- RJ45_TXX- 7 TX- LAN_LED1#
CATHODE1 16
1 3 +3VALW RJ45_RXX+ 6
LANVDD <33> RJ45_RXX+ RX+
D LANGND 2 LANGND_1 D
1
75_0402_1% R248
5 N/C1 GREEN-LINK
LINK_CR 2 R261 1
2
EN_WOL# <29> 4 N/C2 ANODE1 15 LANVDD
330_0402_5%
RJ45_RXX- 3
<33> RJ45_RXX- RX-
LANGND 1 2 LANGND_2 2
75_0402_1% R249 N/C3
R262
1 17 ACT_CR 2 1
N/C4 CATHODE2 LANVDD
330_0402_5%
PCI_AD[0..31] U5 MOD_RING
<15,20,21,25> PCI_AD[0..31]
PCI_AD0 45 50 EECS 2
9 N/C5 YELLOW-ACT
AD0 EECS
1
PCI_AD1 44 10 18 LAN_LED0#
PCI_AD2 AD1 U34 C331 VH1 RING ANODE2
43
1
PCI_AD3 AD2 EEDO 0.1U_0402_10V6K
42 47 4 5 DSSA-P3100SB 11
AD3 MA0/EEDO DO GND 1 TIP
2
PCI_AD4 41 48 EEDI 3 6
PCI_AD5 AD4 MA1/EEDI EESK DI NC
39 49 2 7 12 14 1 1
PCI_AD6 AD5 MA2/EESK EECS SK NC MOD_TIP N/C6 NC
2
38 AD6 MA3 51 1 CS VCC 8 LANVDD 1 1
PCI_AD7 37 52 C267 C268
PCI_AD8 AD7 MA4 AT93C46-10SI-2.7_SO8 C260 C259 RJ-45 & RJ-11 1000P_0402_50V7K 1000P_0402_50V7K
34 AD8 MA5 53
PCI_AD9 220P_1808_3KV8K 220P_1808_3KV8K 2 2
33 AD9 MA6/9356SEL 57
PCI_AD10 2 2
32 AD10 MA7 60
PCI_AD11 31 61 1 2
AD11 MA8/Aux. PWR LANVDD
PCI_AD12 29 63 R294 5.6K_0402_5%
PCI_AD13 AD12 MA9
28 AD13 MA10 64
PCI_AD14 27 65 JP9
PCI_AD15 AD14 MA11 MOD_TIP
26 AD15 MA12 66
PCI_AD16 MOD_RING 1
13 AD16 MA13 67 2
PCI_AD17 11 68
PCI_AD18 AD17 MA14 MODEM CONN.
10 AD18 MA15 69
PCI_AD19 9 70
C PCI_AD20 AD19 MA16 C
8 AD20
PCI_AD21 6
PCI_AD22 AD21
5 AD22
PCI_AD23 4 108
PCI I/F
AD23
LAN I/F MD0
PCI_AD24 128 107
PCI_AD25 AD24 MD1
127 AD25 MD2 105
PCI_AD26 126 104 LANVDD
PCI_AD27 AD26 MD3
125 AD27 MD4 103
PCI_AD28 123 102
PCI_AD29 AD28 MD5
122 AD29 MD6 101
1
PCI_AD30 121 100 2
PCI_AD31 AD30 MD7
120 AD31 R276
PCI_CBE#[0..3] C285
<15,20,21,25> PCI_CBE#[0..3] 0_0402_5% 0.1U_0402_10V6K
PCI_CBE#0 36 99 LAN_LED0#
C/BE#0 LED0 LAN_LED0# <33> 1
PCI_CBE#1 24 98 LAN_LED1#
C/BE#1 LED1 LAN_LED1# <33>
1
PCI_CBE#2 R44 1 2 15K_0402_5%
2
14 C/BE#2 LED2 97
PCI_CBE#3 2 C/BE#3 ISOB R39 2 R41 R40
ISOLATE# 95 1 1K_0402_5% +3VS
PCI_AD17 49.9_0402_1% 49.9_0402_1%
1 2 3 IDSEL
R83 100_0402_5% 92 LAN_TX+
TXD+ LAN_TX-
2
23 91
<15,20,21,25> PCI_PAR
<15,20,21,25> PCI_FRAME# 15
PAR
FRAME#
TXD-
RXIN+ 87 LAN_RX+
U1 1:1
<15,20,21,25> PCI_IRDY# 16 86 LAN_RX-
IRDY# RXIN- LAN_TX- RJ45_TXX-
<15,20,21,25> PCI_TRDY# 17 TRDY# 8 9
LAN_TX+ TD- TX- RJ45_TXX+
<15,20,21,25> PCI_DEVSEL# 19 DEVSEL# WE# 89 7 10
TD+ TX+
<15,20,21,25> PCI_STOP# 20 STOP# OE# 88 6 CT CT 11
C40
21 0.1U_0402_10V6K
<15,20,21,25> PCI_PERR# PERR#
<15,21,25> PCI_SERR# 22 SERR# LWAKE 83 1 2 3 CT CT 14
LAN_RX- 2 15 RJ45_RXX-
LAN_RX+ RD- RX- RJ45_RXX+
<15> PCI_REQ#1 118 REQ# RTT2 82 1 RD+ RX+ 16
1
<15> PCI_GNT#1 117 GNT# RTT3 81
1
B B
Y1 R12 R13
<15> PCI_PIRQB# 114 INTA# CLKOUT XTALFB R34 R33 NS0013_16P 75_0402_1% 75_0402_1%
76 79 CLKOUT 49.9_0402_1% 49.9_0402_1%
<21,25,29> ONBD_LAN_PME# PME# X1 XTALFB 25MHz_25ppm LANGND
2
X2 78 1 2
CRYSTAL
2
115 1
<7,13,15,20,21,22,25,31> PCIRST# RST# C47 C57
RTSET 84 2 1 2
116 R43 1.69K_0603_1% 27P_0402_50V8J 27P_0402_50V8J C16
<12> CLK_PCI_LAN CLK 2 1 1000P_1206_2KV7K
75 110 C48
<16,21,22,25,29> PM_CLKRUN# CLKRUN# ROMCS# 0.1U_0402_10V6K 2
CHASSIS GND
1
7 GND NC 54
18 GND NC 71
30 72
40
55
GND
GND
GND
Power NC
NC
NC
73
94 LANVDD
1
56 GND
R58 62 1
GND VDD
74 GND VDD 12 1 1 1 1 1 1 2
10_0402_5% 80 25 C80 C375 C354 C376 C377 C66
GND VDD C317
85 GND VDD 35
10U_0805_10V4Z 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2
1 93 GND VDD 46
C73 111 58 2 2 2 2 2 2 1
GND VDD
112 GND VDD 59
10P_0402_50V8K 113 77
2 GND VDD
124 GND VDD 90
VDD 96 2 2 2 2 2 2 2
106 C318 C329 C63 C314 C313 C312 C378
VDD
VDD 109
119 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
VDD 1 1 1 1 1 1 1
RTL8139CL_LQFP128
A A
110
122
111
+3VS 1394@0.1U_0402_10V6K 1394@0.1U_0402_10V6K 1394@0.1U_0402_10V6K 1394@0.1U_0402_10V6K
99
17
32
21
30
36
46
47
38
59
56
73
66
5
U2
PCI_AD[0..31]
RAMVDD
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDDC2
VDDC1
PVDD1
PVDD2
PGND2
PGND1
VDDATX0
GNDATX0
VDDATX1
GNDATX1
<15,19,21,25> PCI_AD[0..31]
PCI_AD0 25
PCI_AD1 AD0
24
PCI_AD2 AD1
20
PCI_AD3 AD2 +3VS
19 87 1
PCI_AD4 AD3 VDDATX2 U28
18 AD4
PCI_AD5 16 C295 1394@0.1U_0402_10V6K 1 8
PCI_AD6 AD5 A0 VCC
15 2 7
PCI_AD7 AD6 2 A1 WC EECK_1394
14 80 3 6
AD7 GNDATX2 A2 SCL
1
PCI_AD8 11 62 1 4 5 EEDI_1394
PCI_AD9 AD8 VDDARX0 GND SDA R247
10
PCI_AD10 AD9 C19 1394@0.1U_0402_10V6K 1394@AT24C02N-10SC-2.7_SO8 1394@510_0402_5%
9 AD10
PCI_AD11 8 61
PCI_AD12 AD11 GNDARX0 2
7 72 1
PCI_AD13 AD12 VDDARX1
2
4
PCI_AD14 AD13 C284 1394@0.1U_0402_10V6K
3
PCI_AD15 AD14
2 65
PCI_AD16 AD15 GNDARX1 2
117 AD16 VDDARX2 86 1
PCI_AD17 116
PCI_AD18 AD17 C287 1394@0.1U_0402_10V6K
115
AD18
2
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
114
113
109
107
AD19
AD20
AD21
IEEE 1394 GNDARX2 79
26
2
+3VS
Place close to 1394 chip 2
PCI_AD23
PCI_AD24
106
103
AD22
AD23
AD24 VT6307S EECS
EEDO
SDA/EEDI
27
28 EEDI_1394 1
1
PCI_AD25 102 29 EECK_1394
PCI_AD26 AD25 SCL/EECK R272 R253 R252 C258
101
PCI_AD27 AD26 1394@1K_0402_5% 1394@54.9_0402_1% 1394@0.33U_0805_16V7K
98 34
PCI_AD28 AD27 PME# 1394@54.9_0402_1%2
97 AD28 NC1 39
PCI_AD29 96 40
PCI_AD30 AD29 NC2 XTPBIAS0 JP5
2
95
PCI_AD31 AD30 XTPA0+
94 60
PCI_CBE#[0..3] AD31 XCPS XTPA0- 4
<15,19,21,25> PCI_CBE#[0..3] 3
PCI_CBE#0 12 63 1394_XREXT XTPB0+
PCI_CBE#1 CBE0# XREXT XTPB0- 2
1
CBE1# 1
2
PCI_CBE#2 119 67 XTPB0-
PCI_CBE#3 CBE2# XTPB0M XTPB0+ R270 1394@1394_FOX
104 68
CBE3# XTPB0P
1
69 XTPA0- 1394@1K_0402_5%
PCI_AD16 XTPA0M
1 R49 2 105 70 XTPA0+ R251 R250
IDSEL XTPA0P
2
<15,19,21,25> PCI_FRAME# 1394@100_0402_5% 120 71 XTPBIAS0 2
FRAME# XTPBIAS0 1394@54.9_0402_1% 1394@54.9_0402_1%
1
<15,19,21,25> PCI_IRDY# 121 IRDY#
<15,19,21,25> PCI_TRDY# 123 74 XTPB1- R274 C283
TRDY# XTPB1M XTPB1+
2
124 75
2
<15,19,21,25> PCI_DEVSEL# DEVSEL# XTPB1P 1 1394@47P_0402_50V8J
125 76 XTPA1- 1394@6.34K_0603_1%
<15,19,21,25> PCI_STOP# STOP# XTPA1M XTPA1+
1
<15,19,21,25> PCI_PERR# 127 77 1
PERR# XTPA1P
1
<15,19,21,25> PCI_PAR 128 78 XTPBIAS1
PAR XTPBIAS1 C262 R260
<15> PCI_REQ#0 93
REQ#
<15> PCI_GNT#0 92 81
GNT# NC3 1394@270P_0402_25V8K 2 1394@5.1K_0603_1%
<13,15> PCI_PIRQA# 88 82
INTA# NC4
89 83
<7,13,15,19,21,22,25,31> PCIRST# PCIRST# NC5
I2CEEENA
CLK_PCI_1394 C17
2
90 84
RAMVSS
NC7
NC21
NC20
NC19
NC18
NC17
NC16
NC15
NC14
NC13
NC12
NC11
NC10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
55 2 1
NC9
NC8
PHYRESET
XO
XI
3 3
1
VT6307S-CD_LQFP128 X3
112
126
118
108
100
1
22
33
23
13
91
31
64
54
53
52
51
50
49
48
45
44
43
42
41
37
35
57
58
1
R35 XI 1 XO
6
2
R26 R25 C29
10_0402_5% 1394@24.576MHz_16P_3XG-24576-43E1 1394@54.9_0402_1% 1394@0.33U_0805_16V7K
2
1394@54.9_0402_1%
2
1 2
XO
R275 XTPBIAS1
XI
2
1 2 2
1
1
Place close to 1394 CONN.
R20 R21
+3VS
XTPA0+
XTPA0- 1394@54.9_0402_1% 1394@54.9_0402_1%
XTPB0+
XTPB0-
2
1 1 1 1
2
TVS6 TVS7 TVS8 TVS9 1
1
@SF10402ML080C @SF10402ML080C C23 R19
1394@270P_0402_50V7K 1394@5.1K_0603_1%
2 2 2 2 2
@SF10402ML080C @SF10402ML080C
2
4 4
+12VALW S1_VCC
1 1
U3
C33 13 C44
0.1U_0402_16V7K VCC 4.7U_0805_10V4Z
VCC 12
2 9 11 2
12V VCC S1_VPP S1_VCC
+5VALW 0.1U_0402_16V7K
1 1 1
1 10 +3V_CB 1
VPP C35 C296 C60
1
5 0.1U_0402_16V7K 0.1U_0402_16V7K
C39 5V 2 2 2
6
0.1U_0402_16V7K 5V
2 1 1
1 VCCD0#
VCCD0 VCCD1# C36 C304 S1_VPP S1_VCC
2 1 R23 2 +3VS
+3VALW VCCD1 VPPD0 4.7U_0805_10V4Z @0_1206_5%
VPPD0 15
VPPD1 2 2 J11
VPPD1 14 1 2 +3VALW
0.1U_0402_16V7K R30 0_1206_5% 1 1 1 1
3
3.3V +3VALW C355 10U_1206_16V4Z C343 C339
1 4 8 C358
3.3V OC
SHDN
GND VPPD0 4.7U_1206_25VFZ 0.1U_0402_16V4Z 0.1U_0402_16V7K
C46 VPPD1 2 2 2 2
1 2
0.1U_0402_16V7K VCCD0# C274 0.1U_0402_16V7K CARDBUS HOUSING
2 CP-2211_SSOP16 VCCD1#
16
7
JP11
126
138
122
102
PM_RSMRST#
74
73
72
71
44
18
90
86
50
30
14
63
a68 a68
U31 a34
PCI_AD[0..31] S1_CD2# a34
a67
VPPD1
VPPD0
VCCD1#
VCCD0#
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCCI
VCCP0
VCCP1
VCCSK0
VCCSK1
<15,19,20,25> PCI_AD[0..31] a67
S1_WP a33
PCI_CBE#[0..3] S1_D10 a33
<15,19,20,25> PCI_CBE#[0..3] a66 a66
S1_D2 a32
S1_D9 a32
a65 a65
PCI_AD31 3 144 S1_D10 S1_D1 a31
PCI_AD30 AD31 CAD31/D10 S1_D9 S1_D8 a31
4 AD30 CAD30/D9 142 a64 a64
PCI_AD29 5 141 S1_D1 S1_D0 a30
PCI_AD28 AD29 CAD29/D1 S1_D8 S1_BVD1 a30
7 AD28 CAD28/D8 140 a63 a63
+3V_CB PCI_AD27 8 139 S1_D0 S1_A0 a29
PCI_AD26 AD27 CAD27/D0 S1_A0 S1_BVD2 a29
9 AD26 129 a62
PCI_AD25 CAD26/A0 S1_A1 S1_A1 a62
10 AD25 128 a28
2 PCI_AD24 CAD25/A1 S1_A2 S1_REG# a28 2
1 1 1 1 1 1 1 11 AD24 CAD24/A2 127 a61 a61
C61 C59 C299 C297 C289 C275 C22 PCI_AD23 15 124 S1_A3 S1_VCC S1_A2 a27
PCI_AD22 AD23 CAD23/A3 S1_A4 S1_INPACK# a27
16 AD22 CAD22/A4 121 a60 a60
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PCI_AD21 17 120 S1_A5 S1_A3 a26
2 2 0.1U_0402_16V7K
2 2 0.1U_0402_16V7K
2 2 0.1U_0402_16V7K
2 PCI_AD20 AD21 CAD21/A5 S1_A6 S1_WAIT# a26
19 118 a59
AD20 CAD20/A6 a59
1
PCI_AD19 23 116 S1_A25 S1_A4 a25
PCI_AD18 AD19 CAD19/A25 S1_A7 S1_RST a25
24 AD18 CAD18/A7 115 a58 a58
PCI_AD17 25 113 S1_A24 R282 S1_A5 a24
PCI_AD16 AD17 CAD17/A24 S1_A17 47K_0402_5% S1_VS2 a24
26 98 a57
PCI_AD15 AD16 CAD16/A17 S1_IOWR# S1_A6 a57
38 96 a23
PCI_AD14 AD15 CAD15/IOWR# S1_A9 S1_A25 a23
2
39 97 a56
PCI_AD13 AD14 CAD14/A9 S1_IORD# S1_A7 a56
40 93 a22
PCI_AD12 AD13 CAD13/IORD# S1_A11 S1_A24 a22
41 95 a55
PCI_AD11 AD12 CAD12/A11 S1_OE# S1_A12 a55
43 AD11 CAD11/OE# 92 a21 a21
PCI_AD10 45 91 S1_CE2# S1_A23 a54
PCI_AD9 AD10 CAD10/CE2# S1_A10 S1_A15 a54
46 AD9 89 a20
PCI_AD8 CAD9/A10 S1_D15 S1_A22 a20
47 AD8 87 a53
PCI_AD7 CAD8/D15 S1_D7 S1_A16 a53
49 85 a19
PCI_AD6 AD7 CAD7/D7 S1_D13 a19
51 AD6 CAD6/D13 82 S1_VPP a52 a52
PCI_AD5 52 83 S1_D6 a18
PCI_AD4 AD5 CAD5/D6 S1_D12 a18
53 AD4 80 S1_VCC a51
PCI_AD3 CAD4/D12 S1_D5 a51
54 AD3 81 a17
PCI_AD2 CAD3/D5 S1_D11 S1_VCC S1_A21 a17
55 77 a50
PCI_AD1 AD2 CAD2/D11 S1_D4 S1_RDY# a50
PCI_AD0
56
57
AD1 PQFP 144 CAD1/D4
79
76 S1_D3 1 2 S1_A23 S1_A20
a16
a49
a16
AD0 CAD0/D3 a49
PCI_CBE#3
22.2 X 22.2 X 1.60 S1_REG#
R51 @22K_0402
S1_WP
S1_WE#
S1_A19
a15
a15
12 C/BE3# CC/BE3#/REG# 125 1 2 a48 a48
PCI_CBE#2 27 112 S1_A12 R50 @22K_0402 S1_A14 a14
PCI_CBE#1 C/BE2# CC/BE2#/A12 S1_A8 S1_RST S1_A18 a14
37 99 1 2 a47
PCI_CBE#0 C/BE1# CC/BE1#/A8 S1_CE1# R447 @47K_0402_5% S1_A13 a47
48 88 a13
C/BE0# CC/BE0#/CE1# S1_CE1# S1_A17 a13
1 2 a46 a46
20 119 S1_RST R448 @47K_0402_5% S1_A8 a12
3 <7,13,15,19,20,22,25,31> PCIRST# RST# CRST#/RESET S1_CE2# a12 3
<15,19,20,25> PCI_FRAME# 28 111 S1_A23 1 2 S1_IOWR# a45
FRAME# CFRAME#/A23 S1_A15 R449 @47K_0402_5% S1_A9 a45
<15,19,20,25> PCI_IRDY# 29 IRDY# CIRDY#/A15 110 a11
+12VS S1_A22 S1_IORD# a11
<15,19,20,25> PCI_TRDY# 31 109 a44
TRDY# CTRDY#/A22 S1_A21 S1_A11 a44
<15,19,20,25> PCI_DEVSEL# 32 107 a10
DEVSEL# CDEVSEL#/A21 S1_A20 S1_VS1 a10
<15,19,20,25> PCI_STOP# 33 STOP# CSTOP#/A20 105 a43 a43
34 104 S1_A14 S1_OE# a9
<15,19,20,25> PCI_PERR# PERR# CPERR#/A14 a9
2
G
69 75 S1_CD1# 83
143 RSVD/D2
75
22
42
58
78
94
75
1
2 2 74 74
R281 73
S1_D2 C286 C58 73
4 @10_0402_5% S1_A18 1000P_0402_50V7K 4
S1_D14 1 1 PCMC68PIN
2
1
C294
1000P_0402_50V7K
@15P_0402_50V8J
2
H H
+3VS
U33 LPD[0..7] RP4
LPD[0..7] <26,33>
<16,29,31> LPC_AD0 LPC_AD0 20 68 LPD0 CTS2# 1 8
LPC_AD1 LAD0 PD0/INDEX# LPD1 DSR2#
<16,29,31> LPC_AD1 21 LAD1 PD1/TRK0 69 2 7
<16,29,31> LPC_AD2 LPC_AD2 22 70 LPD2 DCD2# 3 6
G LPC_AD3 LAD2 PD2/WRTPRT# LPD3 RI2# G
<16,29,31> LPC_AD3 23 LAD3 PD3/RDATA# 71 4 5
72 LPD4
LPC_FRAME# PD4/DSKCHG# LPD5 4.7K_8P4R_0804_5%
<16,29,31> LPC_FRAME# 24 LFRAME# PD5 73
25 74 LPD6
<16> LPC_DRQ#1 LDRQ# PD6/MTR0#
75 LPD7 RP3 +5VS
PD7 DCD#1
<7,13,15,19,20,21,25,31> PCIRST# 26 PCIRST# 4 5
1 2 27 79 LPTBUSY DSR1# 3 6
+3VS LPCPD# BUSY/MTR1# LPTBUSY <26,33>
R401 10K_0402_5% 78 LPTPE CTS1# 2 7
LPC_SMI# PE/WDATA# LPTSLCT LPTPE <26,33> RI1#
50 GPIO12/IO_SMI# 77 1 8
+3VS LPC_PME# SLCT/WGATE# LPTERR# LPTSLCT <26,33>
17 IO_PME# ERROR#/HDSEL# 81 LPTERR# <26,33>
SIRQ 30 80 LPTACK# 4.7K_8P4R_0804_5%
<15,21,29,31> SIRQ SIRQ ACK#/DS1# LPTACK# <26,33>
28 66 LPTINIT#
<16,19,21,25,29> PM_CLKRUN# CLKRUN# INIT#/DIR# LPTINIT# <26,33>
CLK_PCI_SIO 29 82 LPTAFD#
<12> CLK_PCI_SIO PCICLK AUTOFD#/DRVDEN0# LPTAFD# <26,33>
83 LPTSTB#
STROBE#/DS0# LPTSTB# <26,33>
CLK_14M_SIO 19 67 LPTSLCTIN#
<12> CLK_14M_SIO CLK14 SLCTIN#/STEP# LPTSLCTIN# <26,33>
RXD1 2 1
F 1 2 LPC_SMI# PID0 48 100 R53 1K_0402_5% F
<13> PID0 GPIO10 DTR2#
R78 10K_0402_5% PID1 54 99 CTS2#
<13> PID1 GPIO15 CTS2#
1 2 LPC_PME# PID2 55 98 RXD2 1 2
<13> PID2 GPIO16 RTS2#
10K_0402_5% PID3 56 97 DSR2# R54 1K_0402_5%
R63 <13> PID3 GPIO17 DSR2#
57 GPIO20 TXD2 96
58 95 RXD2
CLK_14M_SIO CLK_PCI_SIO GPIO21 RXD2 DCD2#
59 GPIO22 DCD2# 94
6 92 RI2#
2 GPIO24 RI2#
2
32 +3VS
GPIO30 DTR1#
R309 R324 33 GPIO31 DTR1# 89 DTR#1 <33>
@10_0402 34 88 CTS1# +5VS
@33_0402 GPIO32 CTS1# CTS#1 <33>
2
35 87 RTS1#
GPIO33 RTS1# RTS#1 <33>
+3VS 36 86 DSR1# R225
GPIO34 DSR1# DSR#1 <33>
TXD1 JP10
21
21
37 GPIO35 TXD1 85 TXD1 <33>
C397 38 84 RXD1 @1K_0402_5% 1
C369 GPIO36 RXD1 RXD1 <33> 1
RP71 @15PF_0402 @22PF_0402 39 91 DCD#1 2
E GPIO37 DCD1# DCD#1 <33> 2 E
RI1# RXD1
1
40 GPIO40 RI1# 90 RI#1 <30,33> 3
PID0 TXD1 3
1
1
1 8 41 GPIO41 4
PID1 IRMODE DSR1# 4
2 7 42 GPIO42 IRMODE/IRRX3 63 IRMODE <26> 5 5
3 6 PID2 43 61 IRRX RTS1# 6
GPIO43 IRRX2 IRRX <26> 6
4 5 PID3 44 62 IRTXOUT CTS1# 7
GPIO44 IRTX2 IRTXOUT <26> 7
45 DTR1# 8
100K_8P4R_0804_5% GPIO45 RDATA# RI1# 8
46 GPIO46 16 9
RDATA# WDATA# DCD#1 9
47 GPIO47 10 10
WDATA# WGATE# 10
11
WGATE# HDSEL# @96212-1011S
1 2 51 GPIO13/IRQIN1 12
R312 10K_0402_5% HDSEL# FDDIR#
52 GPIO14/IRQIN2 8
DIR# STEP#
1 2 64 GPIO23/FDC_PP 9
R307 10K_0402_5% STEP# DRV0#
5
DS0# INDEX#
+3VS
18 VTR INDEX#
13 For SW debug use when no seial port
4 DSKCHG#
DSKCHG# WP#
D 53 VCC 15 D
WRTPRT# TRACK0#
65 VCC 14
TRK0# MTR0#
93 VCC 3
MTR0# 3MODE#
1
DRVDEN0
7 VSS
31 2 +5VS
VSS DRVDEN1 +3VS RP70
60 VSS
76 49 WP# 1 8
VSS GPIO11/SYSOPT TRACK0# 2 7
2
INDEX# 3 6
SMsC LPC47N227 DSKCHG# 4 5
R80
@1K_0402_5% 1K_8P4R_0804_5%
+3VS
1
RP5
C WDATA# 6 5 +5VS C
1
WGATE# 7 4 STEP#
1 1 1 1 1 Base I/O Address R81 HDSEL# 8 3 MTR0#
1K_0402_5% FDDIR# 9 2 RDATA#
C85 C370 C360 C65 C342 * 0 = 02Eh +5VS 10 1 DRV0#
4.7U_0805_10V4Z 0.1U_0402_10V6K 1 = 04Eh
2 2 2 2 2 1K_10P8R_1206_5%
2
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
2 1 3MODE#
+5VS
R297 10K_0402_5%
B B
A
Title
Compal Electronics, Inc. A
LA-XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 22 of 49
10 9 8 7 6 5 4 3 2 1
A B C D E F G H
U23
@0.1U_0402_16V4Z
2 1 SUSP#
+5VS VIN SD SUSP# <29,34,38>
1 1 1 4 R1901 2 @30K_0603_1%
C198 C207 C205 ADJ
<29> BEEP# +3VALW 5 3 C183 2 1
@10U_1206_6.3V6M~D @1U_0603_10V6K GND VOUT
+3VALW 2 2 2 @100P_0402_50V8K +5VAMP
1
+3VALW @LP3965-ADJ
1
+5VAMP 1
1 R82 R193 C179
100K_0402_1%
14
5
1
1 C108 U7 U4D @10K_0402_1% @0.1U_0402_16V4Z 1
1
C113 2
2
0.1U_0402_16V4Z P
P
OE#
2 R84 R88 R181
2
2 4 1 2 9 8 2 1 1 2 +5VS 1 2 +5VAMP
A Y I O 10K_0402_1% R192 0_1206_5%
10K_0402_1% 560_0402_5%
G
G
1 1U_0603_10V6K
SN74AHCT1G125GW_SOT353-5 SN74LVC14APWLE_TSSOP14 C170
C99 1U_0603_10V6K
3
2
0.22U_0603_10V7K 2 1
2 VDDA_CODEC
1
U19
R182 W=40Mil 4 5
+5VS VIN VOUT
10K_0402_1%
R176
1 1 2 6 1 2 1 1
DELAY SENSE or ADJ C168
28.7K_0603_1%
1
R427 C167 C149 C150 C165
2
7 ERROR CNOISE 1
+3VALW MONO_IN 1 2 MONO_INC 1 2 MONO_INR 4.7U_0805_6.3V6K 0.1U_0402_10V6K 1 4.7U_0805_6.3V6K 0.1U_0402_10V6K
2 2 R177 2 2
8 SD GND 3
39.2K_0402_1% 1U_0603_10V6K C156 10K_0603_1%
14
U4E 1 2 SI9182DH-AD_MSOP8
1
C114 C 2
2
P
R89 R174
11 10 2 1 1 2 2 Q24 2 1
<21> PCM_SPK# I O 2.4K_0402_5% +5VS
560_0402_5% B 2SC2411K_SOT23 R411 10K_0402_5% 0.01U_0402_25V7Z
G
1U_0603_10V6K E
SN74LVC14APWLE_TSSOP14
3
+5VAMP_CODEC
7
1 2 VDDA_CODEC
L34 0_0805_5%
+3VALW
+5VAMP_CODEC 1 2 +5VAMP
L35 @0_0805_5%
14
U4F
2 C115 2
1 1 1 1
P
R90 C160
<16> SB_SPKR 13 I O 12 2 1 1 2
560_0402_5% C161 C172 C473
G
1
7
D11
R92 RB751V_SOD323 2
@10K_0402_5% C472 L37
0.1U_0402_16V4Z +3VS_CODEC 1 2 +3VS
FBM-L10-160808-301-T_0603
2
1
1 1 1
C478
C468 C163
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 2
25
38
34
43
9
U22
AVDD1
AVDD2
AVDD4
AVDD3
DVDD1
DVDD2
MONO_INR 14 35
AUX_L LINE_OUT_L LINE_OUTL <24>
R212 2 1 4.7K_0402_5% DLINE_IN_R_L
<33> DLINE_IN_L
R219 1 2 4.7K_0402_5% 15 36
AUX_R LINE_OUT_R LINE_OUTR <24>
R213 2 1 4.7K_0402_5% DLINE_IN_R_R 2 R199 1 0_0402_5%16 37 MDMIC C159 1 2 1U_0603_10V6K
<33> DLINE_IN_R JS1 MONO_OUT MD_MIC <25,28>
R220 1 2 4.7K_0402_5%
<24> HPS 1 2 17 39
C213 R444 4.7K_0402_5% JS0 HP_LOUT_L
1 2 1U_0603_10V6K DLINE_IN_RC_L 23 41
R209 2 LINE_IN_L HP_LOUT_R
<18> CDROM_L 1 4.7K_0402_5% CDROM_R_L
R214 1 2 1.3K_0402_5% C214 1 2 1U_0603_10V6K DLINE_IN_RC_R 24
3 LINE_IN_R R377 2 3
6 1 33_0402_5% AC97_BITCLK <16,25,28>
R211 2 BIT_CLK
<18> CDROM_R 1 4.7K_0402_5% CDROM_R_R C208 1 2 1U_0603_10V6K CDROM_RC_L 18
R216 1 CD_L
2 1.3K_0402_5% 8 R378 2 1 33_0402_5% AC97_SDIN0 <16>
C210 1 SDATA_IN
2 1U_0603_10V6K CDROM_RC_R 20
CD_R
XTL_IN 2 2 1 CLK_14M_CODEC CLK_14M_CODEC <12>
R215 1 2 2.7K_0402_5% CD_GNA C209 1 2 1U_0603_10V6K CDGNDA 19 R184 0_0402_5%
<18> CD_AGND CD_GND R189
2 1
1
R210 2 1 1.1K_0402_5% 1 2 21 @1M_0402_5%
<28> MIC1 C211 1U_0603_10V6K MIC1
<25> MDC_AUDIO_MON
R218 1 2 @10K_0402_5% MDC_AUDIO_MONR 1 2 MDC_AUDIO_MONRC 22 3 Y3 R175
R217 @1K_0402_5% C212 @1U_0603_10V6K MIC2 XTL_OUT @10_0402_5%
1 2 1 1
1 2 13 C188 @24.576MHz 1
<28> MIC2 C487 1U_0603_10V6K PHONE @22P_0402_50V8J C162
2
R388 2 1 0_0402_5% MD_SPKR 1 2 MD_SPKRC 28 @22P_0402_50V8J C164
<25,28> MD_SPK VREFOUT CODEC_REF 2 2
R387 1 2 10K_0402_5% C483 0.1U_0402_16V4Z @15P_0402_50V8J
27 2
VREF
<16,25,28> AC97_RST# 11 RESET# AUD_REF
<16,25,28> AC97_SYNC 1 R381 2 33_0402_5% 10 SYNC AFILT1 29 AFILT1 1 1
30 AFILT2
AFILT2
2 2 2 <16,25,28> AC97_SDOUT 1 R367 2 33_0402_5% 5 31 AFILT3 C189 1 2 270P_0402_50V7K C202 C197
SDATA_OUT AFILT3 AFILT4 1U_0603_10V6K 0.1U_0402_16V4Z
1 2 32
C482 C493 C494 R365 1K_0402_5% AFILT4 C185 1 2 2
L9 0_1206_5% 1 2 45 2 270P_0402_50V7K
0.1U_0603_16V7K @0.1U_0402_16V4Z R363 1K_0402_5% ID0
1 2 46 ID1
1 1 1 L36 C182 1
12 2 270P_0402_50V7K
NC
1 2 <24> EAPD 1 2 47 EAPD 42
FBM-L10-160808-301-T_0603 NC C178 1
L10 0_1206_5% 2 270P_0402_50V7K
<33> SPDIFO 2 1 48 26
C155 R361 SPDIFO AVSS1
40
@0.1U_0402_16V4Z 0_0402_5% AVSS2
2 1 4 44
DVSS1 AVSS3
2
C477 External
2 1
Stuff Stuff 14.318MHZ
@0.1U_0402_16V4Z
C474
Compal Electronics, Inc.
2 1 GNDA Title
AC97 CODEC
@0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
GND GNDA DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 23 of 49
A B C D E F G H
A B C D E
1 1
+5VAMPP +5VAMP
40mils 1 2
1 L15 0_1206_5%
1 1 1
+ C206 C492
C175 C488
@150U_D2_6.3VM 10U_1206_6.3V7K 0.1U_0603_25V7M 0.1U_0603_25V7M
2 2 2 2
R414 0_0402_5%
1 2 LINE_R_OUTR
<23> LINE_OUTR
19
18
7
R428 U24
0_0402_5% C174 0.022U_0603_25V7K
VDD
PVDD2
PVDD1
1 2 LINE_C_OUTR 23
R413 @0_0402_5% C490 0.47U_0603_10V7K RLINEIN SPK_L- SPKL-
9 1 2
R_HP_C LOUT- SPK_L+ SPKL+_C SPKL+
1 L17 0_1206_5%
+
1 2 1 2 20 RHPIN 4 2 1 2 SPKL+ <28>
C215 0.47U_0603_10V7K LOUT+ SPK_R- SPKR-
16 1 L16 0_1206_5%
2 C565 100U_6.3V_M
2 ROUT- SPK_R+ SPKR+_C SPKR+ 2
1 L12 0_1206_5%
+
1 2 8 RIN ROUT+ 21 2 1 2 SPKR+ <28>
R416 @0_0402_5% L11 0_1206_5% C566 100U_6.3V_M
1 2 LINE_R_OUTL C216 0.47U_0603_10V7K
1 1 2 10
LIN SE/BTL#
15 HPS
R429 C489 0.47U_0603_10V7K
L_HP_C +5VAMP
0_0402_5% 1 2 6 17
LHPIN HP/LINE#
1
R419 0_0402_5% C201 0.022U_0603_25V7K
1 2 1 2 LINE_C_OUTL 5 R393 R394
<23> LINE_OUTL LLINEIN
2
3
C176 0.47U_0603_10V7K GAIN1 100K_0402_5% @100K_0402_5%
2
GAIN0
1 2 14 PC-BEEP
2
11 Gain Settings
EAPD# R162 1 BYPASS
2 0_0402_5% 22 1
R163 1 SHUTDOWN#
<28,29> EC_MUTE# 2 @0_0402_5% C217
1
GND1
GND2
GND3
GND4
+5VAMP 0.47U_0603_10V7K R391 R392 GAIN0 GAIN1 SE/BTL# Av(inv)
2
TPA0312PWP_TSSOP24~D @100K_0402_5% 100K_0402_5% 6 dB
0 0 0
12
13
24
1
1
R432
2
0 1 0 10 dB
100K_0402_5%
EAPD# 15.6 dB
2
EAPD# <28> 1 0 0
1
D
2 Q51 21.6 dB
<23> EAPD
G 2N7002 1N_SOT23 1 1 0
S JP19
SPKL+_C 4.1 dB
3
1 X X 1
+5VAMP SPKL- 1
2 2
3 L-SPK CONN 3
JP18
5
SPKR+_C 1 1
2 SPKR- 2 2
P
<33> DOCK_HPS I0
R420 4 HPS 1 1 1 1
O HPS <23>
HP_PLUG 1 2 1 C193 C194 C195 C196 R-SPK CONN.
<28> HP_PLUG I1
G
100K_0402_5% U21
1 TC7SH32FU_SSOP5 47P_0402_50V8J
2
C562 2 2 2 2
3
R159 47P_0402_50V8J
100K_0402_5% 0.1U_0603_16V7K 47P_0402_50V8J
2 47P_0402_50V8J
1
+5VAMP
4 4
Q16
1 1 1 1 1 1 1 1 1 3 1SI2301DS_SOT23
2
C84 C106 C107 4.7U_0805_6.3V6K
1U_0603_10V6K 0.1U_0402_16V7K
2 2 2 2
0.01U_0402_16V7K
<31> Wireless_OFF
PCI_AD[0..31]
PCI_AD[0..31] <15,19,20,21>
JP28
TIP 1 2 RING
1 2
KEY KEY
3 3 4 4
5 5 6 6
7 7 8 8
R65 @0_0402_5% 9 10
D17 9 10 R70 @0_0402_5%
<15,21> PCI_PIRQC# 1 2 11 11 12 12
<28,29,31> Wireless_OFF# 1 2 13 13 14 14 1 2 PCI_PIRQC#
R64 0_0402_5% RB751V_SOD323 15 16
15 16 W=40mils R69 0_0402_5%
<15> PCI_PIRQD# 1 2 17 17 18 18 +5VS
+3VS W=40mils 19 19 20 20 1 2 PCI_PIRQD#
2 PCI_GNT#4 2
<15> PCI_REQ#4 21 21 22 22 PCI_GNT#4 <15>
23 24 W=40mils +3VALW
CLK_PCI_MINI 23 24
<12> CLK_PCI_MINI 25 25 26 26 PCIRST# <7,13,15,19,20,21,22,31>
27 28 W=40mils
27 28 +3VS
PCI_REQ#3 29 30 PCI_GNT#3
<15> PCI_REQ#3 29 30 PCI_GNT#3 <15>
31 31 32 32
PCI_AD31 33 34
PCI_AD29 33 34 MINI_PME# <19,21,29>
35 35 36 36 1 R72 2 CH_CLK <31>
37 38 PCI_AD30 1K_0402_5%
R298 PCI_AD27 37 38
39 39 40 40
1K_0402_5% PCI_AD25 41 42 PCI_AD28
41 42 PCI_AD26
<31> CH_DATA 1 2 43 43 44 44
45 46 PCI_AD24
<15,19,20,21> PCI_CBE#3 45 46
CLK_PCI_MINI PCI_AD23 47 47 48 48 MINI_IDSEL 1 2 R76 PCI_AD18
49 50 100_0402_5%
PCI_AD21 49 50 PCI_AD22
51 51 52 52
1
PCI_AD19 53 54 PCI_AD20
R301 53 54
55 55 56 56 PCI_PAR <15,19,20,21>
PCI_AD17 57 58 PCI_AD18
10_0402_5% PCI_CBE#2 57 58 PCI_AD16
<15,19,20,21> PCI_CBE#2 59 59 60 60
PCI_IRDY# 61 62
<15,19,20,21> PCI_IRDY# 61 62 PCI_FRAME#
2
1 63 63 64 64 PCI_FRAME# <15,19,20,21>
C319 65 66 PCI_TRDY#
<16,19,21,22,29> PM_CLKRUN# 65 66 PCI_TRDY# <15,19,20,21>
PCI_SERR# 67 68 PCI_STOP#
<15,19,21> PCI_SERR# 67 68 PCI_STOP# <15,19,20,21>
10P_0402_50V8K 69 70
2 PCI_PERR# 69 70 PCI_DEVSEL#
<15,19,20,21> PCI_PERR# 71 71 72 72 PCI_DEVSEL# <15,19,20,21>
PCI_CBE#1 73 74
<15,19,20,21> PCI_CBE#1 PCI_AD14 73 74 PCI_AD15
75 75 76 76
77 78 PCI_AD13
PCI_AD12 77 78 PCI_AD11
79 79 80 80
PCI_AD10 81 82
81 82 PCI_AD9
83 83 84 84
3 PCI_AD8 85 86 PCI_CBE#0 3
PCI_AD7 85 86 PCI_CBE#0 <15,19,20,21>
87 87 88 88
89 90 PCI_AD6
PCI_AD5 89 90 PCI_AD4
91 91 92 92
93 94 PCI_AD2
PCI_AD3 93 94 PCI_AD0
95 95 96 96
W=30mils 97 98
+5VS 97 98
PCI_AD1 99 100
99 100
101 101 102 102
AC97_SYNC 103 104
<16,23,28> AC97_SYNC 103 104
AC97_SDIN2 105 106 AC97_SDOUT
<16> AC97_SDIN2 105 106 AC97_SDOUT <16,23,28>
AC97_BITCLK 107 108
<16,23,28> AC97_BITCLK 107 108
2 1 C76 +3VALW 109 110 AC97_RST#
109 110 AC97_RST# <16,23,28>
@15P_0402_50V8J 111 112
MDC_AUDIO_MON 111 112
113 113 114 114
<23> MDC_AUDIO_MON MD_MIC 115 116 MD_SPK
<23,28> MD_MIC 115 116 MD_SPK <23,28>
117 117 118 118
119 119 120 120
<30> MODEM_RI# MODEM_RI# 121 122
W=30mils 121 122 W=40mils
+5VS 123 123 124 124 +3VAUX
127 127 128 128
Mini-PCI SLOT
4 4
D D
1
LPD0 12 5 FD0 FD2 TVS19 1 2 @SF10402ML080C
R5 C9 LPD7 13 4 FD7 220P_1206_8P4C_50V8K
1K_0402_5% 0.1U_0402_16V7K LPD6 14 3 FD6 FD3 TVS2 1 2 @SF10402ML080C
2 LPD5 15 2 FD5 CP1
LPD4 16 1 FD4 LPTACK# 1 8 FD4 TVS17 1 2 @SF10402ML080C
W=20mils LPTBUSY
2
2 7
33_16P8R_1206_5% LPTPE 3 6 FD5 TVS16 1 2 @SF10402ML080C
LPTSTB# 1 2 +5V_PRN_R LPTSLCT 4 5
<22,33> LPTSTB#
R4 33_0402_5% LPTINIT# 1 2 LPT_INIT# FD6 TVS15 1 2 @SF10402ML080C
<22,33> LPTINIT#
JP2 R2 33_0402_5% 220P_1206_8P4C_50V8K
FD7 TVS14 1 2 @SF10402ML080C
1 LPTSLCTIN# 1 2 SLCTIN#
<22,33> LPTSLCTIN#
LPTAFD# 1 2 AFD/3M# 14 R3 33_0402_5% CP3 +5V_PRN_R TVS24 1 2 @SF10402ML080C
<22,33> LPTAFD#
R1 33_0402_5% FD0 2 FD0 1 8
LPTERR# 15 +5V_PRN FD1 2 7 AFD/3M# TVS23 1 2 @SF10402ML080C
<22,33> LPTERR#
FD1 3 FD2 3 6
LPT_INIT# 16 RP2 FD3 4 5 LPTERR# TVS21 1 2 @SF10402ML080C
FD2 4 FD0 1 10
C SLCTIN# FD1 FD7 220P_1206_8P4C_50V8K LPT_INIT# TVS1 1 C
17 2 9 2 @SF10402ML080C
FD3 5 FD2 3 8 FD6
18 FD3 4 7 FD5 CP2 SLCTIN# TVS18 1 2 @SF10402ML080C
FD4 6 5 6 FD4 FD4 1 8
+5V_PRN FD5 LPTACK# TVS13 1
19 2 7 2 @SF10402ML080C
FD5 7 4.7K_10P8R_1206_5% FD6 3 6
20 FD7 4 5 LPTBUSY TVS12 1 2 @SF10402ML080C
FD6 8
21 +5V_PRN 220P_1206_8P4C_50V8K LPTPE TVS11 1 2 @SF10402ML080C
FD7 9 RP1
22 SLCTIN# 1 10 LPTSLCT TVS10 1 2 @SF10402ML080C
LPTACK# 10 LPT_INIT# 2 9 LPTACK#
<22,33> LPTACK#
23 LPTERR# 3 8 LPTBUSY
LPTBUSY 11 AFD/3M# 4 7 LPTPE
<22,33> LPTBUSY
24 5 6 LPTSLCT
LPTPE +5V_PRN
<22,33> LPTPE 12
25 4.7K_10P8R_1206_5%
LPTSLCT 13
<22,33> LPTSLCT
LPTCN-25-SUYIN
FIR Module
B +5VS B
1
FIR@10_1206 FIR@10_1206
2
1 1 1
1
C218 C220
+ C233 C232
FIR@0.1U_0402_10V6K
+ FIR@22UF_10V_1206 FIR@10U_TE-01_6.3VM FIR@0.1U_0402_10V6K
+5VS_FIR
2 2
T = 40mil 2
2
U25
T = 20mil 1
IRED_A IRTXOUT
1 2
IRED_C TXD
3 T = 12mil IRTXOUT <22>
C219 4 5 T = 12mil IRMODE
RXD SD/MODE IRMODE <22>
6 7
FIR@0.1U_0402_10V6K VCC MODE IRRX
2
8 GND T = 12mil IRRX <22>
FIR@IR_VISHAY_TFDU6101E-TR4_8P
A A
Title
Compal Electronics, Inc.
LPT Port & FIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 26 of 49
5 4 3 2 1
5 4 3 2 1
1
2 C251 + +
GND R243 150U_D2_6.3VM C261 C266 C252 C272 C271
1 RT9701-CBL_SOT23_5 470K_0402_5% 0.1U_0402_10V6K 1000P_0402_50V7K 150U_D2_6.3VM 0.1U_0402_10V6K 1000P_0402_50V7K
C278 2 2 2 2 2 2
4.7U_0805_10V4Z OVCUR#0
2
2 OVCUR#0 <16>
L30
1
1 0_0603_5%
R244 2 1 JP7
C254 1
560K_0402_5% 1000P_0402_50V7K L25 USB1D- VCC
<16> USB20P1- 2 1 2 D-
2 USB1D+ 3
D+
4 @DLW21SN900SQ2
2
<16> USB20P1+ 3 4
GND
L28
0_0603_5% 2 1 USB_CONN1
2 1 JP8 L31
1 VCC 0_0603_5%
2 L24 1 USB0D- 2
<16> USB20P0- D-
USB0D+ 3 USB_VCCA
D+
<16> USB20P0+ 3 4 @DLW21SN900SQ2 4 USB1D-
GND USB1D+ 1 1 1
2 1 USB_CONN1
TVS30 TVS29 TVS28
L29
0_0603_5% @SF10402ML080C @SF10402ML080C
USB_VCCA
C USB0D- 2 2 2 C
USB0D+ 1 1 1 @SF10402ML080C
@SF10402ML080C @SF10402ML080C
2 2 2
@SF10402ML080C
USB CONNECTOR 3
+5V U26 USB_VCCC
3 1
W=40mils
VIN VOUT
4 VIN/CE VOUT 5 1
1 1
1
2 C253 +
GND R259 150U_D2_6.3VM C270 C269
1 RT9701-CBL_SOT23_5 470K_0402_5% 0.1U_0402_10V6K 1000P_0402_50V7K
C279 2 2 2
B 4.7U_0805_10V4Z OVCUR#2 B
2
2 OVCUR#4 <16>
1
1
R266 C273
560K_0402_5% 1000P_0402_50V7K
2
2
L26
0_0603_5% JP6
2 1
1 VCC
2 L23 1 USB4D- 2
<16> USB20P4- D-
USB4D+ 3 D+
<16> USB20P4+ 3 4 @DLW21SN900SQ2 4
GND
2 1 USB_CONN1
L27
0_0603_5%
USB_VCCC
USB4D-
USB4D+ 1 1 1
TVS33 TVS32 TVS31
@SF10402ML080C @SF10402ML080C
2 2 2
@SF10402ML080C
A A
Title
Compal Electronics, Inc.
USB Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 27 of 49
5 4 3 2 1
MDC Conn. INT_KBD CONN.
+3VMDC JP16
1
11 12 L33 2 1 @0_0603 USB20P5+ <16,31> JP21
C463 C466 CD_RIGHT RESERVED/USB+ L32
13 14 2 1 @0_0603 USB20P5- <16,31> 1 2
MDC@4.7UF_10V_0805 MDC@0.1U_0402_10V6K CD_LEFT RESERVED/USB- KSO0 1 2 KSO0
15 16 3 4
1 GND RESERVED/PRIMARY_DN KSO2 3 4 KSO2
2
+3VMDC 17 18 BT_WAKE_UP <29> 5 6
+3.3Vaux/BT_VCC RESERVED/+5VD/WAKEUP KSO5 5 6 KSO5
19 20 7 8
GND RESERVED/GND KSIN14 7 8 KSIN14
+3VS 21 22 AC97_SYNC <16,23,25> <30> KSIN14 9 10
+3.3Vmain AC97_SYNC 9 10 KSIN8
<16,23,25> AC97_SDOUT 23 AC97_SDATA_OUT AC97_SDATA_IN1 24 2 1 R352 AC97_SDIN1 <16> <30> KSIN8
KSIN8 11 12
MDC@22_0402 KSIN12 11 12 KSIN12
25 26 <30> KSIN12 13 14
<16,23,25> AC97_RST# AC97_RESET# AC97_SDATA_IN0 13 14 KSIN10
27 GND GND 28 2 1 R350 <30> KSIN10
KSIN10 15 15 16 16
+3VS 29 30 MDC@22_0402 KSI0 17 18 KSI0
AC97_MSTRCLK AC97_BITCLK AC97_BITCLK <16,23,25> 17 18 KSI4
KSI4 19 20
+5VS KSI2 19 20 KSI2
21 21 22
MDC@AMP 3-1473290-0 KSI1 22 KSI1
23 23 24
KSI3 24 KSI3
1 25 26
25 26
1
C158 KSO3 27 28 KSO3
MDC@1000PF_0402 C157 KSO8 27 28 KSO8
1 29 30
29 30
1
2
33 34
MDC@1000PF_0402 MDC@0.1U_0402_10V6K KSO6 33 34 KSO6
35 36
2 KSO10 35 36 KSO10
2
37 38
KSO1 37 38 KSO1
39 39 40 40
KSI5 41 42 KSI5
KSI6 41 42 KSI6
43 43 44
KSI7 44 KSI7
45 46
KSIN13 45 46 KSIN13
<30> KSIN13 47 48
KSIN11 47 48 KSIN11
<30> KSIN11 49 50
KSIN9 49 50 KSIN9
<30> KSIN9 51 52
STS-KB5_5P
2
R329
5
100K_0402_5%
D28
D21
ON/OFFBTN#
2
3 ON/OFFBTN# <29>
@SM05_SOT23 ON/OFF 1
<33> ON/OFF
2 51_ON# <35>
+3VALW DAN202U_SC70 LID_SW# 1 SW2
1
<29> LID_SW# 2
+5VS
1
1
1
R330 D22 1
1
RLZ20A_LL34 3 4
R421 4.7K_0402 Q44 C421 TVS3
2 0.01U_0402_16V7K HORNG CHIH
150_0402_5% 1 R334 22K @SF10402ML080C
2
<29> EC_ON 2 2
0_0402_5% 22K
2
22
17-21/GVC-AMPB/3T_GRN D
2
G
@2N7002 WHEN R=0,Vbe=1.35V
1
S
Q43 WHEN R=33K,Vbe=0.8V
3
Title
Compal Electronics, Inc.
MDC/BT/KBD/ON_OFF/LID
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 28 of 49
A B C D E
I/O Address
0.1U_0402_16V7K EC_AVCC BADDR1-0 Index Data
+3VALW +3VALW RTCVREF
1 1 1 1 +3VS 2 0 0 2E 2F
0 1 4E 4F
C147 C137 C132 C109 1 1 C128 * 1 0 (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
123
136
157
166
161
4.7U_0805_6.3V6K 0.01U_0402_16V7K 1 1 Reserved
16
34
45
95
1U_0603_10V6K
2 2 2 2 C148 C146 U15 1
0.1U_0402_16V7K 4.7U_0805_6.3V6K 0.1U_0402_16V7K
VBAT
VDD
AVCC
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
2 2 ENV0 ENV1 TRIS
L8
+3VALW 1 2 EC_AVCC BATT_TEMP <42>
MURATA BLM11A20PT_0603 2 1 IRE 0 0 0
7 81 1 2 ECAGND
1 C86 <15,21,22,31> SIRQ SERIRQ AD0 0.01U_0402_16V7K 1
C91 1 R443 C116 OBD 0 1 0
0.1U_0402_16V7K
1000P_0402_50V7K <16,31> LPC_DRQ#0
2
@0_0402_5%
8
9
LDRQ# AD1 82
83
*
L7 <16,22,31> LPC_FRAME# LFRAME# AD2 BATT_OVP <36> R86
1 2 1 ECAGND 2 <16,22,31> LPC_AD0 15 84 ADP_IR 1 2 ADP_I <36> DEV 1 0 0
LAD0 Host interface AD3
MURATA BLM11A20PT_0603 <16,22,31> LPC_AD1 14 87 LI/NIMH# <42> 1 10K_0402_5%
LAD1 IOPE0AD4
<16,22,31> LPC_AD2 13 LAD2 IOPE1/AD5 88 PROG 1 1 0
+3VS 10 89 C112
<16,22,31> LPC_AD3 LAD3 IOPE2/AD6 0.22U_0603_10V7K
R148 CLK_PCI_LPC 18 AD Input 90
1 2 EC_RST# <12> CLK_PCI_LPC 19
LCLK IOPE3/AD7
93
2 SHBM=1: Enable shared memory with host BIOS
+3VALW RESET1# DP/AD8
J1 22 94 TRIS=1: While in IRE and OBD, float all the
SMI# DN/AD9
1
GATEA20 5 32
<15> GATEA20 GA20/IOPB5 IOPA0/PWM0 INVT_PWM <13> R75
RC# 6 33 KBA1 (ENV1) 1 2
KBRST/IOPB6 IOPA1/PWM1 BEEP# <23>
36 EN_WOL# <19> 10K_0402_5%
KSI[0..7] PWM IOPA2/PWM2
<28> KSI[0..7] IOPA3/PWM3 37 ACOFF <36>
KSO[0..10] KSI0 KBA2 R74
<15> RC# <28> KSO[0..10] 71
KBSIN0
or PORTA
IOPA4/PWM4 38 PM_BATLOW# <16> (BADDR0) 1 2
KSI1 72 39 @10K_0402_5%
KBSIN1 IOPA5/PWM5 EC_ON <28>
KSI2 73 40
KBSIN2 IOPA6/PWM6 EC_LID_OUT# <16> R73
KSI3 74 43 KBA3 (BADDR1) 1 2
KBSIN3 IOPA7/PWM7 EC_THRM# <16>
KSI4 77 10K_0402_5%
CLK_PCI_LPC KSI5 KBSIN4 DEV_ID0
78 153
KSI6 KBSIN5 IOPB0/URXD DEV_ID1 KBA5
79
KBSIN6 IOPB1/UTXD 154 (SHBM) 1 2
1
KSI7 80 Key matrix scan 162 DEV_ID2 R71 10K_0402_5%
R142 KBSIN7 IOPB2/USCLK EC_SMC_1
IOPB3/SCL1 163 EC_SMC_1 <30,33,42>
KSO0 49 PORTB 164 EC_SMD_1 CONA 1 2
KBSOUT0 IOPB4/SDA1 EC_SMD_1 <30,33,42>
10_0402_5% KSO1 50 165 R97 20K_0402_5%
KBSOUT1 IOPB7/RING/PFAIL/RESET2 B_PCIRST# <15,18>
KSO2 51
KSO3 KBSOUT2
2
1
KSO10 61 1
KBSOUT10 IOPC7/CLKOUT R62
64 KBSOUT11
65 26 ACIN <16,33,35,37> 100K_0402_5%
KBSOUT12 IOPD0/RI1/EXWINT20
66 29 SLP_S4# <16>
KBSOUT13 PORTD-1 IOPD1/RI2/EXWINT21
67 30 SLP_S3# <16,33>
KBSOUT14 IOPD2/EXWINT24/RESET2
2
68
KBSOUT15
2 ON/OFFBTN# <28> <19,21,25> PCM_PME#
EC_TINIT# IOPE4/SWIN
105 TINT# IOPE5/EXWINT40 44 SLP_S5# <16>
RP6 EC_TCK 106 PORTE 24
TCK IOPE6/LPCPD/EXWIN45 RING# <30> <19,21,25> MINI_PME#
10 1 KBD_DATA EC_TDO 107 25
+5V TDO IOPE7/CLKRUN/EXWINT46 PM_CLKRUN# <16,19,21,22,25>
9 2 KBD_CLK EC_TDI 108 JTAG debug port
TP_DATA EC_TMS TDI KBA0 <19,21,25> ONBD_LAN_PME#
8 3 109 124
PS2_DATA TP_CLK TMS IOPH0/A0/ENV0 KBA1
7 4 IOPH1/A1/ENV1 125 <19,21,25> USB20_PME#
PS2_CLK 6 5 KBD_CLK 110 126 KBA2
+5V <33> KBD_CLK PSCLK1/IOPF0 IOPH2/A2/BADDR0
KBD_DATA 111 127 KBA3 PCI_PME#
<33> KBD_DATA PSDAT1/IOPF1 IOPH3/A3/BADDR1
10K_10P8R_1206_5% PS2_CLK 114 128 KBA4
<33> PS2_CLK PSCLK2/IOPF2 IOPH4/A4/TRIS
SD307100207 PS2_DATA 115 PORTH 131 KBA5
<33> PS2_DATA PSDAT2/IOPF3 IOPH5/A5/SHBM
TP_CLK 116 PS2 interface 132 KBA6
<28> TP_CLK PSCLK3/IOPF4 IOPH6/A6
TP_DATA 117 133 KBA7
+3VALW <28> TP_DATA PSDAT3/IOPF5 IOPH7/A7
RP10 LID_SW# 118
<28> LID_SW# PSCLK4/IOPF6
FSEL# 1 8 BT_WAKE_UP 119 138 ADB0
<28> BT_WAKE_UP PSDAT4/IOPF7 IOPI0/D0 +3VALW
SELIO# 2 7 139 ADB1 RP12
FREAD# IOPI1/D1 ADB2 DEV_ID2
3 6 140 1 8
EC_SMI# IOPI2/D2 ADB3 DEV_ID1
4 5 141 2 7
CRY1 PORTI IOPI3/D3 ADB4 DEV_ID0
158 32KX1/32KCLKIN 144 3 6
10K_8P4R_0804_5% IOPI4/D4 ADB5
IOPI5/D5 145 4 5
3 12 R94 CRY2 160 146 ADB6 3
SD309100200 32KX2 IOPI6/D6
X1 20M_0603_5% 147 ADB7 10K_8P4R_0804_5%
IOPI7/D7
2 1 2 1 R93
1 1 120K_0402_5% 150 FREAD#
IOPJ0/RD FREAD# <30>
32.768KHz_12.5P_CM155 PORTJ-1 151 FWR#
IOPJ1/WR0 FWR# <30>
C118 C119
10P_0402_50V8K 10P_0402_50V8K SELIO#
2 2 SELIO# 152 SELIO# <30> EC DEBUG port
+5VALW EC_SMI# 62 41
<16> EC_SMI# IOPJ2/BST0 IOPD4 JP14
RP15 MSEN# 63 42
<13,14,33> MSEN# IOPJ3/BST1 IOPD5 NUMLED# <30>
EC_SMD_2 1 8 CONA 69 PORTD-2 54 1
<33> CONA IOPJ4/BST2 IOPD6 CAPSLED# <30> 1 +5VALW
EC_SMC_2 2 7 70 PORTJ-2 55 2 EC_TINIT#
EC_SMD_1 <16> EC_RIOUT# IOPJ5/PFS IOPD7 2 EC_TCK
3 6 75 3
EC_SMC_1 <21> PCM_SUSP# IOPJ6/PLI KBA8 3 EC_TDO
4 5 <12,16> SLP_S1# 76 IOPJ7/BRKL_RSTO IOPK0/A8 143 4 4
142 KBA9 5 EC_TDI
10K_8P4R_0804_5% IOPK1/A9 KBA10 5 EC_TMS
148 135 6
<34,38> SYSON IOPM0/D8 PORTK IOPK2/A10 KBA11 6
<23,34,38> SUSP# 149 IOPM1/D9 IOPK3/A11 134 7 7
155 130 KBA12 8 DEV_ID0
<34,39,41> VR_ON IOPM2/D10 IOPK4/A12 8
156 PORTM 129 KBA13 9 DEV_ID1
<25,28,31> Wireless_OFF# IOPM3/D11 IOPK5/A13_BE0 KBA14 9 DEV_ID2
3 121 10
<16,21> PM_RSMRST# IOPM4/D12 IOPK6/A14_BE1 KBA15 10
4 120
+3VALW <13> ENABLT# IOPM5/D13 IOPK7/A15_CBRD
27
<4> PROCHOT# IOPM6/D14 KBA16 @96212-1011S
28 113
LID_SW# <13> BKOFF# IOPM7/D15 IOPL0/A16 KBA17
1 2 IOPL1/A17 112
R67 20K_0402_5% FSEL# 173 PORTL 104 KBA18
<30> FSEL# SEL0# IOPL2/A18
1 2 MSEN# 174 103 KBA19
R99 20K_0402_5% SEL1# IOPL3/A19
47 48 FSTCHG <36>
CLK IOPL4/WR1#
1
AGND
GND1
GND2
GND3
GND4
GND5
GND6
GND7
NC10
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
R96
4 10K_0402_5% 4
122
159
167
137
17
35
46
96
11
12
20
21
85
86
91
92
97
98
PC87591L-VPCN01 A2_LQFP176
2
2
ECAGND C572
@1U_0603_10V6K
1
Title
Compal Electronics, Inc.
EC PC87591L
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-1701
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 29 of 49
A B C D E
INPUT <29> KBA[0..19]
<29> ADB[0..7]
KBA[0..19]
ADB[0..7]
+3VALW OUTPUT
+3VALW
8
7
6
5
8
7
6
5
C120
RP13 RP14 1 2 +5VALW
C135
100K_8P4R_0804_5% 100K_8P4R_0804_5% 0.1U_0402_16V7K 1 2
20
SD309100300 SD309100300
U11 0.1U_0402_16V7K
1
2
3
4
1
2
3
4
ADB0
20
2 18
VCC
1A1 1Y1 ADB1 U17
4 1A2 1Y2 16
6 14 ADB2 ADB0 3 2
VCC
<28> TP_ON/OFF# 1A3 1Y3 +3VALW D0 Q0 FULL_LED# <28>
8 12 ADB3 ADB1 4 5
<28> EC_MUTE_IN# 1A4 1Y4 D1 Q1 POWER1_LED# <28,33>
11 9 ADB4 ADB2 7 6
<28> BT/WL_ON/OFF# 2A1 2Y1 D2 Q2
13 7 ADB5 C133 ADB3 8 9
<28> VOL_UP# 2A2 2Y2 D3 Q3 CHARGING_LED# <28>
15 5 ADB6 2 1 ADB4 13 12
<28> VOL_DW# 2A3 2Y3 D4 Q4 BT_ON# <28>
17 3 ADB7 ADB5 14 15
<28> BT_PRES# 2A4 2Y4 D5 Q5 BT_DETACH <28>
0.1U_0402_16V7K ADB6
14
17 16 TPAD_LED# <28>
U16A ADB7 D6 Q6
1 18 19
GND
1G KBA2 D7 Q7
19 1
P
2G A
14
3 11
GND
U16B SN74LVC244APWLE_TSSOP20 SELIO# O LARST# CP
2 B 1
MR
10
G
KBA1 4
P
A SN74LVC32APWLE_TSSOP14 SN74HCT273PW_TSSOP20
6
O
10
SELIO#
7
<29> SELIO# 5
B
G
C143
SN74LVC32APWLE_TSSOP14
+5VALW
7
1 2 1 2
R125
20K_0402_5%
1U_0603_10V6K
+3VALW
+3VALW
8
7
6
5
8
7
6
5
C93
RP8 RP7 1 2
SD309100300 SD309100300
U6
1
2
3
4
1
2
3
4
2 18 ADB0
VCC
1
4 16 ADB1 +3VALW +3VALW
<28> KSIN9 1A2 1Y2
6 14 ADB2 R37
<28> KSIN10 1A3 1Y3
8 12 ADB3 10K_0402_5%
<28> KSIN11 1A4 1Y4
1
11 9 ADB4
<28> KSIN12 2A1 2Y1
13 7 ADB5 1 2 C152 R152
<28> KSIN13 2A2 2Y2 0.1U_0402_16V7K D8
ADB6 10K_0402_5%
2
<28> KSIN14 15 5
2A3 2Y3 ADB7
17 2A4 2Y4 3 <21> PCM_RI# 1 2
U20
RB751V_SOD323
2
1 8 1
GND
1G VCC A0
19 7 2 <29> RING#
2G WP A1
14
KBA3 9 1 2
P
A <25> MODEM_RI#
1
8
SELIO# O R143 AT24C16N10SI-2.7_SO8 R144 RB751V_SOD323
10
B
G
1K_0402_5% 1K_0402_5%
1
SN74LVC32APWLE_TSSOP14 D
RI#1
7
2 RI#1 <22,33>
2
G
+3VALW S Q11
U29 @2N7002 1N_SOT23
3
KBA0 21 31 +3VALW
KBA1 A0 VCC0
20 30 1
KBA2 A1 VCC1
19
KBA3 A2 C124
18 A3
1
KBA4 17 25 ADB0 0.1U_0402_16V4Z
KBA5 A4 D0 ADB1 2
16 A5 D1 26 R116
KBA6 15 27 ADB2 20K_0402_5% SUS_STAT# <13,16> +5VS +5VS
A6 D2
2
KBA7 14 28 ADB3
G
14
KBA8 A7 D3 ADB4
8 32
A8 D4
1
KBA9 7 33 ADB5
2
12 1 3
P
A10 D6 O S
KBA11 6 35 ADB7 13 Q19
A11 D7 B
G
22
22
A14 RP# +3VALW U16D FWR# <29>
KBA15 2 11 R422 SN74LVC32APWLE_TSSOP14
KBA16 A15 NC @100K_0402_5%
1 12 GREEN D6 GREEN D7
KBA17 A16 READY/BUSY#
40 A17 NC0 29
KBA18 13 38 17-21/GVC-AMPB/3T_GRN 17-21/GVC-AMPB/3T_GRN
KBA19 A18 NC1
37
A19
FSEL# 22
1
<29> FSEL# CE#
FREAD# 24 23
<29> FREAD# OE# GND0
3
FWE# 9 39 Q31 Q33
WE# GND1
PDTA114EK_SOT23 E PDTA114EK_SOT23 E
@SST39VF080-70_TSOP40 10K 10K
B B
<29> CAPSLED# 2 <29> NUMLED# 2
10K 10K
JP31 C C
+3VALW KBA16 KBA17
KBA15 1 2
3 4 1 1
U35 KBA14
1
KBA13 5 6 KBA19
7 8 TVS5 TVS4
KBA18 9 8 KBA12 KBA10 @SF10402ML080C_0402 @SF10402ML080C_0402
KBA16 A18 VCC FWE# KBA11 9 10 ADB7
10 7
KBA15 A16 WE* KBA17 KBA9 11 12 ADB6
11 6
KBA12 A15 A17 KBA14 KBA8 13 14 ADB5 2 2
12 5
KBA7 A12 A14 KBA13 FWE# 15 16 ADB4
13 4
KBA6 A7 A13 KBA8 RESET# 17 18
14 A6 A8 3 19 20 +3VALW
KBA5 15 2 KBA9
KBA4 A5 A9 KBA11 21 22
16 A4 A11 1 23 24
KBA3 17 32 FREAD# KBA18 ADB3
KBA2 A3 OE* KBA10 KBA7 25 26 ADB2
18 A2 A10 31 27 28
KBA1 19 30 FSEL# KBA6 ADB1
KBA0 A1 CE* ADB7 KBA5 29 30 ADB0
20 29
ADB0 A0 DQ7 ADB6 KBA4 31 32 FREAD#
21 28
ADB1 22
DQ0
DQ1
DQ6
DQ5
27 ADB5 KBA3 33
35
34
36
Compal Electronics, Inc.
ADB2 23 26 ADB4 KBA2 FSEL# Title
DQ2 DQ4 ADB3 KBA1 37 38 KBA0
24 VSS DQ3 25 39 40 BIOS & EC I/O Port
@SUYIN-80065A-040G2T THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
39F040_TSOP AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 30 of 49
5 4 3 2 1
+3VS
D R405 SD@1K_0402_5% D
WR_PT 1 2 SDLED
SDPWCTL#
1 1
C556 C557
36
35
34
33
32
31
30
29
28
27
26
25
U42
SD@0.1U_0402_10V6K SD@10U_1206_6.3V6M
MSCLK
VSS
MSLED
SDPWCTL#
SDLED
MSPWCTL#
SCC4
SCC8
MS1
MS2
MS3
MS4
2 2
JP17
WR_PT MMC_DET#
R406 SD1 1 2 SD2
SD_CLK SD3 3 4 SD4
1 2 37 24
SD@FBM-11-100505-600T_0402 SD1 SDCLK MS5 CLK_SD_48M SD5 5 6 SD_CLK
38 23 CLK_SD_48M <12>
SD2 SD1 XIN SDPWCTL# 7 8
39 22
SD2 XOUT 9 10
40 21
+3VS SD3 VDD3V SCRST# SDLED 11 12
41 SD3 SCIO 20 13 14
SD4 42 19 R407
SD4 SCCLK +5VS 15 16 +3VS
SD5
LPC_AD3
43
44
SD5 W83L518D (LPC) SCPSNT 18
17
1 2
1 SD@SD_16PIN 1
LAD3 SCPWCTL# SD@8.2K_0402_5%
LPC_AD2 45 16 C298 C300
LPC_AD[0..3] LPC_AD1 LAD2 SCLED
<16,22,29> LPC_AD[0..3] 46 15 +5VS
LPC_AD0 LAD1 VDD SD@0.1U_0402_10V6K SD@0.1U_0402_10V6K
47 LAD0 SCBLED 14
48 13 MMC_DET# 2 2
<15,21,22,29> SIRQ SERIRQ SCBPWCTL# 1 1
C558 C559
SD@0.1U_0402_10V6K SD@10U_1206_6.3V6M
2 2
C C
LPC_DRQ#
SCBPSNT
LFRAME#
SCBRST#
SCBCLK
PCICLK
lESET#
SCBC4
SCBC8
SCBIO
PME#
VSS
SD@W83L518D (LPC)
10
11
12
1
2
3
4
5
6
7
8
9
CLK_PCI_SD CLK_PCI_SD CLK_SD_48M
<12> CLK_PCI_SD
1 R147 2
<16,29> LPC_DRQ#0
2
2
0_0402_5%
R408 <16,22,29> LPC_FRAME# R409
<7,13,15,19,20,21,22,25> PCIRST#
10_0402_5% @10_0402
1
1
1
1 C561
C560
@10PF_0402
10P_0402_50V8K 2
2
B R424 B
1 2
@0_0805_5%
+3VALW Q53 +3VAUX_BT
SI2301DS_SOT23
3 1
1 1 1 1
C568 C570 C571 C569
2
JP32 4.7U_0805_6.3V6K
1 +3VAUX_BT 1U_0603_10V6K 0.1U_0402_16V7K
1 2 2 2 2
2
2 R425 1
3 2 0_0603_5% USB20P5+ <16,28>
3 R426 1
4 4 2 0_0603_5% USB20P5- <16,28>
0.01U_0402_16V7K
5
5 R442
6 6 CH_DATA <25>
7 CH_CLK <25> <25> Wireless_OFF 1 2 +5VALW
7
8 8
100K_0402_5%
1
BT_CONN D
2 Q54
<25,28,29> Wireless_OFF#
G 2N7002 1N_SOT23
S
A
3 A
+3VALW
+3VALW
1
R59
@10K_0402_5%
14
14
U4A U4B
2
R61 D18
P
<12,16,41> VGATE 1 2 1 2 3 4 1 2
I O I O
G
100K_0402_5% RB751V_SOD323
SN74LVC14APWLE_TSSOP14 1 SN74LVC14APWLE_TSSOP14
7
C79 +3VS
1U_0603_10V6K
2
1
+3VS +3VALW R317
10K_0402_5%
2
1
PM_POK <16>
R68
47K_0402_5%
14
U4C
2
1
D
P
5 6 2 Q39
I O 2N7002 1N_SOT23
G
G
1 S
1
SN74LVC14APWLE_TSSOP14
3
R60 C78
330K_0402_5% 0.47U_0603_10V7K 7
2
2
Title
Compal Electronics, Inc.
RESET CKT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-1701
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 32 of 49
A B C D E
1
VIN 2 1 DOCKVIN DOCKVIN P2 P2 G2 G2
R441
1 A1 B1 ON/OFF
1 +12V A1 B1 SLP_S3# ON/OFF <28>
C41 C38 R28 2 1SPR@1K_0402_5%A2 B2 SPR@1K_0402_5%
+5V A2 B2 SLP_S3# <16,29>
+3V A3 A3 B3 B3 +3V
SPR@1000P_0402_50V7K SPR@1000P_0402_50V7K R27 2 SPR@0_0402_5% POWER1_LED POWER1_LED
2
1 A4 A4 B4 B4
2 2 ACIN KBD_DATA
<16,29,35,37> ACIN A5 A5 B5 B5 KBD_DATA <29>
1
KBD_CLK D Q52
A6 B6 KBD_CLK <29>
CTS#1 A6 B6 PS2_DATA
<22> CTS#1 A7 B7 PS2_DATA <29> 2 POWER1_LED# <28,30>
RTS#1 A7 B7 PS2_CLK G
<22> RTS#1 A8 B8 PS2_CLK <29>
DSR#1 A8 B8 EC_SMD_1 SPR@2N7002 1N_SOT23
<22> DSR#1 A9 A9 B9 B9 EC_SMD_1 <29,30,42> S
RI#1 EC_SMC_1
3
<22,30> RI#1 A10 B10 EC_SMC_1 <29,30,42>
DCD#1 A10 B10
<22> DCD#1 A11 B11
RXD1 A11 B11 COMPS
<22> RXD1 A12 B12 COMPS <13,14>
TXD1 A12 B12 CRMA
<22> TXD1 A13 B13 CRMA <13,14>
DTR#1 A13 B13 LUMA
<22> DTR#1 A14 B14 LUMA <13,14>
A14 B14
A15 A15 B15 B15
LPTSLCTIN# A16 B16 D_VSYNC_R 1 2 D_VSYNC
<22,26> LPTSLCTIN# A16 B16 D_HSYNC_R R435 1 D_VSYNC <14>
<22,26> LPTINIT#
LPTINIT# A17 A17 B17 B17 2 SPR@0_0402_5% D_HSYNC D_HSYNC <14>
LPTERR# A18 B18 D_DDCCLK R436 SPR@0_0402_5%
<22,26> LPTERR# A18 B18 D_DDCDATA D_DDCCLK <14>
LPTAFD# A19 B19
<22,26> LPTAFD# A19 B19 MSEN D_DDCDATA <14>
LPTSLCT A20 B20
<22,26> LPTSLCT A20 B20 MSEN# <13,14,29>
LPTPE A21 B21
<22,26> LPTPE A21 B21 BLUE_S 1
LPTBUSY A22 B22 2
<22,26> LPTBUSY A22 B22 BLUE <13,14>
1
LPTACK# GREEN_S 1 R48 D
<22,26> LPTACK# A23 B23 2 SPR@0_0402_5% GREEN <13,14>
LPTSTB# A23 B23 RED_S
<22,26> LPTSTB# A24 B24 1 R47 2 SPR@0_0402_5% RED <13,14> 2 Q14
LPD7 A24 B24 R46 SPR@0_0402_5% SPR@2N7002 1N_SOT23
<22,26> LPD7 A25 B25 G
LPD6 A25 B25
<22,26> LPD6 A26 B26 S
2 LPD5 A26 B26 2
3
<22,26> LPD5 A27 A27 B27 B27
LPD4 A28 B28
<22,26> LPD4 A28 B28
LPD3 A29 B29
<22,26> LPD3 A29 B29
LPD2 A30 B30
<22,26> LPD2 A30 B30
LPD1 A31 B31
<22,26> LPD1 A31 B31
LPD0 A32 B32
<22,26> LPD0 A32 B32
A33 A33 B33 B33
A34 A34 B34 B34
A35 A35 B35 B35
A36 B36 SLP_S3#
USB20P2- USB20P2-_R A36 B36
<16> USB20P2- 1 2 A37 A37 B37 B37
R437 SPR@0_0402_5% A38 B38 ON/OFF
USB20P2+ USB20P2+_R A38 B38
<16> USB20P2+ 1 2 A39 A39 B39 B39
R438 SPR@0_0402_5% A40 B40
A40 B40
3
USB20P3- 1 2 USB20P3-_R A41 B41
<16> USB20P3- A41 B41
R439 SPR@0_0402_5% A42 B42
USB20P3+ USB20P3+_R A42 B42 D29
<16> USB20P3+ 1 2 A43 A43 B43 B43
R440 SPR@0_0402_5% A44 B44
A44 B44
A45 A45 B45 B45
A46 B46 SM05_SOT23
A46 B46
A47 A47 B47 B47
DOCK_HPS# A48 B48
A48 B48
1
A49 A49 B49 B49
SPDIFO A50 B50
<23> SPDIFO A50 B50
A51 A51 B51 B51
A52 A52 B52 B52
A53 A53 B53 B53
<23> DLINE_IN_L DLINE_IN_L A54 B54
DLINE_IN_R A54 B54
<23> DLINE_IN_R A55 A55 B55 B55
A56 A56 B56 B56
DLINE_OUT_L A57 B57
<28> DLINE_OUT_L A57 B57
DLINE_OUT_R A58 B58
3 <28> DLINE_OUT_R A58 B58 3
A59 A59 B59 B59
A60 A60 B60 B60
R277 1 2 SPR@0_0402_5% XTPB1-_R A61 B61
<20> XTPB1- A61 B61
A62 A62 B62 B62
R278 1 2 SPR@0_0402_5% XTPB1+_R A63 B63
<20> XTPB1+ A63 B63
A64 A64 B64 B64
R279 1 2 SPR@0_0402_5% XTPA1-_R A65 B65
<20> XTPA1- A65 B65
A66 B66 L4
R280 1 SPR@0_0402_5% XTPA1+_R A66 B66
<20> XTPA1+ 2 A67 A67 B67 B67 1 2
A68 B68 R45 SPR@1K_0402_5% SPR@0_0603_5%
LAN_LED0# A68 B68
<19> LAN_LED0# A69 A69 B69 B69 1 2 +5V
+5VS +5VS CONA C32
<29> CONA A70 A70 B70 B70 LAN_LED1# <19>
A71 A71 B71 B71 2 1
1 2 1 2 A72 A72 B72 B72 2 1 2 1
1
DOCK_HPS <24>
GND
GND
GND
GND
GND
GND
1
D
DOCK_HPS# 2 Q10
G 2N7002 1N_SOT23 SPR@SPR-154PIN
1
2
3
4
5
6
S
3
4 4
U10 U36
+12VALW 8 1 +12VALW 8 1
D S D S 1
1
7 D S 2 7 D S 2 1
1 6 3 1 6 3 R382 C476
D S D S
1
C134 5 4 1 1 5 4 1 1 C480 100K_0402_5% 1U_0805_16V7K
R24 D G C130 R395 C440 D G 0.1U_0402_16V7K 2
3
1 SI4800DY_SO8 C125 100K_0402_5% SI4800DY_SO8 C407 C412 2 S 1
100K_0402_5% 2 10U_1206_6.3V6M 0.1U_0402_10V6K 2 10U_1206_6.3V6M 10U_1206_6.3V6M
G
Q47
12
2
2 2 10U_1206_6.3V6M 2 2 NDS352P 1P_SOT23
R380
2
2
D
5VON RUNON 51K_0402_5%
1
0.1U_0402_16V7K
1 1
1
1
D D
2
+12V
SYSON# 2 Q9 C123 SUSP 2 Q50 C506
1
G 2N7002 1N_SOT23 0.01U_0402_16V7K G 2N7002 1N_SOT23 0.01U_0402_16V7K D
2 2 1
S S 5VON 2 Q49
2N7002 1N_SOT23 C470
3
3
G
S 1U_0805_16V7K
2
3
+5VALW to +5V Transfer +5VALW to +5VS Transfer
+5VALW +5V +5VALW +5VS +12VALW TO +12VS Transfer
U32 U41
8 1 8 1 +12VALW +12VALW
D S D S
7 D S 2 7 D S 2
1 6 D S 3 1 6 D S 3
5 4 1 1 5 4 1 1
C332 D G C307 C496 D G C547 1
1
SI4800DY_SO8 C303 10U_1206_6.3V6M SI4800DY_SO8 C548 10U_1206_6.3V6M 1
2 0.1U_0402_16V7K 2 10U_1206_6.3V6M 0.1U_0402_16V7K R379 C475
2 2 2 2 C479 100K_0402_5% 1U_0805_16V7K
2 10U_1206_6.3V6M 5VON RUNON 2 2
3
2 S
G
Q46
12
2
0.1U_0402_16V7K NDS352P 1P_SOT23
R386
+1.5VALW to +1.5VS Transfer
D
51K_0402_5%
1
+2.5V to +2.5VS Transfer +1.5VALW +1.5VS
2
+2.5V +2.5VS +12VS
U30 0.1U_0402_16V4Z
1
D
8 1 1
U39 D S RUNON Q48
7 2 2
D S
1
8 1 6 3 1 1 G 2N7002 1N_SOT23 C469
D S D S R284 1U_0805_16V7K
7 D S 2 5 4 S
D G C308 C309 @475_0402_1% 2
3
1 6 3
D S SI4800DY_SO8
5 4 1 1 1 1 1
C484 D G C292 C290 2 2
SI4800DY_SO8 C491 C485 C291
2
2 10U_1206_6.3V6M 10U_1206_10V4Z 10U_1206_10V4Z
1
2 2 2 2 2 22U_1206_10V4Z D
10U_1206_6.3V6M RUNON 2 SUSP
10U_1206_10V4Z RUNON G
0.1U_0402_16V7K S Q35
@2N7002_SOT23 +5VALW
1
R87
100K_0402_5%
Discharge circuit
2
3 +5VALW +CPU_CORE 3
SYSON#
<40> SYSON#
1
+VCCP +2.5V +3V +5V +12V
1
R113 R313 D
100K_0402_5% 470_0402_5% SYSON 2 Q17
<29,38> SYSON
1
G 2N7002 1N_SOT23
R311 R351 R318 R295 R187 S
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0805_5%
12
3
D
VR_ON# 2 Q40
<39> VR_ON#
2N7002 1N_SOT23
12
12
12
12
12
1
D D D D D D
S
VR_ON# Q41 SYSON# Q45 SYSON# Q42 SYSON# Q38 SYSON# Q25 Q18
3
2 2 2 2 2 <29,39,41> VR_ON 2
G 2N7002 1N_SOT23 G 2N7002 1N_SOT23 G 2N7002 1N_SOT23 G 2N7002 1N_SOT23 G G 2N7002 1N_SOT23
S S S S S 2N7002 1N_SOT23 S +5VALW
3
1
R183
100K_0402_5%
2
1
SUSP
<40> SUSP
1
1
R238 R38
470_0402_5% 470_0402_5% R195 R31 R194 R286 R283
1
470_0402_5% 470_0402_5% 470_0402_5% 470_0805_5% 470_0402_5% D
2 Q26
<23,29,38> SUSP# 2N7002 1N_SOT23
12
12
G
D D
12
12
12
12
12
S
4 SUSP 2 Q30 SUSP 2 Q13 D D D D D 4
3
G 2N7002 1N_SOT23 G SUSP 2 Q28 SUSP 2 Q12 SUSP 2 Q27 SUSP 2 Q37 SUSP 2 Q34
S S 2N7002 1N_SOT23 G 2N7002 1N_SOT23 G 2N7002 1N_SOT23 G 2N7002 1N_SOT23 G 2N7002 1N_SOT23 G 2N7002 1N_SOT23
3
S S S S S
3
VIN
Detector
PL15
PCN2 PD22 FBM-L18-453215-900LMA90T_1812
3
3 1
1 ADPIN
EC10QS04
1 2
VIN detector
1
100P_0603_50V8J
14.229 13.717 13.217
1
PR165
12.520 12.110 11.566
1000P_0603_50V7K
4 2 @10_1206_5%
1
PC135
100P_0603_50V8J
1
1
PC138
4 2 PC136
PC137
1000P_0603_50V7K PR166
2
1
SINGATRON_2DC_S736I201 1M_0603_1% 1
1
2
2
1 2
ADPGND
PZD1 VIN VS VIN
0.01U_0603_50V7K
@RLZ24B
8.2K_0805_5%
1
1
453K_0603_1%
PR169
PC139
PR168
10K_0603_5%
PR167
1 2 ACIN <16,29,33,37>
PR170
2
8
PR171 22K_0603_1%
2
200_1206_5% 1 2 3 3.2V
P
VS + PACIN
1 2 O 1 PACIN <36>
68P_0603_50V8J
2 -
G
365K_0603_1%
PD23 PU13A
1
PC140
0.1U_0603_16V7K
PR174
RLS4148
PR172
PC141
200_1206_5% LM393M_SO8 PZD2 PR173
4
2 1 1 2 RLZ4.3B 10K_0603_5%
VIN
2
2
2
2 1 VL
PR175
10K_0603_5%
5V
PD34
RLS4148
2
VMB 2 1 2
1 PR223
2
1.5K_1206_5%
+5VP
0.22U_1206_25V7K
0.1U_0603_16V7K
2 1 1 PR178
2
VIN B+
1
150K_0603_5%
RLZ4.3B 1.5K_1206_5%
1
1
PR179
PC142
1
PR180
PC144
PC143 PZD4
0.1U_0805_25V7K RLZ5.1B
PR181
2
1 2
1.5K_1206_5%
2
2
1
2
<28> 51_ON# 1 2
1
PR182 PR185
22K_0603_5% PR183 PR184 806K_0603_1%
10K_0603_5% 2M_0603_5%
1 2 2 1
VL
2
5V PU13B
LM393M_SO8
8
PD27
CHGRTCP 3 5
P
<4,37,42> MAINPWON +
1
3.3V PR186 2
1 7
O
6
3
PU14 <36> ACON -
3
1
RTCVREF 200_0805_5%
1
S-812C33AUA
0.1U_0603_16V7K
RB715F_SOT323 PR187
1
1000P_0603_50V7K
2M_0603_5%
4
1
PR290
PC146
PR189 PC145
2
PC147
RTCVREF 1 1.5M_0603_1% 1000P_0603_50V7K
2
2 3 3 2 2
1
2
1
511_0603_1% PZD5
2
1
RLZ16B
2
PC149
4.7U_1206_25VFZ ACIN
1
2
2
PC148
1U_0805_25V4Z
Precharge detector 2 1 PQ37 PR192
VL
2N7002_SOT23 47K_0603_5%
12.432 11.717 11.061
1
PR188 D
10.188 9.702 9.051 5V 10K_0603_5% 2 2 1 PACIN
2
G
S
3
PR259
1
@66.5K_0603_1%
BAT ONLY
1
PJP3 PJP4
3MM 3MM Precharge detector 100K
2 +5VALWP
+1.2VSP PQ38
+3VALWP
1 2
+3VALW
1 2 +1.2VS 9.507 9.030 8.589 DTC115EUA
7.263 7.015 6.579 100K
PJP5 PJP6
3
3MM 3MM
1 2 +1.5VALWP 1 2
4
+5VALWP +5VALW +1.5VALW 4
PJP7
PJP8 PJP15
2MM
1 2 3MM 2MM
+12VALWP +12VALW +1.25VSP +1.8VSP
1 2 +1.25VS 1 2 +1.8VS
Compal Electronics, Inc.
PJP9 Title
3MM PJP14
Detector
1 2 2MM
+2.5V THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
+2.5VP +1.05VSP 1 2 +VCCP AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B LA-1701 0.4C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 35 of 49
A B C D E
A B C D E
Charger
1 PD39 1
1 2
Iadp=0~3.0A
B++ B540C
P2 P3 B+
PL7 PQ18
2200P_0603_50V7K
PD40 PQ17 PR75 FBM-L18-453215-900LMA90T_1812 SI4835DY_SO8
4.7U_1210_25V6K
4.7U_1210_25V6K
0.1U_0805_25V7K
B540C SI4835DY_SO8 0.02_2512_1%
VIN 2 1 1 8 2 1 1 2 1 8
2 7 2 7
2
0.01U_0603_50V7K
3 6 1 1 3 6
PC222
PC62
PC63
PC64
PC65
47U_25V_M
47U_25V_M
5 5
1
PC224
PC225
+ +
PR76
1
200K_0402_5%
4
4
2 2
1 2
VIN
3
2
1
PR77
2
PQ19 47K_0603_5%
2
SI4835DY_SO8
PR79 4 PR80
0_0603_5% 10K_0603_5%
PU5
1 24
-INC2 +INC2 ACOFF#
1
<29> ADP_I
1
2 1 2 23
PR81 OUTC2 GND PC66
5
6
7
8
1
31.6K_0603_1%
ACOFF# 1 2 ACOFF <29>
1
0.01U_0402_16V7K
4 -INE2 VCC(o) 21 1 2
1
10K_0603_1%
PR84
PR82
3
2 11 2 5 20
FB2 OUT
1
<35> PACIN 1 2 2
2N7002_SOT23 4700P_0603_50V7K LXCHRG
2
G 6 19 1 2
VREF VH CC=0(0.5A) ~ 2.7A
0.1U_0603_16V7K
S
1
PC73
3
ACON 1 2 1 2 7 18 1 2 0.1U_0805_25V7K
<35> ACON PR86 FB1 VCC PL8 PR88
PC72 1K_0603_5% 15U_SPC-1204P-150_4A_20% 0.02_2512_1% BATT+
2
2200P_0603_50V7K 8 17 1 2 1 2 1 2 BATT+
-INE1 RT PR87
66.5K_0603_1%
4.7U_1210_25V6K
4.7U_1210_25V6K
4.7U_1210_25V6K
1 2 9 16
PR89 +INE1 -INE3
1
<29> IREF
PC74
PC76
PC77
127K_0603_1% PR90 PR91 PC75
1
66.5K_0603_1%
2 1 10 OUTC1 FB3 15 1 2 1 2
1
2
0.01U_0402_16V7K 11 14 ACON
OUTD CTL
2
2
IREF=0.580~3.132V
1
2
1 2
12 13 PR93
-INC1 +INC1 PC79 @10K_0603_5%
MB3887_SSOP24 @10P_0603_50V8F
2
3 3
2 1 4.2V 2 1
OVP voltage : LI-MH 8 CELL(4S2P) BATT+ PR94 PR95
47.5K_0603_0.1% 143K_0603_0.1%
BATT+ : 18.0V--> BATT_OVP : 2.0V
(BATT_OVP voltage = 0.1109*BATT+) 1 2
<29> AIR_ACIN
1
PC80 +3VALWP
PR209 @22P_0603_50V8J
604K_0603_1% CS
1
VS
PR96
1
CS 47K_0603_5%
2
0.1U_0603_50V4Z
1
PU16B
2
1
100K
PC158
PR213 LM358A_SO8 2
1M_0603_0.5% PR277 PQ23
DTC115EKA_SOT23
1
PR285 10K_0603_5% DTC115EUA
2
PQ50
10K_0603_5% 5 2 1 100K
100K + 2.5VREF
2
2 2 1 7
0
8
<29> FSTCHG
3
- 6 2 1 VIN 100K
1
3 2
P
+
0.01U_0603_50V7K
2
-
1
1
2.2K_0603_5%
@0.1U_0603_16V7K
PR286 100K
3
1
1
PR216
PC162
10K_0603_5%
PC161
PU16A
4
3
LM358A_SO8 PR279
2
10K_0603_0.5%
2
PR217
Compal Electronics, Inc.
2
200K_0603_0.5%
2
Title
Charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-1701 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 36 of 49
A B C D E
A B C D E
+3.3V/+5V/+12V
B++
1 1
2
PR54
PL5 @10K_1206_5%
2 1
FBM-L18-453215-900LMA90T_1812
PC33
4.7U_1210_25V6K
1
1 2
1
2
PD10 PD9
PC35 DAP202U_SOT323 PC34 EC11FS2_SOD106
0.1U_0805_25V7K 470P_0805_100V7K
BST31 BST51
1
B+++ 1 2
3
SNB 1 FLYBACK
2
2
2
2200P_0603_50V7K
PR55
0.1U_0805_25V7K
4.7U_1210_25V6K
4.7U_1210_25V6K
PR56 22_1206_5%
0.1U_0603_16V7K
PQ14 0_0603_5% VL
1 8 DH31 1 2 +12VALWP PC40
D1 G1
1
VS 0.1U_0805_25V7K
1
2 7
D1 S1/D2
PC36
PC37
PC38
PC39
3 6 1 2
G2 S1/D2
4.7U_1206_10V7K
3
4 5
S2 S1/D2
10_1206_5%
PC42
B+++ PT1
2
1
SI4814DY_SO8 9U_SDT-1204P-9R0-120_4.5A_20%
2
PR58
PR57
2200P_0603_50V7K
0_0603_5%
PC41
PQ15
2.7K_1206_5%
0.1U_0805_25V7K
4.7U_1210_25V6K
4.7U_1210_25V6K
1 D1 G1 8
1
LX3
1
2 7
D1 S1/D2
1
PR287
2
2
3 6
G2 S1/D2
PC43
PC44
PC45
PC46
DL3 4 5
S2 S1/D2
0.1U_0805_25V7K
2 PR59 2
+3.3V Ipeak = 6.66A ~ 10A
4.7U_1210_25V6K
0_0603_5% SI4814DY_SO8
2
1
DH3
PC47
2
1
PC48
PQ51
1
1
PC50 2N7002_SOT23 D
1
PL6 47P_0402_50V8J ACIN
2
2
10U_SPC-1204P-100_4.5A_20%
2
G
S 1 PR60
2 DH51
0_0603_5%
1
2
22
21
PC51
25 4 47P_0402_50V8J
V+
VL
BST3 12OUT
2
2
VDD 5
1M_0402_1%
27 18 BST5 CSH5
DH3 BST5
1
PR61
16 DH5
PR62 PU4 DH5 LX5
26 17
LX3 MAX1632_SSOP28 LX5
1
+3VALWP 0.012_2512_1% 24 19 DL5
DL3 DL5
1
1
PGND 20
14 PR63 PR64
CSH3 CSH5 2M_0402_5% 0.012_2512_1%
2
1 13
CSH3 CSL5
2 12
CSL3 FB5
2
3 15
FB3 SEQ
3.57K_0603_1%
150U_D2_6.3VM
150U_D2_6.3VM
2
1 1 <16,29,33,35> ACIN 1 2 10 9 2.5VREF
SKIP# REF
1
23 6
SHDN# SYNC
1
+ +
PC52
PC53
PR66
PR65 11
RST#
1
PC54 10K_0402_5% 7
100P_0402_50V8K TIME/ON5 PC55
2 2 +5VALWP
PR67 4.7U_1206_10V7K
2
28
GND
@300K_0402_5% RUN/ON3
2
10.2K_0402_1%
@150U_D2_6.3VM
2
1
1
1
PD11
150U_D2_6.3VM
1
1
3 + 3
PC57
EP10QY03 PC56
8
VL 1 2 1 2
+5VP 680P_0402_50V7K +
PR70
PC59
PC58
PR68 PR69 100P_0402_50V8K PD12
2
2
1
2
2
10K_0402_1%
PR71
47K_0402_1%
PR72
1
1
PR73
MAINPWON <4,35,42>
1
10K_0402_1%
PC60
@0.047U_0603_16V4Z
PR74
+5V Ipeak = 6.66A ~ 10A
2
2
47K_0603_5%
1 2 VL
1
PC61
1U_0805_25V4Z
2
4 4
Title
3.3V / 5V / 12V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY O F THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-1701 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIORWRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 37 of 49
A B C D E
5 4 3 2 1
+2.5VP/+1.8VSP
D D
PL17
HCB4532K-800T90_1812
4.7U_1210_25V6K
0.1U_0805_25V7K
4.7U_1210_25V6K
2200P_0603_50V7K
1 2 B++
1
PC170
PC171
PC172
PC173
2
PR230 +5VALWP
51_1206_5%
2200P_0603_50V7K
1
0.1U_0805_25V7K
4.7U_1210_25V6K
4.7U_1210_25V6K
PD37 PC175 PR255 PC174
1
DAP202U_SOT323 0.1U_0805_25V7K 2.2_0603_5% 2.2U_0805_10V6K
1
PR162
PC176
PC177
PC178
PC179
1K_0603_5%
1
2 1 SUSP# <23,29,34>
C C
2
PC181
PC180 4.7U_0805_6.3V6K
14
28
0.01U_0603_50V7K
2 1 12 SOFT1 17 2 1
VIN
VCC
SOFT2 +1.8VSP
PC184 PL18 PC182 PC183 PL19
+2.5VP 150U_D2_6.3VM 4.7U_SPC-1204P4R7_5.7A_20% 0.1U_0805_25V7K 0.1U_0805_25V7K 5UH_SPC_06704-5R0A
2 1 2 1 1 2 6 BOOT1 23 1 2 2 1 2 1
BOOT2 PR232
1 PR231 0_0603_5%
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
+
@150U_D2_6.3VM
1 D1 G1 8 1 PR233 2 5 UGATE1 UGATE2 24 1 PR234 2 8 G1 D1 1 1 1
1
100U_6.3V
1 2 7 0_0603_5% PU18 0_0603_5% 7 2
D1 S1/D2 S1/D2 D1
1
100U_6.3V
PC186
PC187
PC227
PC189
3 6 4 25 6 3 PC190 + +
2 G2 S1/D2 PHASE1 PHASE2 S1/D2 G2
PC226
+ PC191 4 5 5 4 0.01U_0603_50V7K
0.01U_0603_50V7K S2 S1/D2 PR235 PR236 S1/D2 S2
2
2
1
2
1 2 7 ISEN1 ISEN2 22 1 2
1
1
1
2 27 PR237
LGATE1 LGATE2
1
2
2
2
3 PGND1 PGND2 26
2
9 VOUT1 20
VOUT2
10 VSEN1 19
EN1 VSEN2
8 EN1 EN2 21 2 1 EN1
B 15 16 B
PG1 PG2/REF
1
PR248
GND
DDR
1
11 18 0_0603_5% PR242
OCSET1 OCSET2
1
13
1
10K_0603_1% @0_0603_5% 1SUSP#
1
2
2
PC193 PR245 PR288
2
@1000P_0603_50V7K 84.5K_0603_1% PR246 @0_0603_5%
2
147K_0603_0.1%
2
2
<29,34> SYSON 2 1
PR247
0_0603_5%
+3VALWP
1
PR249
@10K_0603_5%
A A
+1.2VSP/+1.5VALWP/1.05VSP
CPUB++ PL1
HCB4532K-800T90_1812 CPUB+
1 2
2200P_0603_50V7K
0.1U_0805_25V7K
4.7U_1210_25V6K
4.7U_1210_25V6K
1
2
PC2
PC3
PC4
PC1
PR1 +5VALWP
51_1206_5%
2
D D
2200P_0603_50V7K
PR2
1
2.2_0603_5%
0.1U_0805_25V7K
4.7U_1210_25V6K
4.7U_1210_25V6K
PC6 PC5
1
PD1 0.1U_0805_25V7K 2.2U_0805_10V6K
DAP202U_SOT323
1
PR256
PC7
PC8
PC9
PC10
2
2 1 VR_ON <29,34,41>
1K_0603_5%
2
PC12
PC11 4.7U_0805_6.3V6K
14
28
0.01U_0603_50V7K
2 1 12 17 2 1
VIN
VCC
PL2 SOFT1 SOFT2 +1.2VSP
+1.5VALWP PC13 PC14 PL3
4.7U_SPC-1204P4R7_5.7A_20% 0.1U_0805_25V7K 0.1U_0805_25V7K 5UH_SPC_06704-5R0A
2 1 2 1 1 2 6 BOOT1 23 1 PR4 2 2 1 2 1
PR3 BOOT2 0_0603_5%
0_0603_5%
4.7U_0805_6.3V6K
@150U_D2_6.3VM
PQ1 PQ2
150U_D2_6.3VM
150U_D2_6.3VM
4.7U_0805_6.3V6K
1 1 1 D1 G1 8 1 PR5 2 5 24 1 PR6 2 8 1 1 1
UGATE1 UGATE2 G1 D1
1
100U_6.3V
2 7 0_0603_5% PU1 0_0603_5% 7 2 PC21
D1 S1/D2 S1/D2 D1
PC228
+ + + +
PC16
PC15
PC17
PC18
PC19
3 6 4 25 6 3 0.01U_0603_50V7K
PC22 G2 S1/D2 PHASE1 PHASE2 S1/D2 G2
4 S2 S1/D2 5 5 S1/D2 S2 4
0.01U_0603_50V7K
2
2
1 PR7
2 7 22 1 PR8 2
ISEN1 ISEN2
1
C 1.74K_0603_1% 1.5K_0603_1% PR9 C
1
1
2 LGATE1 27 0_0603_5%
LGATE2
1
PR12
PR11 0_0603_5% PR10
6.81K_0603_1% 3.48K_0603_1%
2
2
2
3 26
PGND1 PGND2
2
9 VOUT1 VOUT2 20
10 VSEN1 19
EN2 VSEN2
8 21 2 1 EN2
EN1 EN2
1
15 16 PR20
PG1 PG2/REF
1
PC24 0_0402_5%
GND
DDR
1
@1000P_0603_50V7K 11 18 PR14
OCSET1 OCSET2
1
13
1
1
PR15 @0_0603_5% 1VR_ON
2
2
10K_0603_1% PR17
2
84.5K_0603_1% PR18 PR289
2
147K_0603_0.1% @0_0402_5%
2
+3VALWP
2
2 1
PR19
0_0603_5%
+1.5VALWP
1
PR224 PQ40
B 0_0603_5% B
SI3442DV
D
6 +3VALWP
S
2
5 4 +1.05VSP
2
1 1
1
1
220U_D2_2M_R9
G
1
5.1K_0603_5%
PC166
PR226 + PR21
1
0_0603_5% @10K_0603_5%
3
PR225
PC164
4.7U_1206_25VFZ +5VALWP 2
0.1U_0603_16V7K
2
2
2
2
1
PC169
PC165
560P_0603_50V7K
1
PR229
2
8
137K_0603_1%
3 2 1 2.5VREF
P
+
1 0
2
-
G
100K_0603_1%
0.01U_0603_50V7K
PU17A PQ41
4
LM358A_SO8
1
1
PR228
DTC115EUA
PC168
100K
2
+ 5 1 2 2 1 2 VR_ON# <34>
7
A 0 PC167 PR227 A
6
- 68P_0603_50V8J 5.1K_0603_5% 100K
PU17B
3
LM358A_SO8
D
+3VALWP D
+3VALWP
2
PR264
PR260 5.1_0603_5%
0_0402_5% 2 1
1U_0603_10V6K
1
1
1
D
PC217
PC218
4.7U_1210_25V6K
0.1U_0603_16V7K
SUSP 2
2
G
2
S
PC220
PQ53
3
2N7002_SOT23
1
PL20
PU22
5UH_SPC_06704-5R0A
+1.25VSP
1 VIN PVIN 8
2 7 2 1
GND LX
3 6
SD PGND
+2.5VP 2 1 4
VREF VFB
5
0.1U_0603_16V7K
PR265 1
PR261 CM3718 100K_0603_5%
2
FB_VDD+
1U_0603_10V6K
100K_0603_0.5% 1 2 + PC221
2
D
100K_0402_5%
PC219
220U_D_6.3M_R55
2
SUSP 2
2
PC215
PR263
PR262
1
G
100K_0603_0.5% S 1 2 1 2
C PQ54 PR266 C
3
2N7002_SOT23 1K_0603_5% PC216
1
1
470P_0603_50V8J
REMOTE SENSE
VS
+2.5VP
PC205
0.1U_0603_50V4Z
1
PR257 PC206
2
10K_0603_0.5% 0.1U_0402_16V4Z
B B
2
8
PR254
(1.25V) 0_0603_5%
2
3
+SDREF P +
1 2 1
0
- 2
1
1
PC204 PU20A PR258
10U_1206_10V4Z LM358A_SO8 10K_0603_0.5% PC203
4
0.1U_0402_16V4Z
2
2
2
1
SDREF_L D PR291 1 2 @0_0402_5% SUSP <34>
PQ45 2
G PR292 1 2 0_0402_5% SYSON# <34>
2N7002_SOT23 S
3
+ 5
7
0
- 6
PU20B
LM358A_SO8
A A
+5VDRIVE
CPU-CORE
CPUB+ PL9
PR103 PD15 FBM-L18-453215-900LMA90T_1812 B+
0_1206_5% EP10QY03
+5VS 2 1 2 1 1 2
1U_0805_25V4Z
2200P_0603_50V7K
1
1
4.7U_1210_25V6K
4.7U_1210_25V6K
4.7U_1210_25V6K
0.1U_0805_25V7K
PC207
PC90
PC86
PC87
PC88
PC89
PC85 PR104
1
4.7U_0805_10V4Z 2.2_0603_5%
5
2
2
5
6
7
8
5
6
7
8
1 10
VCC
IN BST
@IRF7821_S08
PQ27
+3VS PR105
IRF7821_S08
1
D
D
D
D
D
D
D
D
1
PQ26
0_0603_5%
1 PC91 3205_SD# 2 9 1 2 1
100P_0603_50V8J SD DRVH
G
S
S
S
S
S
S
PU8
2
3 8 1 2
DRVLSD SW
2
2
PR293
PR295 PR106 2.2_0603_5%
4
3
2
1
4
3
2
1
GND
33K_0603_5% 15K_0603_1% 2 PR107
1 1 40 4 6 +CPU_CORE
<5> PSI# 0_0603_5% PSI TSYNC DLY DRVL
RB751V_SOD323
1 PR108
2 2 39 PL10 PR111
HYSSET DRV3
1
0_0603_5%
23.7K_0603_1% 0.6U_HK_AE26A0R6_26A_25% 0.002_2512_5%
1
7
PR110
PD42
<5> CPU_VID5 2 PR109 1 3 VID5 DRVLSD3 38 PU7 1 2 2 1 +CPU_CORE
2
220U_D2_2M_R9
0_0603_5% ADP3415
0.01U_0603_50V7K
PR112 2 PR113 1 4 37 1
<5> CPU_VID4 VID4 DRV2
EC31QS04
5.36K_0603_1% 0_0603_5% PR114
1
PC209
2 PR115 1 13.7_0603_1% +
2
<5> CPU_VID3 5 36
VID3 DRVLSD2
5
6
7
8
5
6
7
8
@IRF7832_SO8
PC92
0_0603_5% PD16
300K_0603_5% 1SS355_SOD323
2 PR116 1
IRF7832_SO8
1
1
6 35 1 2
D
D
D
D
D
D
D
D
<5> CPU_VID2 VID2 DRV1 2
0_0603_5% EC31QS04
2
2
PQ28
PQ29
2 PR117 1 PC93
2
<5> CPU_VID1 7 34
VID1 DRVLSD1
PD18
PD17
0_0603_5% PR119 0_0402_5% 0.01U_0603_50V7K
2
G
S
S
S
S
S
S
300K_0603_5%
4
3
2
1
4
3
2
1
9 VREF 32 2 1
CS2
12
PR121
PR120
3.9K_0603_1% 10 31
BOOTSET CS1 PR123 56 _0402_1%
1
PR122
11 30 PC94 2 1
DPRSET CS+
2
330K_0402_5%
10P_0402_50V8K
1
PR126
PR124 2 PR125 1
1
<16> PM_DPRSLPVR 12 29
6.34K_0603_1% 0_0603_5% DPRSLP CS-
2 PR127 1
2
<12,16> STP_CPU# 13 28
DPSLP RAMP
1
0_0603_5%
PC95
1
2
14 27
2 PWRGD REG 2
470P_0402_50V7K 10P_0402_50V8K
0.01U_0603_50V7K PD41 PR129 604K _0402_1%
1
2
1
PC96
200_0402_1%
17 DPWRGD DACREFFB 24
2
<12,16,32> VGATE
VR_ON 2 PR132 13205_SD# 1 PR133 +5VDRIVE
2
<29,34,39> VR_ON 18 SD COREFB 23 2
0_0603_5% CPUB+
4.7U_0805_10V4Z
19 22 2.7_0402_5% PD19
SS VCC
1
PR134 EP10QY03 PC105
PC97
20 21 3.32K_0402_1% 2 1 1U_0805_25V4Z
CLAMP GND
1
2200P_0603_50V7K
0.1U_0805_25V7K
4.7U_1210_25V6K
4.7U_1210_25V6K
4.7U_1210_25V6K
0.1U_0402_16V4Z
MCH_PWRGD 2 PR135 1
1
PC100
@IRF7821_S08
PC99
PR283 0_0603_5% PC98
5
6
7
8
5
6
7
8
PC101
PC102
PC103
PC208
PC104
3.3K_0402_5% 0.047U_0603_25V7M PR136
IRF7821_S08
2
1
VCCP_PWGD 2 PR137 2.2_0603_5%
2
2
1
D
D
D
D
D
D
D
D
5
PQ30
PQ31
ADP3205
2
2
1 10
VCC
IN BST
5.36K_0402_1%
0_0603_5%
2
2
G
S
S
S
S
S
S
PR139
PR140
+3VS PR138 2 9 10_0603_5%2
3K_0603_5% SD DRVH
4
3
2
1
4
3
2
1
3 8 1 2
DRVLSD SW PR294 PL11 PR141
1
3205_VCC 2.2_0603_5% 0.6U_HK_AE26A0R6_26A_25% 0.002_2512_5%
1
GND
PC106 4 6 2 1 2 1
DLY DRVL
2
0.1U_0402_16V4Z
1
+3VS PU9
1
RB751V_SOD323
ADP3415 PR142
7
PR143 10_0603_1%
5
6
7
8
5
6
7
8
0_0603_5%
@IRF7832_SO8
+3VS PD20
PD43
EC31QS04
IRF7832_SO8
1
1 2
D
D
D
D
D
D
D
D
1
3 3
2
1
PQ32
PQ33
PR144 PC107
2
47K_0603_5% PR145 0.01U_0603_50V7K
PU10
G
S
S
S
S
S
S
2.7_0603_5%
XC61CN0902MR
2
4
3
2
1
4
3
2
1
3205_VCC
2
1 2 MCH_PWRGD
+1.8VSP VDDIN PWDOUT
VSS
PC108
1
4.7U_1206_16V4Z PC109
PC110 0.1U_0805_25V7K
1000P_0603_50V7K
3
2
2
+3VS
PR222
0_0603_5%
1
1 2
PR146
PU11 47K_0603_5%
XC61CN0902MR
2
1 2 VCCP_PWGD
+1.05VSP VDDIN PWDOUT
VSS
4 4
1
PC111
1000P_0603_50V7K
3
2
1
4 VS
5 1 2
1 EC_SMC PC150 PC151 1
6 EC_SMD 1000P_0603_50V7K 0.01U_0603_50V7K
7
2
3
8
1
1K_0603_5%
PC153
1
PR197
SUYIN_25133A-08G1-01_8P 1 PD28 PC152 0.1U_0603_50V4Z
@BAS40-04 @0.1U_0402_10V6K
2
2
CPU VL
2
2
PTH1
10K_1% PR199
L_10
47K_0402_1%
2
1 2
1
PR200
LI/NIMH# <29>
1
PR201 47K_0402_1%
PR195 PR196 0_0402_5%
100_0603_5% 100_0603_5% 1 2 PR203 PD29
+3VALWP
8
PR202 16.9K_0402_1% PU15A 1SS355_SOD323
1
25.5K_0603_1%
2
1 2 3
P
+
OTP_C
2
1 2 1
O
1
1 2 REV 2
L_10T
-
G
PR204 VL
1K_0603_5% PR198 LM393M_SO8
100K_0402_1%
4
3 PR205
1
PC156 2.74K_0603_1%
2
1
PD30 0.22U_0805_16V7K
2
1
@BAS40-04 PR207
<4,35,37>
MAINPWON
100K_0402_1%
2
2
PC154
2
2 2
1000P_0603_50V7K
2
BATT_TEMP <29>
EC_SMD_1
EC_SMD_1 <29,30,33>
EC_SMC_1
EC_SMC_1 <29,30,33>
1
PD31 PD32
@BAS40-04 @BAS40-04
PH2 near main Battery CONN :
1
BAT. thermal protection at 84 +-3 degree C
Recovery at 45 +-3 degree C
3
100K
2
VL
100K
PQ39
+5VALWP
3
DTC115EKA_SOT23
1
3 PC157 3
@0.1U_0402_10V6K VL
BATTERY
2
PTH2
10K_1%
PR208
L_11
47K_0402_1%
1 2
2
PR210 PR211
0_0402_5% 47K_0402_1%
PR212
8
16.9K_0402_1%
1
1 2 5
L_11T
P
+
O 7 OTP_B2 1
REV 6
1
G
- PD33
PR214 1SS355_SOD323
3.32K_0603_1% PU15B
4
LM393M_SO8
1
PC160
2
0.22U_0805_16V7K
2
4 4
Title
BATTERY CONN / OTP/1.8V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALSize Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-1701 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Wednesday, July 09, 2003 Sheet 42 of 49
A B C D
5 4 3 2 1
REV: 0.1A
1. Update PCI resource table. (Page 3)
2. Change U41 power source form +12VS to +5VS for correcting error. (Page 4)
3. Remove DVI signals. (Page 13)
D
4. Add Video board ID and Mother board ID for HP requirement. (Page 16) D
5. Change LAN controller from RTL8100BL to RTL8139CL+ for HP requirement. (Page 19)
6. Change audio CODEC from ALC202A to AD1981B and modify relational components for HP requirement. (Page 23,24)
7. Change USB power protector from Poly switch to RT9701-CBL for meet HP's specification. (Page 27)
8. Add CP9, CP10 (100P_1206_8P4C) for EMI requirement. (Page 28)
9. Add a power button LED (D34) for HP requirement. (Page28)
9. Add a power button LED (D34) for HP requirement. (Page28)
REV: 0.1B
1. U33,U34,U56 combine to U33 (74HCT08 TSSOP14).(Page 18)
2. Add Q81,C892,C891 for +3VAUX turn on/off.(Page 25)
C
3. Add R91,R1132,C893 for correcting error. (Page 26) C
14. Connecting the pin97 of JP28 and JP29 to GND for HP's requirement. (Page9,10)
15. Install a 0 ohm (R703) between ITP_DBRESET# and SYSRST# then de-populate U51,R704 and C833. (Page 16)
16. Modify USB routing method for HP's requirement. (Page 16)
i. USB0 and USB 1 (U45.C20/D20, U45.A21/B21) to the two ganged system USB ports.
ii. USB2 and USB3 (U45.C18/D18, U45.A19/B19) to the docking connector.
iii. USB4 (U45.C16/D16) to single USB.
iv. USB5 (U45.A17/B17) to MDC.
17. Delete net MBAY_DISABLE from JP1 pin A49 for HP's requirement. (Page 29,33)
18. Change powerm source of D10,D11 and D12 from CRTVDD to +3VS for HP's requirement. (Page 14)
19. Add an IO buffer (U56) for supporting EVO600's keyboard. (Page 30)
A
REV: 0.1C A
REV: 0.1D
1. Change U20 to AT24C16N and change power source to +3VALW. (Page 30)
2. Change U49 EC_SMC_1/EC_SMD_1 to EC_SMC_2/EC_SMD_2. (Page 4)
3. Change Battery EC_SMC_2/EC_SMD_2 to EC_SMC_1/EC_SMD_2. (Page 42)
D
4. Modify SD controller to M/B. (Page 31) D
REV: 0.2D
1. To change the mute circuitry for SI build.
a. Connect EAPD (pin U22.47) to JP24.2 and reserve a 0_0402_5% (R431) resistor for testing.
b. Install R162 (0_0402_5%) and no install R163.
c. Add R432 (100K_0402_5%) and Q51 (2N7002) to invert EAPD signal for amplifier and mute LED.
D REV: 0.2E D
B
REV: 0.3 (For SI SMT) B
REV: 0.3B
1. Exchange signals NUMLED# and CAPSLED# of Q31 and Q33 for solving BC022.
2. Rotate JP20 180 degree for solving PCP assembly issue.
3. Change JP18 & JP19's pin1 signal from SPKR+ and SKPL+ to SPKR+_C and SPKL+_C for solving audio noise issue.
REV: 0.4 (For PV gerber)
D
1. Connection LPC_DRQ#0 to U42.2 through R147 0_0402_5% for support SD controller DMA function. D
3. Reserve R447,R448,R449 layout pad for support CB1410 B0 version chip in the further.
4. Add D29 SM05 for solving ESD test fail issue.
5. For solving "BoBo" audio noise from HLDS and TEAC ODD.
a. Change R214,R216 from 4.7K_0402_5% to 1.3K_0402_5%.
b. Change R210 from 2.7K_0402_5% to 1.1K_0402_5%.
REV: 1.0 (MP)
REV: 2.0
1. Install R72 and R298 1K_0402_5% (page 25). This is for better performance when both BT and Wireless cards co-exist in the system.
2. Connection SLP_S3# to D29 (ESD diode) on docking side..
C C
B B
A A
2 change reference voltage, because VL build up fast then PR188 change to 34K, add PR259 (66.5K) 2002.10.15
RTCVREF 35
4 the current rating of the new BEAD is 9A, the old one
is 8A. 37 PL5 change to FBM-L18-453215-900-LMA90T 2002.10.15
add PD38,PD39,PD40,PQ46,PQ47,PQ48,PQ49,PQ50,PQ51,
36 PQ52,PU21,PR267,PR268,PR269,PR270,PR271,PR272, 2002.10.23
5 modify circuit for aircraft power PR273,PR274,PR275,PR276,PR277,PR278,PR279,PR280,
PR281,PC210,PC211,PC212,PC213,PC214,PZD8
delete PD35,PD36,PQ44,PR250,PR251,PR252,PR253,
C PC194,PC195,PC196,PC197,PC198,PC199, C
PC200,PC201,PU19
6 modify circuit for DDR, change CM8500 to CM3718 40 2002.10.23
add PR260,PR261,PR262,PR263,PR264,PR265,PR266
PC215,PC216,PC217,PC218,PC219,PC220,PC221,
PU22
change VIN detector voltage and Precharge deterctor PR167 change to 60.4K, PR166 change to 604K,
7 voltage 35 PR184 change to 604K, PR185 change to 301K, 2002.10.23
PR187 change to 402K
modify circuit for aircraft power, when use aircraft power, delete PU21,PQ47,PQ48,PQ49,PQ51,PD40,PZD8,PQ16,
8 battery can discharge 36 PR267~PR276,PR280~PR281,PC210~PC214,PC223,PD38,PD39 2002.12.04
add PD40,PD41,PQ50,PZD6,PR285,PR286
delete PQ26~PQ29,PU7,PD15,PD16,PC85~PC90,PC93,
12 modify circuit form dual phase to single phase at CPU-CORE 41 PL10,PR104,PR105,PR110,PR111 2002.12.04
add PC223
change PR129 to 604K_0402_5%,
PR134 to 3.32K_0402_1%,
PR126 to 120K_0402_5%,
PR141 to 0.001_2512_5%,
PC107 to 0.01U_0603_25V
14 change CPU thermal protect to 90 degree C 42 change PR205 form 3.32K_0603_1% to 2.74K_0603_1% 2002.12.18
A 15 to reduce tolerance on CPU CORE voltage feedback 41 change PR126 form 120K_0402_5% to 120K_0402_1% 2002.12.18 A
add PQ26,PQ29,PU7,PD15,PD16,PC85~PC90,PC93,PC97
PL10,PR104,PR105,PR110,PR111,PR114,PC230,PC231
2003,01,23
25 to solve noise issue (A2C021) 41 delete PC223
change PR129 to 604K_0402_5%,
PR134 to 3.32K_0402_1%,
PR126 to 330K_0402_5%,
PR123 to56_0402_1%,
PC96 to 10P_0402_50V
add PD42,PD43
26 to reduce negative voltage at High-side GATE 41 change PR105 and PR140 to 2.2_0603_5% 2003,01,23
for ADP3415 (A2C014,A2C098)
B B
27 to limit RTC battery discharge current for meeting OSM 4.3.8 35 change PR290 from 200_0805_5% to 511_0603_1% 2003,05,02
specification.
28 adjust ripple voltage and ripple current when charger battery 36 delete PC79 and PC80 2003,05,02
change PR91 from 330K_0603_5% to 47K_0603_5%
29 to solve noise issue (OTS:97258) 37 change PC33 from 2.2U_1206 to 4.7U_1210 2003,05,02
A A