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HP CQ40 Compal La-4101p PDF
HP CQ40 Compal La-4101p PDF
1 1
www.kythuatvitinh.com
Compal confidential 2
Schematics Document
Mobile Penryn uFCPGA with Intel
3
Cantiga_GM+ICH9-M core logic 3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 1 of 46
A B C D E
A B C D E
P6, 7, 8
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Intel Cantiga MCH
Dual Channel
CRT FCBGA 1329
P18
2
HDMI P35 2
USB2.0 X12
DMI X4 C-Link BT Conn
P30
USB Camera
P19
PCI-E BUS*5 Azalia
4
SPDIF 4
CIR
K/B backlight Conn MIC*1 Capsense switch Conn
P33
P33 LINE-OUT*1
Security Classification Compal Secret Data Compal Electronics, Inc.
2006/02/13 2006/03/10 Title
DC/DC Interface CKT. Issued Date Deciphered Date
Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P36 P34 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 2 of 46
A B C D E
A
Symbol Note :
Voltage Rails O MEANS ON X MEANS OFF USB assignment:
: means Digital Ground USB-0 Right side
USB-1 Right side
USB-2 Left side(with ESATA)
: means Analog Ground USB-3 Dock
power USB-4 Camera
plane
USB-5 WLAN
+B +5VALW +1.8V +5VS @ : means just reserve , no build USB-6 Bluetooth
+3VS USB-7 Finger Printer
+3VALW +1.5VS
45@ : means need be mounted when 45 level assy or rework stage. USB-8 MiniCard(WWAN/TV)
+0.9V DEBUG@ : means just reserve for debug. USB-9 Express card
State +VCCP USB-10 X
+CPU_CORE
BATT @ : means need be mounted when 45 level assy or rework stage. USB-11 X
+2.5VS CONN@ : means ME part
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+1.8VS
ESATA @ : means just reserve for ESATA PCIe assignment:
GS @ : means just reserve for G sensor PCIe-1 TV /WWAN/Robeson
S0 O O O O PCIe-2 X
FP @ : means just reserve for Finger Print PCIe-3 WLAN
S1 O O O O Multi @ : means just reserve for Multi Bay PCIe-4 GLAN (Realtek)
PCIe-5 Card reader
S3
NewC@ : means just reserve for New card PCIe-6 New Card
O O O X
DOCK@ : means just reserve for Docking
S5 S4/AC O O X X Main@ : means just reserve for Main stream
S5 S4/ Battery only O X X X OPP@ : means just reserve for OPP
S5 S4/AC & Battery 2MiniC@ : means just reserve for 2nd Mini card slot
don't exist X X X X
1 1
SMB_CK_CLK1
SMB_CK_DAT1
ICH9 X X X X V V V X X V V
LCD_CLK
LCD_DAT
Cantiga X X X X X X X V X X X
43154432L01 UMA GM PA FF (SI-1)
43154432L02 UMA GM PR FF (SI-1)
43154432L01 Main@/DEBUG@/DOCK@/NewC@/FP @/ESATA@/GS@/Multi@/2MiniC@ 43154432L03 UMA GL PR FF-
43154432L02 Main@/DEBUG@/DOCK@/NewC @/FP@/ESATA@/GS@/2MiniC@ 43154432L04 UMA GM OPP (SI-1)
43154432L03 Main@/DEBUG@/DOC K@/NewC@/FP@/2MiniC@ 43154432L05 U MA GL OPP
43154432L04 OP P@/DEBUG@ Cantiga GM45 B0(QR32) SA00001P930
43154432L05 OP P@/DEBUG@ ICH9M A2 ES2 Base SA00002AN10
DA600007100 --->Main THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Do c ument Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cu s tom Montevina B lade 0 .3
DAZ03V00100 --->OPP DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
UMA LA 4101P
Da te: S a turday, January 05, 2008 Sheet 3 of 46
A
5 4 3 2 1
50mA
Finger printer
177mA
ICH9 50mA
1A PC Camera
D
+V_BATTERY Dock con D
300mA
LAN 25mA +3VS_DVDD
ALC268
60mA 35mA
+3VAUX_BT MDC 1.5
0.3A 20mA 1A
INVPWR_B+ LVDS CON +3VALW_EC New card
10mA 278mA
AC VIN SPI ROM ICH9
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1.7A 5.89A 3.39A
+3VALW +3VS 1.5A
2A 550mA +LCDVDD LVDS CON
B++ JMB385
250mA
+3VS_CK505
C
657mA ICH_VCC1_5 C
1A
0.3A 2.2A ICH9 Mini card (WLAN)
+1.5VS 1.56A
ICH9 1A
Mini card (TV tu/WWAN/Robeson)
35mA +VDDA
0.58A 1.3A
+5VALW +5VS IDT 9271B7
B+
10mA
7A +5VAMP
1.8A
ODD
700mA
SATA
B B
3.7A
3.7 X 3=11.1V MCH 1.8A
Muti Bay
DC BATT 8 A
1.9A 12.11A DDR2 800Mhz 4G x2
B+++ +1.8V
50mA
+0.9V
1.17A
ICH9
4.7A 1.26A
1.05V_B+ +VCCP MCH
2.3A
CPU
2A 10mA 34A/1.025V
CPU_B+ +VCC_CORE CPU
A A
Security Classification
2007/08/28
Compal Secret Data
2006/03/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power delivery
Size Do cu me n t Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C Mo n tevina Blade UMA LA4101P 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Sa tu r d a y, Ja n u ary 05, 2008 Sheet 4 of 46
5 4 3 2 1
A
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1 1
+3VS
@ R1
ITP-XDP Connector XDP_DBRESET#_R 1 2 1K_0402_5%
+ VCCP
Change value in 5/02
ADDR GROUP_0
H_A#4 L5 E2 H_ B NR# 25 26
A[4]# BNR# H_ BNR# <9> GND8 GND9
H_A#5 L4 G5 H_ BPRI# 27 28
A[5]# BPRI# H_ BPRI# <9> OBSDATA_B0 OBSDATA_D0
H_A#6 K5 29 30 This shall place near CPU
H_A#7 A[6]# H_ D EFER# OBSDATA_B1 OBSDATA_D1
M3 H5 H_ DEFER# <9> 31 32
H_A#8 A[7]# DEFER# H_ DRDY # GND10 GND11
N2 F21 H_ DRDY # <9> 33 34
H_A#9 A[8]# DRDY# H_ DBSY# R9 OBSDATA_B2 OBSDATA_D2
J1 E1 H_ DBSY# <9> 35 36
H_A#10 A[9]# DBSY# 1K_0402_5% OBSDATA_B3 OBSDATA_D3
N3 37 38
H_A#11 A[10]# H _BR0# GND12 GND13
P5 F1 H_BR0# <9> <7,21> H_ P W RGOOD 2 1H_ P W RG OOD_R 39 40 CLK_CPU_XDP CLK_CPU_XDP <17>
H_A#12 A[11]# BR0# XDP_HOOK1 PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_CPU_XDP#
P2 41 42 CLK_CPU_XDP# <17>
H_A#13 A[12]# H_ IE RR# T1 HOOK1 ITPCLK#/HOOK5
CONTROL
L2 D20 43 44
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A[13]# IERR# + VCCP VCC_OBS_AB VCC_OBS_CD + V CCP
H_A#14 P4 B3 H_ INIT# 2 1 45 46 H_RESET#_R R10 1 2 1K_0402_1% H_RESET#
A[14]# INIT# H_ INIT# <21> HOOK2 RESET#/HOOK6
H_A#15 P1 Place TP with a C1 0.1U_0402_16V4Z 47 48 XDP_DBRESET#_R R11 2 1 200_0402_1% XDP_DBRESET#
H_A#16 A[15]# H _LOCK# HOOK3 DBR#/HOOK7
R1 H4 49 50
H_ADSTB#0 M1
A[16]# LOCK# H_LOCK# <9> GND 0.1" away 51
GND14 GND15
52 XDP_TDO
<9> H_ADSTB#0 ADSTB[0]# SDA TD0
C1 H_RESET# Removed at 5/30.(Follow 53 54 XDP_TRST#
RESET# H_RESET# <9> SCL TRST#
H _REQ#0 K3 F3 H _RS#0 55 56 XDP_TDI R12
<9> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <9> Chimay) TCK1 TDI
H _REQ#1 H2 F4 H _RS#1 XDP_TCK 57 58 XDP_TMS 0_0402_5%
<9> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <9> TCK0 TMS
H _REQ#2 K2 G3 H _RS#2 59 60 XDP_PRE 1 2
<9> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <9> GND16 GND17
H _REQ#3 J3 G2 H_ T RDY#
<9> H_REQ#3 REQ[3]# TRDY# H_ T RDY# <9>
H _REQ#4 L1 SAMTE_BSH-030-01-L-D-A
<9> H_REQ#4 REQ[4]# H _HIT# C ONN@
Place R191 within 200ps (~1") to CPU
<9> H_A#[17..35] G6 H_HIT# <9>
H_A#17 HIT# H _HITM#
Y2 E4 H_HITM# <9>
C H_A#18 A[17]# HITM# C
U5
H_A#19 A[18]# XDP_BPM#0
R3 AD4
A[19]# BPM[0]#
ADDR GROUP_1
U1 AC2
H_A#24 A[23]# PRDY# XDP_BPM#5
R4 AC1
H_A#25 A[24]# PREQ# XDP_TCK +3VS
T5 AC5
H_A#26 A[25]# TCK XDP_TDI
T3 AA6
H_A#27 A[26]# TDI XDP_TDO
W2 AB3
H_A#28 A[27]# TDO XDP_TMS
W5 AB5
A[28]# TMS
0.1U_0402_16V4Z
H_A#29 Y4 AB6 XDP_TRST# 1
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 C20 XDP_DBRESET# <22>
H_A#31 A[30]# DBR# C2
V4
H_A#32 A[31]# U1
W3
H_A#33 A[32]# 2
AA4
A[33]# THERMAL
H_A#34 AB2 H_ P ROCHOT# R13 1 2 49.9_0402_1%
H_A#35 A[34]# + V CCP SMB_EC_CK2
AA3 D21 1 8 SMB_EC_CK2 <32>
H_ADSTB#1 A[35]# PROCHOT# H_ THERMDA_R R14 VDD SMCLK
<9> H_ADSTB#1 V1 A24 1 2 100_0402_5% H_ THERMDA
ADSTB[1]# THERMDA H_ T H ERMDC_R R15
B25 1 2 100_0402_5% H_ T H ERMDC H_ THERMDA 2 7 SMB_EC_DA2
SMB_EC_DA2 <32>
H_A20M# THERMDC C3 DP SMDATA
<21> H_A20M# A6
A20M#
ICH
RSVD[05]
D2
RSVD[06]
D22
RSVD[07]
D3
RSVD[08] For Merom, R14 and R15 are 0ohm
F6
RSVD[09] For Penryn, R14 and R15 are 100ohm.
PWM Fan Control circuit
+5VS
P enryn
11/01 update
JP2
1
1
2
2
1
+ V CCP
1 1
D1 C4 C5 3
4.7U_0805_10V4Z 0.1U_0402_16V4Z GND
4
RB751V_SOD323 GND
1
@ 2 2 ACES_88231-02001
2
R17 C ONN@
56_0402_5%
+ FAN
2 2
1
2
5
6
1
B
D Q2 @ D2 ACES_85204-02001_2P to
E
H_ P ROCHOT# 3 1 O CP# G
OCP# <22> ACES_88231-02001_2P
C
@ Q1 3 RLZ5.1B_LL34
<32> F AN_PWM
MMBT3904_NL_SOT23-3 S SI3456BDV-T1-E3_TSOP6
2
4
+ V CCP
A A
2
R18
56_0402_5%
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(1/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 6 of 46
5 4 3 2 1
5 4 3 2 1
+ V CC_CORE + V CC_CORE
<9> H_ D# [0..15] H_ D#[32..47] <9>
J CPU1B J CP U1C
H_ D#0 E22 Y22 H _D#32 A7 AB20
H_ D#1 D[0]# D[32]# H _D#33 VCC[001] VCC[068]
F24 AB24 A9 AB7
H_ D#2 D[1]# D[33]# H _D#34 VCC[002] VCC[069]
E26 V24 A10 AC7
D[2]# D[34]# VCC[003] VCC[070]
DATA GRP 0
H_ D#3 G22 V26 H _D#35 A12 AC9
D[3]# D[35]# VCC[004] VCC[071]
DATA GRP 2
D H_ D#4 F23 V23 H _D#36 A13 AC12 D
H_ D#5 D[4]# D[36]# H _D#37 VCC[005] VCC[072]
G25 T22 A15 AC13
H_ D#6 D[5]# D[37]# H _D#38 VCC[006] VCC[073]
E25 U25 A17 AC15
H_ D#7 D[6]# D[38]# H _D#39 VCC[007] VCC[074]
E23 U23 A18 AC17
H_ D#8 D[7]# D[39]# H _D#40 VCC[008] VCC[075]
K24 Y25 A20 AC18
H_ D#9 D[8]# D[40]# H _D#41 VCC[009] VCC[076]
G24 W22 B7 AD7
H _D#10 D[9]# D[41]# H _D#42 VCC[010] VCC[077]
J24 Y23 B9 AD9
H _D#11 D[10]# D[42]# H _D#43 VCC[011] VCC[078]
J23 W24 B10 AD10
H _D#12 D[11]# D[43]# H _D#44 VCC[012] VCC[079]
H22 W25 B12 AD12
H _D#13 D[12]# D[44]# H _D#45 VCC[013] VCC[080]
F26 AA23 B14 AD14
H _D#14 D[13]# D[45]# H _D#46 VCC[014] VCC[081]
K22 AA24 B15 AD15
H _D#15 D[14]# D[46]# H _D#47 VCC[015] VCC[082]
H23 AB25 B17 AD17
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
<9> H_DSTBN#0 J26 Y26 H_DSTBN#2 <9> B18 AD18
H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2 VCC[017] VCC[084]
<9> H_DSTBP#0 H26 AA26 H_DSTBP#2 <9> B20 AE9
H_ D INV#0 DSTBP[0]# DSTBP[2]# H_ D INV#2 VCC[018] VCC[085]
<9> H_ DINV#0 H25 U22 H_ DINV#2 <9> C9 AE10
DINV[0]# DINV[2]# VCC[019] VCC[086]
<9> H_ D#[16..31] H_ D#[48..63] <9> C10 AE12
VCC[020] VCC[087]
C12 AE13
H _D#16 H _D#48 VCC[021] VCC[088]
N22 AE24 C13 AE15
H _D#17 D[16]# D[48]# H _D#49 VCC[022] VCC[089]
K25 AD24 C15 AE17
H _D#18 D[17]# D[49]# H _D#50 VCC[023] VCC[090]
P26 AA21 C17 AE18
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H _D#19 D[18]# D[50]# H _D#51 VCC[024] VCC[091]
R23 AB22 C18 AE20
H _D#20 D[19]# D[51]# H _D#52 VCC[025] VCC[092]
L23 AB21 D9 AF9
D[20]# D[52]# VCC[026] VCC[093]
DATA GRP 1
H _D#21 M24 AC26 H _D#53 D10 AF10
D[21]# D[53]# VCC[027] VCC[094]
DATA GRP 3
H _D#22 L22 AD20 H _D#54 D12 AF12
H _D#23 D[22]# D[54]# H _D#55 VCC[028] VCC[095]
M23 AE22 D14 AF14
H _D#24 D[23]# D[55]# H _D#56 VCC[029] VCC[096]
P25 AF23 D15 AF15
H _D#25 D[24]# D[56]# H _D#57 VCC[030] VCC[097]
P23 AC25 D17 AF17
H _D#26 D[25]# D[57]# H _D#58 VCC[031] VCC[098]
P22 AE21 D18 AF18
H _D#27 D[26]# D[58]# H _D#59 VCC[032] VCC[099] + VCCP
T24 AD21 E7 AF20
H _D#28 D[27]# D[59]# H _D#60 VCC[033] VCC[100] R19
R24 AC22 E9
H _D#29 D[28]# D[60]# H _D#61 VCC[034]
L25 AD23 E10 G21 + VCCPA 1 2 0_0402_5%
H _D#30 D[29]# D[61]# H _D#62 VCC[035] VCCP[01] + VCCPB 0_0402_5%
T25 AF22 E12 V6 1 2
C H _D#31 D[30]# D[62]# H _D#63 VCC[036] VCCP[02] R20 C
N25 AC23 E13 J6
H_DSTBN#1 D[31]# D[63]# H_DSTBN#3 VCC[037] VCCP[03]
<9> H_DSTBN#1 L26 AE25 H_DSTBN#3 <9> E15 K6 1
H_DSTBP#1 DSTBN[1]# DSTBN[3]# H_DSTBP#3 VCC[038] VCCP[04]
<9> H_DSTBP#1 M26 AF24 H_DSTBP#3 <9> E17 M6
H_ D INV#1 DSTBP[1]# DSTBP[3]# H_ D INV#3 VCC[039] VCCP[05] + C6
<9> H_ DINV#1 N24 AC20 H_ DINV#3 <9> E18 J21
DINV[1]# DINV[3]# VCC[040] VCCP[06] 330U_D2E_2.5VM_R7
E20 K21
+V_CPU_GTLREF COMP0 VCC[041] VCCP[07]
AD26 R26 F7 M21
@ R21 GTLREF COMP[0] VCC[042] VCCP[08] 2
1 2 1K_0402_5% TEST1 C23 MISC U26 COMP1 F9 N21
@ R22 TEST2 TEST1 COMP[1] COMP2 VCC[043] VCCP[09]
1 2 1K_0402_5% D25 AA1 F10 N6
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
T2 C24 Y1 F12 R21
TEST4 TEST3 COMP[3] VCC[045] VCCP[11]
T3 AF26 F14 R6
TEST5 TEST4 H_DPRSTP# R23 R24 R25 R26 VCC[046] VCCP[12]
T4 AF1 E5 H_DPRSTP# <9,21,43> F15 T21
TEST5 DPRSTP# VCC[047] VCCP[13]
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
TEST6 A26 B5 H_DPSLP# F17 T6
T5 TEST6 DPSLP# H_DPSLP# <21> VCC[048] VCCP[14]
1
TEST7 C3 D24 H_ DP WR# F18 V21
T6 TEST7 DPWR# H_ DP WR# <9> VCC[049] VCCP[15]
CPU_BSEL0 B22 D6 H_ P W R GOOD F20 W21
<17> CPU_BSEL0 BSEL[0] PWRGOOD H_ P W RGOOD <6,21> VCC[050] VCCP[16]
CPU_BSEL1 B23 D7 H _CPUSLP# AA7
<17> CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# <9> VCC[051]
CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
<17> CPU_BSEL2 BSEL[2] PSI# H_PSI# <43> VCC[052] VCCA[01] +1.5VS
AA10 C26
2
VCC[053] VCCA[02]
10U_0805_6.3V6M
0.01U_0402_16V7K
Penryn AA12
VCC[054]
AA13 AD6 CP U_VID0 <43>
VCC[055] VID[0]
* Route the TEST3 and TEST5 signals through AA15
VCC[056] VID[1]
AF5 CP U_VID1 <43> 1 1
AA17 AE5 CP U_VID2 <43>
a ground referenced Zo = 55-ohm trace that VCC[057] VID[2] C7 C8
AA18 AF4 CP U_VID3 <43>
VCC[058] VID[3]
ends in a via that is near a GND via and is AA20 AE3 CP U_VID4 <43>
VCC[059] VID[4] 2 2
Resistor placed within 0.5" AB9
VCC[060] VID[5]
AF3 CP U_VID5 <43>
accessible through an oscilloscope AC10
VCC[061] VID[6]
AE2 CP U_VID6 <43>
of CPU pin.Trace should be AB10
connection. AB12
VCC[062]
at least 25 mils away from AB14
VCC[063]
AF7 V CCSENSE
VCC[064] VCCSENSE V CCSENSE <43>
any other toggling signal. AB15
VCC[065] Near pin B26
AB17
COMP[0,2] trace width is 18 AB18
VCC[066]
AE7 VSSSENSE VSSSENSE <43>
VCC[067] VSSSENSE
B
mils. COMP[1,3] trace width B
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 Penryn
is 4 mils. .
166 0 1 1
R27
1K_0402_1%
+ V CC_CORE
2
+V_CPU_GTLREF
R29
2K_0402_1% R30 1 2 100_0402_1% VSSSENSE
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(2/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 7 of 46
5 4 3 2 1
5 4 3 2 1
+ V CC_CORE
5
1 1 1 1 1 1 1 1
Place these capacitors on C9 C10 C11 C1 2 C13 C14 C15 C16
L8 (North side,Secondary 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
Layer) 2 2 2 2 2 2 2 2
D D
+ V CC_CORE
J CP U1D
A4
VSS[001] VSS[082]
P6 5
A8
VSS[002] VSS[083]
P21 Place these capacitors on 1 1 1 1 1 1 1 1
A11 P24 C17 C18 C19 C2 0 C21 C22 C23 C24
VSS[003] VSS[084] L8 (North side,Secondary
A14 R2
VSS[004] VSS[085] Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
A16 R5
VSS[005] VSS[086] 2 2 2 2 2 2 2 2
A19 R22
VSS[006] VSS[087]
A23 R25
VSS[007] VSS[088]
AF2 T1
VSS[008] VSS[089]
B6 T4
VSS[009] VSS[090] + V CC_CORE
B8 T23
VSS[010] VSS[091]
B11 T26
VSS[011] VSS[092]
B13
VSS[012] VSS[093]
U3 5
B16
VSS[013] VSS[094]
U6 Place these capacitors on 1 1 1 1 1 1 1 1
B19 U21 C25 C26 C27 C2 8 C29 C30 C31 C32
VSS[014] VSS[095] L8 (North side,Secondary
B21 U24
VSS[015] VSS[096] Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
B24 V2
VSS[016] VSS[097] 2 2 2 2 2 2 2 2
C5 V5
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VSS[017] VSS[098]
C8 V22
VSS[018] VSS[099]
C11 V25
VSS[019] VSS[100]
C14 W1
VSS[020] VSS[101] + V CC_CORE
C16 W4
VSS[021] VSS[102]
C19 W23
VSS[022] VSS[103]
C2
VSS[023] VSS[104]
W26 5
C22
VSS[024] VSS[105]
Y3 Place these capacitors on 1 1 1 1 1 1 1 1
C25 Y6 C33 C34 C35 C3 6 C37 C38 C39 C40
VSS[025] VSS[106] L8 (North side,Secondary
D1 Y21
VSS[026] VSS[107] Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
D4 Y24
VSS[027] VSS[108] 2 2 2 2 2 2 2 2
D8 AA2
VSS[028] VSS[109]
D11 AA5
C VSS[029] VSS[110] C
D13 AA8
VSS[030] VSS[111]
D16 AA11
VSS[031] VSS[112]
D19 AA14
D23
VSS[032] VSS[113]
AA16
Mid Frequence Decoupling
VSS[033] VSS[114]
D26 AA19
VSS[034] VSS[115]
E3 AA22
VSS[035] VSS[116]
E6 AA25
VSS[036] VSS[117]
E8 AB1
VSS[037] VSS[118]
E11 AB4
VSS[038] VSS[119]
E14 AB8
VSS[039] VSS[120]
E16 AB11
VSS[040] VSS[121]
E19 AB13
E21
VSS[041]
VSS[042]
VSS[122]
VSS[123]
AB16 ESR <= 1.5m ohm
E24 AB19
VSS[043] VSS[124] Near CPU CORE regulator
F5
F8
VSS[044] VSS[125]
AB23
AB26
Capacitor > 1980uF
VSS[045] VSS[126]
F11 AC3
VSS[046] VSS[127]
F13 AC6
VSS[047] VSS[128] + V CC_CORE
F16 AC8
VSS[048] VSS[129]
F19 AC11
VSS[049] VSS[130]
F2 AC14
VSS[050] VSS[131]
F22 AC16
VSS[051] VSS[132]
330U_D2_2VY_R7M
330U_D2_2VY_R7M
330U_D2_2VY_R7M
330U_D2_2VY_R7M
F25 AC19
VSS[052] VSS[133]
G4 AC21
VSS[053] VSS[134]
G1 AC24 1 1 1 1
VSS[054] VSS[135] @
G23 AD2
VSS[055] VSS[136] C41 + C42 + C43 + C44 +
G26 AD5
VSS[056] VSS[137]
H3 AD8
VSS[057] VSS[138]
H6 AD11
VSS[058] VSS[139] 2 2 2 2
H21 AD13
VSS[059] VSS[140]
H24 AD16
VSS[060] VSS[141]
J2 AD19
B VSS[061] VSS[142] B
J5 AD22
VSS[062] VSS[143]
J22 AD25
VSS[063] VSS[144]
J25 AE1
VSS[064] VSS[145]
K1 AE4
VSS[065] VSS[146]
K4 AE8 11/21 Change ESR=7m ohm
VSS[066] VSS[147]
K23 AE11
VSS[067] VSS[148]
K26 AE14
VSS[068] VSS[149]
L3 AE16
VSS[069] VSS[150]
L6 AE19
VSS[070] VSS[151]
L21 AE23
VSS[071] VSS[152]
L24 AE26
VSS[072] VSS[153]
M2 A2
VSS[073] VSS[154]
M5 AF6
M22
VSS[074] VSS[155]
AF8 + V CCP Inside CPU center cavity in 2 rows
VSS[075] VSS[156]
M25
VSS[076] VSS[157]
AF11 5
N1 AF13
VSS[077] VSS[158]
N4 AF16 1 1 1 1 1 1
VSS[078] VSS[159] C45 C46 C47 C48 C49 C50
N23 AF19
VSS[079] VSS[160]
N26 AF21
VSS[080] VSS[161] 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
P3 A25
VSS[081] VSS[162] 2 2 2 2 2 2
AF25
VSS[163]
P enryn
.
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Penryn(3/3)-AGTL+/ITP-XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 8 of 46
5 4 3 2 1
5 4 3 2 1
2.2U_0603_6.3V4Z
0.01U_0402_25V7K
H_ D#1 G8 F16 H_A#5 R33 AT21 M _ CLK_DDR1 M _ CLK_DDR1 <15>
H_D#_1 H_A#_5 T9 RESERVED SA_CK_1
H_ D#2 F8 H13 H_A#6 T33 AV24 M _ CLK_DDR2 M _ CLK_DDR2 <16>
H_D#_2 H_A#_6 +1.8V T10 RESERVED SB_CK_0
H_ D#3 E6 C18 H_A#7 AH9 AU20 M _ CLK_DDR3 M _ CLK_DDR3 <16>
H_D#_3 H_A#_7 T11 RESERVED SB_CK_1
H_ D#4 G2 M16 H_A#8 AH10
H_D#_4 H_A#_8 T12 RESERVED
H_ D#5 H6 J13 H_A#9 1 1 AH12 AR24 M _ CLK_DDR#0
H_D#_5 H_A#_9 T13 RESERVED SA_CK#_0 M _ CLK_DDR#0 <15>
1
C51
C52
H_ D#6 H2 P16 H_A#10 AH13 AR21 M _ CLK_DDR#1
H_D#_6 H_A#_10 T14 RESERVED SA_CK#_1 M _ CLK_DDR#1 <15>
H_ D#7 F6 R16 H_A#11 R31 K12 AU24 M _ CLK_DDR#2
H_D#_7 H_A#_11 T15 RESERVED SB_CK#_0 M _ CLK_DDR#2 <16>
H_ D#8 D4 N17 H_A#12 1K_0402_1% AL34 AV20 M _ CLK_DDR#3
H_D#_8 H_A#_12 2 2 T16 RESERVED SB_CK#_1 M _ CLK_DDR#3 <16>
H_ D#9 H3 M13 H_A#13 AK34
H_D#_9 H_A#_13 T17 RESERVED
H _D#10 M9 E17 H_A#14 AN35 BC28 DDR _CKE0_DIMMA
T18 DDR_CKE0_DIMMA <15>
2
H _D#11 H_D#_10 H_A#_14 H_A#15 S MRCOMP_VOH RESERVED SA_CKE_0 DDR _CKE1_DIMMA
M11 P17 T19 AM35 AY28 DDR_CKE1_DIMMA <15>
D H _D#12 H_D#_11 H_A#_15 H_A#16 RESERVED SA_CKE_1 DDR _CKE2_DIMMB D
J1
H_D#_12 H_A#_16
F17 80% of 1.8V VCC_SM T20 T24
RESERVED SB_CKE_0
AY36 DDR_CKE2_DIMMB <16>
1
H _D#13 J2 G20 H_A#17 BB36 DDR _CKE3_DIMMB
H_D#_13 H_A#_17 SB_CKE_1 DDR_CKE3_DIMMB <16>
RSVD
H _D#14 N12 B19 H_A#18 R32 B31
H_D#_14 H_A#_18 T21 RESERVED
H _D#15 J6 J16 H_A#19 3.01K_0402_1% B2 BA17 DDR _CS0_DIMMA#
H_D#_15 H_A#_19 T22 RESERVED SA_CS#_0 DDR_CS0_DIMMA# <15>
H _D#16 P2 E20 H_A#20 20% of 1.8V VCC_SM M1 AY16 DDR _CS1_DIMMA#
H_D#_16 H_A#_20 T23 RESERVED SA_CS#_1 DDR_CS1_DIMMA# <15>
H _D#17 L2 H16 H_A#21 AV16 DDR _CS2_DIMMB#
DDR_CS2_DIMMB# <16>
2
H _D#18 H_D#_17 H_A#_21 H_A#22 SMRCOMP_VOL SB_CS#_0 DDR _CS3_DIMMB#
R2 J20 AR13 DDR_CS3_DIMMB# <16>
H _D#19 H_D#_18 H_A#_22 H_A#23 SB_CS#_1
N9 L17 T24 AY21
H_D#_19 H_A#_23 RESERVED
1
2.2U_0603_6.3V4Z
0.01U_0402_25V7K
H _D#20 L6 A17 H_A#24 BD17 M_ODT0 M_ODT0 <15>
H _D#21 H_D#_20 H_A#_24 H_A#25 R33 SA_ODT_0 M_ODT1
M5 B17 1 1 AY17 M_ODT1 <15>
H_D#_21 H_A#_25 SA_ODT_1 +1.8V
C5 3
C5 4
H _D#22 J3 L16 H_A#26 1K_0402_1% BF15 M_ODT2 M_ODT2 <16>
H _D#23 H_D#_22 H_A#_26 H_A#27 SB_ODT_0 M_ODT3
N2 C21 T25 BG23 AY13 M_ODT3 <16>
H _D#24 H_D#_23 H_A#_27 H_A#28 RESERVED SB_ODT_1
R1 J17 T26 BF23
2
H _D#25 H_D#_24 H_A#_28 H_A#29 2 2 RESERVED S MRCOMP R34
N5 H20 T27 BH18 BG22 1 2 80.6_0402_1%
H _D#26 H_D#_25 H_A#_29 H_A#30 RESERVED SM_RCOMP SMRCOMP# R35
N6 B18 T28 BF18 BH21 1 2 80.6_0402_1%
H _D#27 H_D#_26 H_A#_30 H_A#31 RESERVED SM_RCOMP#
P13
H_D#_27 H_A#_31
K17 Follow Design Guide
H _D#28 N8 B20 H_A#32 BF28 S MRCOMP_VOH
H _D#29 L7
H_D#_28 H_A#_32
F21 H_A#33 SM_RCOMP_VOH
BH28 SMRCOMP_VOL For Cantiga: 80.6ohm
H _D#30 H_D#_29 H_A#_33 H_A#34 SM_RCOMP_VOL
N10 K21
H _D#31 H_D#_30 H_A#_34 H_A#35 V _ DDR _MCH_REF
M3 L20 AV42
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H _D#32 H_D#_31 H_A#_35 SM_VREF SM_PWROK R36
Y3 AR36 1 2 0_0402_5%
H _D#33 H_D#_32 H _ADS# SM_PWROK SM_REXT R37
AD14 H12 H_ADS# <6> BF17 1 2 499_0402_1%
H _D#34 H_D#_33 H_ADS# H_ADSTB#0 SM_REXT TP_SM_DRAMRST#
Y6 B16 H_ADSTB#0 <6> BC36 T29 P AD
H _D#35 H_D#_34 H_ADSTB#_0 H_ADSTB#1 +3VS SM_DRAMRST#
Y10 G17 H_ADSTB#1 <6>
H _D#36 H_D#_35 H_ADSTB#_1 H_ B NR# CL K _ MCH_DREFCLK
Y12 A9 H_ B NR# <6> B38 CL K _ MCH_DREFCLK <17>
H _D#37 H_D#_36 H_BNR# H_ BPRI# PM_EXTTS#0 R38 DPLL_REF_CLK
Y14 F11 H_ BPRI# <6> 1 2 10K_0402_5% A38 CL K _MCH_DREFCLK#
CL K _MCH_DREFCLK# <17>
H _D#38 H_D#_37 H_BPRI# H _BR0# DPLL_REF_CLK# M CH_ SSCDREFCLK
Y7 G12 H_BR0# <6> E41 M CH_ SSCDREFCLK <17>
H _D#39 H_D#_38 H_BREQ# H_ D EFER# DPLL_REF_SSCLK M CH_ SSCDREFCLK#
W2 E9 F41
HOST
CLK
H _D#41 Y9 AH7 C LK_MCH_BCLK F43 CLK_MCH_3GPLL
H_D#_41 HPLL_CLK CLK_MCH_BCLK <17> PEG_CLK CLK_MCH_3GPLL <17>
H _D#42 AA13 AH6 CLK_MCH_BCLK# E43 CLK_MCH_3GPLL#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# <17> PEG_CLK# CLK_MCH_3GPLL# <17>
H _D#43 AA9 J11 H_ DP WR# CLKREQ#_7 R40 1 2 10K_0402_5%
C H_D#_43 H_DPWR# H_ DP WR# <7> C
H _D#44 AA11 F9 H_ DRDY #
H_D#_44 H_DRDY# H_ DRDY # <6>
H _D#45 AD11 H9 H _HIT#
H_D#_45 H_HIT# H_ HIT# <6>
H _D#46 AD10 E12 H _HITM# AE41 DMI_TXN0
H_D#_46 H_HITM# H_HITM# <6> DMI_RXN_0 DMI_TXN0 <22>
H _D#47 AD13 H11 H _LOCK# AE37 DMI_TXN1
H_D#_47 H_LOCK# H_ LOCK# <6> DMI_RXN_1 DMI_TXN1 <22>
H _D#48 AE12 C9 H_ T RDY# AE47 DMI_TXN2
H_D#_48 H_TRDY# H_ T RDY# <6> DMI_RXN_2 DMI_TXN2 <22>
H _D#49 AE9 AH39 DMI_TXN3
H_D#_49 DMI_RXN_3 DMI_TXN3 <22>
H _D#50 AA2
H _D#51 H_D#_50 DMI_TXP0
AD8 AE40 DMI_TXP0 <22>
H _D#52 H_D#_51 MCH_CLKSEL0 DMI_RXP_0 DMI_TXP1
AA3 <17> MCH_CLKSEL0 T25 AE38 DMI_TXP1 <22>
H _D#53 H_D#_52 H_ D INV#0 MCH_CLKSEL1 CFG_0 DMI_RXP_1 DMI_TXP2
AD3 J8 H_ DINV#0 <7> <17> MCH_CLKSEL1 R25 AE48 DMI_TXP2 <22>
H _D#54 H_D#_53 H_DINV#_0 H_ D INV#1 MCH_CLKSEL2 CFG_1 DMI_RXP_2 DMI_TXP3
AD7 L3 H_ DINV#1 <7> <17> MCH_CLKSEL2 P25 AH40 DMI_TXP3 <22>
H _D#55 H_D#_54 H_DINV#_1 H_ D INV#2 CFG_2 DMI_RXP_3
AE14 Y13 H_ DINV#2 <7> P20
H _D#56 H_D#_55 H_DINV#_2 H_ D INV#3 CFG_3 D MI_RXN0
AF3 Y1 H_ DINV#3 <7> P24 AE35 DMI_RXN0 <22>
H _D#57 H_D#_56 H_DINV#_3 CF G5 CFG_4 DMI_TXN_0 D MI_RXN1
AC1 <11> CF G5 C25 AE43 DMI_RXN1 <22>
H _D#58 H_D#_57 H_DSTBN#0 CF G6 CFG_5 DMI_TXN_1 D MI_RXN2
AE3 L10 H_DSTBN#0 <7> <11> CF G6 N24 AE46 DMI_RXN2 <22>
H _D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1 CF G7 CFG_6 DMI_TXN_2 D MI_RXN3
AC3 M7 H_DSTBN#1 <7> <11> CF G7 M24 AH42 DMI_RXN3 <22>
H _D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2 CF G8 CFG_7 DMI_TXN_3
AE11 AA5 H_DSTBN#2 <7> <11> CF G8 E21
H_D#_60 H_DSTBN#_2 CFG_8
CFG
H _D#61 AE8 AE6 H_DSTBN#3 CF G9 C23 AD35 DMI_RXP0
H_DSTBN#3 <7> <11> CF G9 DMI_RXP0 <22>
DMI
H _D#62 H_D#_61 H_DSTBN#_3 CF G10 CFG_9 DMI_TXP_0 DMI_RXP1
AG2 <11> CF G10 C24 AE44 DMI_RXP1 <22>
H _D#63 H_D#_62 H_DSTBP#0 CF G11 CFG_10 DMI_TXP_1 DMI_RXP2
AD6 L9 H_DSTBP#0 <7> <11> CF G11 N21 AF46 DMI_RXP2 <22>
H_D#_63 H_DSTBP#_0 H_DSTBP#1 CF G12 CFG_11 DMI_TXP_2 DMI_RXP3
M8 H_DSTBP#1 <7> <11> CF G12 P21 AH43 DMI_RXP3 <22>
H_DSTBP#_1 H_DSTBP#2 CF G13 CFG_12 DMI_TXP_3
AA6 H_DSTBP#2 <7> <11> CF G13 T21
+ H_ SWNG H_DSTBP#_2 H_DSTBP#3 CF G14 CFG_13
C5 AE5 H_DSTBP#3 <7> <11> CF G14 R20
H_ R COMP H_SWING H_DSTBP#_3 CF G15 CFG_14
E3 <11> CF G15 M20
H_RCOMP H _REQ#0 CF G16 CFG_15
B15 L21
GRAPHICS VID
H_REQ#_0 H_ REQ#0 <6> <11> CF G16 CFG_16
K13 H _REQ#1 CF G17 H21
H_REQ#_1 H_ REQ#1 <6> <11> CF G17 CFG_17
F13 H _REQ#2 CF G18 P29
H_REQ#_2 H_ REQ#2 <6> <11> CF G18 CFG_18
B13 H _REQ#3 CF G19 R28
H_REQ#_3 H_ REQ#3 <6> <11> CF G19 CFG_19
<6> H_RESET# H_RESET# C12 B14 H _REQ#4 CF G20 T28 B33
H_CPURST# H_REQ#_4 H_ REQ#4 <6> <11> CF G20 CFG_20 GFX_VID_0 T30
<7> H_CPUSLP# H _CPUSLP# E11 B32
H_CPUSLP# GFX_VID_1 T31
B6 H _RS#0 H_RS#0 <6> G33
H_RS#_0 GFX_VID_2 T32
F12 H _RS#1 H_RS#1 <6> F33
B H_RS#_1 GFX_VID_3 T33 B
C8 H _RS#2 H_RS#2 <6> <22> PM_BMBUSY# PM_BMBUSY# R29 E33
H_RS#_2 PM_SYNC# GFX_VID_4 T34
+ H_VREF A11 H_DPRSTP# B7
H_AVREF <7,21,43> H_DPRSTP# PM_DPRSTP#
B11 PM_EXTTS#0 N33
H_DVREF <15> PM_EXTTS#0 PM_EXT_TS#_0
PM_EXTTS#1 P32
<16> PM_EXTTS#1 PM_EXT_TS#_1
PM
CANTIGA ES_FCBGA1329 PM_PWROK AT40 C34
<22,32> PM_PWROK PWROK GFX_VR_EN T35 + V CCP
PLT_RST# R41 1 2 AT11
Layout note: <20,25,26,27> PLT_RST#
<6,21> H_THERMTRIP# R42 1 2 100_0402_5% THERMTRIP# T20
RSTIN#
0_0402_5% DP RSLPVR THERMTRIP#
Route H_SCOMP and H_SCOMP# with trace <22,43> DPRSLPVR R32
DPRSLPVR
1
width, spacing and impedance (55 ohm) same as CL_CLK
AH37 C L_CLK0
CL_CLK0 <22>
R43
0.1U_0402_16V4Z
AH36 CL_DATA0 1K_0402_1%
FSB data traces CL_DATA CL_DATA0 <22>
1 @ BG48
NC CL_PWROK
AN36 M _PWROK
M _PWROK <22,32>
C55 BF48 AJ35 CL_RST#
CL_RST# <22>
2
NC CL_RST# + CL_VREF
Layout Note: Layout Note: V_DDR_MCH_REF BD48 AH34
ME
NC CL_VREF
BC48
1
H_RCOMP / H_VREF / H_SWNG trace width and spacing is 20/20. 2 NC
BH47
NC
0621 add CLK and DAT for DVI 1
BG47 C5 6 R44
trace width and spacing is 10/20 BE47
NC
N28 0.1U_0402_16V4Z 499_0402_1%
+1.8V NC DDPC_CTRLCLK T36
BH46 M28 T37
NC DDPC_CTRLDATA HDM ICLK_NB 2
+V_DDR_MCH_REF generated by DC-DC BF46 G36 HDM ICLK_NB <35>
2
+ VCCP NC SDVO_CTRLCLK
NC
BG45 E36 HD MIDAT_NB
NC SDVO_CTRLDATA HDMIDAT_NB <35>
1
MISC
NC CLKREQ# CLKREQ#_7 <17>
R45 BH43 H36 M CH_ ICH _SYNC#
NC ICH_SYNC# M CH_ ICH_SYNC# <22>
1K_0402_1%
221_0603_1%
1K_0402_1% BH6
NC
1
BH2
2
0.1U_0402_16V4Z
1
100_0402_1%
0.1U_0402_16V4Z
A BF1 C29
1 1 HDA _SDOUT_NB <21>
2
2 NC HDA_SDO
2K_0402_1%
HDA
BC1
NC
F1
2 2 NC
A47 0830 Add pull-up and pull-down resistor.
2
NC
CANTIGA ES_FCBGA1329
Security Classification Compal Secret Data Compal Electronics, Inc.
within 100 mils from NB Near B3 pin Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(1/6)-AGTL/DMI/DDR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 9 of 46
5 4 3 2 1
5 4 3 2 1
D D
www.kythuatvitinh.com
DDR _A_D17 SA_DQ_16 SA_DM_5 DDR _A_DM6 DDR _B_D17 SB_DQ_16 SB_DM_4 DDR _B_DM5
AY44 AT7 BC44 BA3
DDR _A_D18 SA_DQ_17 SA_DM_6 DDR _A_DM7 DDR _B_D18 SB_DQ_17 SB_DM_5 DDR _B_DM6
BA40 AJ5 BG43 AP1
A
DDR _A_D19 SA_DQ_18 SA_DM_7 DDR _B_D19 SB_DQ_18 SB_DM_6 DDR _B_DM7
BD43 DDR_ A _DQS[0..7] <15> BF43 AK2
B
DDR _A_D20 SA_DQ_19 DDR _A_DQS0 DDR _B_D20 SB_DQ_19 SB_DM_7
AV41 AJ44 BE45 DDR_ B _DQS[0..7] <16>
DDR _A_D21 SA_DQ_20 SA_DQS_0 DDR _A_DQS1 DDR _B_D21 SB_DQ_20 DDR _B_DQS0
AY43 AT44 BC41 AL47
DDR _A_D22 SA_DQ_21 SA_DQS_1 DDR _A_DQS2 DDR _B_D22 SB_DQ_21 SB_DQS_0 DDR _B_DQS1
BB41 BA43 BF40 AV48
DDR _A_D23 SA_DQ_22 SA_DQS_2 DDR _A_DQS3 DDR _B_D23 SB_DQ_22 SB_DQS_1 DDR _B_DQS2
BC40 MEMORY BC37 BF41 BG41
DDR _A_D24 SA_DQ_23 SA_DQS_3 DDR _A_DQS4 DDR _B_D24 SB_DQ_23 SB_DQS_2 DDR _B_DQS3
AY37 AW12 BG38 BG37
MEMORY
DDR _A_D25 SA_DQ_24 SA_DQS_4 DDR _A_DQS5 DDR _B_D25 SB_DQ_24 SB_DQS_3 DDR _B_DQS4
BD38 BC8 BF38 BH9
DDR _A_D26 SA_DQ_25 SA_DQS_5 DDR _A_DQS6 DDR _B_D26 SB_DQ_25 SB_DQS_4 DDR _B_DQS5
AV37 AU8 BH35 BB2
DDR _A_D27 SA_DQ_26 SA_DQS_6 DDR _A_DQS7 DDR _B_D27 SB_DQ_26 SB_DQS_5 DDR _B_DQS6
AT36 AM7 DDR_ A _DQS#[0..7] <15> BG35 AU1
DDR _A_D28 SA_DQ_27 SA_DQS_7 DDR _A_DQS#0 DDR _B_D28 SB_DQ_27 SB_DQS_6 DDR _B_DQS7
AY38 AJ43 BH40 AN6 DDR_ B _DQS#[0..7] <16>
C DDR _A_D29 SA_DQ_28 SA_DQS#_0 DDR _A_DQS#1 DDR _B_D29 SB_DQ_28 SB_DQS_7 DDR _B_DQS#0 C
BB38 AT43 BG39 AL46
DDR _A_D30 SA_DQ_29 SA_DQS#_1 DDR _A_DQS#2 DDR _B_D30 SB_DQ_29 SB_DQS#_0 DDR _B_DQS#1
AV36 BA44 BG34 AV47
DDR _A_D31 SA_DQ_30 SA_DQS#_2 DDR _A_DQS#3 DDR _B_D31 SB_DQ_30 SB_DQS#_1 DDR _B_DQS#2
AW36 BD37 BH34 BH41
DDR _A_D32 SA_DQ_31 SA_DQS#_3 DDR _A_DQS#4 DDR _B_D32 SB_DQ_31 SB_DQS#_2 DDR _B_DQS#3
BD13 AY12 BH14 BH37
DDR _A_D33 SA_DQ_32 SA_DQS#_4 DDR _A_DQS#5 DDR _B_D33 SB_DQ_32 SB_DQS#_3 DDR _B_DQS#4
AU11 BD8 BG12 BG9
DDR _A_D34 SA_DQ_33 SA_DQS#_5 DDR _A_DQS#6 DDR _B_D34 SB_DQ_33 SB_DQS#_4 DDR _B_DQS#5
BC11 AU9 BH11 BC2
DDR _A_D35 SA_DQ_34 SA_DQS#_6 DDR _A_DQS#7 DDR _B_D35 SB_DQ_34 SB_DQS#_5 DDR _B_DQS#6
BA12 AM8 DDR_A_MA[0..14] <15> BG8 AT2
SA_DQ_35 SA_DQS#_7 SB_DQ_35 SB_DQS#_6
SYSTEM
SYSTEM
SA_DQ_37 SA_MA_0 SB_DQ_37 DDR_B_MA[0..14] <16>
DDR _A_D38 BD12 BC24 D DR_A_MA1 DDR _B_D38 BF8 AV17 D DR_B_MA0
DDR _A_D39 SA_DQ_38 SA_MA_1 D DR_A_MA2 DDR _B_D39 SB_DQ_38 SB_MA_0 D DR_B_MA1
BC12 BG24 BG7 BA25
DDR _A_D40 SA_DQ_39 SA_MA_2 D DR_A_MA3 DDR _B_D40 SB_DQ_39 SB_MA_1 D DR_B_MA2
BB9 BH24 BC5 BC25
DDR _A_D41 SA_DQ_40 SA_MA_3 D DR_A_MA4 DDR _B_D41 SB_DQ_40 SB_MA_2 D DR_B_MA3
BA9 BG25 BC6 AU25
DDR _A_D42 SA_DQ_41 SA_MA_4 D DR_A_MA5 DDR _B_D42 SB_DQ_41 SB_MA_3 D DR_B_MA4
AU10 BA24 AY3 AW25
DDR _A_D43 SA_DQ_42 SA_MA_5 D DR_A_MA6 DDR _B_D43 SB_DQ_42 SB_MA_4 D DR_B_MA5
AV9 BD24 AY1 BB28
DDR _A_D44 SA_DQ_43 SA_MA_6 D DR_A_MA7 DDR _B_D44 SB_DQ_43 SB_MA_5 D DR_B_MA6
BA11 BG27 BF6 AU28
DDR _A_D45 SA_DQ_44 SA_MA_7 D DR_A_MA8 DDR _B_D45 SB_DQ_44 SB_MA_6 D DR_B_MA7
BD9 BF25 BF5 AW28
DDR _A_D46 SA_DQ_45 SA_MA_8 D DR_A_MA9 DDR _B_D46 SB_DQ_45 SB_MA_7 D DR_B_MA8
AY8 AW24 BA1 AT33
DDR _A_D47 SA_DQ_46 SA_MA_9 DDR_A_MA10 DDR _B_D47 SB_DQ_46 SB_MA_8 D DR_B_MA9
BA6 BC21 BD3 BD33
DDR _A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR _B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
AV5 BG26 AV2 BB16
SA_DQ_48 SA_MA_11 SB_DQ_48 SB_MA_10
DDR
DDR _A_D49 AV7 BH26 DDR_A_MA12 DDR _B_D49 AU3 AW33 DDR_B_MA11
SA_DQ_49 SA_MA_12 SB_DQ_49 SB_MA_11
DDR
DDR _A_D50 AT9 BH17 DDR_A_MA13 DDR _B_D50 AR3 AY33 DDR_B_MA12
DDR _A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR _B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
AN8 AY25 AN2 BH15
DDR _A_D52 SA_DQ_51 SA_MA_14 DDR _B_D52 SB_DQ_51 SB_MA_13 DDR_B_MA14
AU5 AY2 AU33
DDR _A_D53 SA_DQ_52 DDR _B_D53 SB_DQ_52 SB_MA_14
AU6 AV1
DDR _A_D54 SA_DQ_53 DDR _B_D54 SB_DQ_53
AT5 AP3
DDR _A_D55 SA_DQ_54 DDR _B_D55 SB_DQ_54
AN10 AR1
DDR _A_D56 SA_DQ_55 DDR _B_D56 SB_DQ_55
AM11 AL1
DDR _A_D57 SA_DQ_56 DDR _B_D57 SB_DQ_56
AM5 AL2
DDR _A_D58 SA_DQ_57 DDR _B_D58 SB_DQ_57
AJ9 AJ1
DDR _A_D59 SA_DQ_58 DDR _B_D59 SB_DQ_58
AJ8 AH1
DDR _A_D60 SA_DQ_59 DDR _B_D60 SB_DQ_59
AN12 AM2
B DDR _A_D61 SA_DQ_60 DDR _B_D61 SB_DQ_60 B
AM13 AM3
DDR _A_D62 SA_DQ_61 DDR _B_D62 SB_DQ_61
AJ11 AH3
DDR _A_D63 SA_DQ_62 DDR _B_D63 SB_DQ_62
AJ12 AJ3
SA_DQ_63 SB_DQ_63
CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(2/6)-DDR2 A/B CH
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 10 of 46
5 4 3 2 1
5 4 3 2 1
U 2C
R148
ENBKL
Strap Pin Table
1 2
R57 +VCC_PEG
L32 000 = FSB 1066MHz
100K_0402_5% ENBKL L_BKLT_CTRL
<32> ENBKL G32 T37 1 2 CFG[2:0] FSB Freq
R58 L_BKLT_EN PEG_COMPI 010 = FSB 800MHz
+3VS 1 2 10K_0402_5% M32 T36 49.9_0402_1%
L_CTRL_CLK PEG_COMPO select
R59 1 2 10K_0402_5% M33 011 = FSB 667MHz
DDC2 _CLK L_CTRL_DATA PEGCOMP trace width
<19> DDC2 _CLK K33 H44 Others = Reserved
DD C2_DATA L_DDC_CLK PEG_RX#_0 and spacing is 20/25 mils.
<19> DDC2_DATA J33 J46
L_DDC_DATA PEG_RX#_1
L44
PEG_RX#_2
PEG_RX#_3
L40 CFG[4:3] Reserved
<19> E NA VDD E NA VDD M29 N41
R60 1 L_VDD_EN PEG_RX#_4
2 2.37K_0402_1% C44 P48 0 = DMI x 2
D LVDS_IBG PEG_RX#_5 D
Follow Intel DG & B43 N44 CFG5 (DMI select) 1 = DMI x 4
Checklist
E37
E38
LVDS_VBG
LVDS_VREFH
PEG_RX#_6
PEG_RX#_7
T43
U43
*
0 = T he iT PM Host Interface is enable
LVDS_VREFL PEG_RX#_8
LVDS
LVDS_ACLK- C41 Y43 CFG6
LVDS_ACLK+ LVDSA_CLK# PEG_RX#_9
C40 Y48 1 = T he iT PM Host Interface is disable
T80
LVDS_BCLK-
LVDS_BCLK+
B37
A37
LVDSA_CLK
LVDSB_CLK#
PEG_RX#_10
PEG_RX#_11
Y36
AA43 0 =(T LS)chiper suite with no confidentiality
*
T81 LVDSB_CLK PEG_RX#_12
AD37 CFG7 (Intel Management
LVDS_A0- PEG_RX#_13
H47 AC47 1 =(T LS)chiper suite with confidentiality
LVDS_A1-
LVDS_A2-
E46
G40
LVDSA_DATA#_0
LVDSA_DATA#_1
PEG_RX#_14
PEG_RX#_15
AD39 Engine Crypto strap) *
LVDS_A3- LVDSA_DATA#_2
T38 A40 H43
LVDSA_DATA#_3 PEG_RX_0
PEG_RX_1
J44 CFG8 Reserved
LVDS_A0+ H48 L43
GRAPHICS
LVDS_A1+ LVDSA_DATA_0 PEG_RX_2 TMDS_B_HPD#
D45 L41 TMDS_B_HPD# <35>
LVDS_A2+ LVDSA_DATA_1 PEG_RX_3
F40
LVDSA_DATA_2 PEG_RX_4
N40 CFG9 (PCIE Graphics 0 = Reverse Lane,15->0, 14->1
LVDS_A3+ B40 P47
T39 LVDSA_DATA_3 PEG_RX_5
N43 Lane Reversal) 1 = Normal Operation,Lane Number in
T72
LVDS_B0-
LVDS_B1-
A41
H38
LVDSB_DATA#_0
PEG_RX_6
PEG_RX_7
T42
U42 order *
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T73 LVDSB_DATA#_1 PEG_RX_8
LVDS_B2- G37 Y42
T74 LVDSB_DATA#_2 PEG_RX_9
LVDS_B3- J37 W47 CFG10 (PCIE 0 = Enable
T40 LVDSB_DATA#_3 PEG_RX_10
Y37
LVDS_B0+ PEG_RX_11 Lookback
B42 AA42 1 = Disable
T75
T77
LVDS_B1+
LVDS_B2+
G38
F37
LVDSB_DATA_0
LVDSB_DATA_1
PEG_RX_12
PEG_RX_13
AD36
AC48 CFG11
enable)
Reserved
*
T79 LVDSB_DATA_2 PEG_RX_14
LVDS_B3+ K37 AD40
T41 LVDSB_DATA_3 PEG_RX_15
TV_COMPS 00 = Reserved
T48
PCI-EXPRESS
TV_LUMA J41 TMDS_BDATA2# C274 1 2 0.1U_0402_10V7K TMDS_B_DATA2# <35> CFG[13:12] (XOR/ALLZ) 01 = XOR Mode Enabled
T49 PEG_TX#_0
TV_CRMA M46 TMDS_BDATA1# C275 1 2 0.1U_0402_10V7K TMDS_B_DATA1# <35> 10 = All Z Mode Enabled
T50 PEG_TX#_1
F25 M47 TMDS_BDATA0# C276 1 2 0.1U_0402_10V7K 11 = Normal Operation (Default)
TVA_DAC PEG_TX#_2 TMDS_B_DATA0# <35>
*
1
75_0402_1%
75_0402_1%
C C
Follow Intel DG & K25
TVC_DAC PEG_TX#_4
M42
TV
R61 R62 R63 R48 CFG[15:14] Reserved
Checklist PEG_TX#_5
H24 N38
TV_RTN PEG_TX#_6
T40
2
PEG_TX#_7
PEG_TX#_8
U37 CFG16 (FSB Dynamic ODT) 0 = Disabled
11/10 Disable TV out U40 1 = Enabled
+3VS @ R64 1 2 2.2K_0402_5%
C31
E32
TV_DCONSEL_0
PEG_TX#_9
PEG_TX#_10
Y40
AA46
*
R406 0_0402_5% TV_DCONSEL_1 PEG_TX#_11
1 2
PEG_TX#_12
AA37 CFG[18:17] Reserved
<18> M_BLUE M_BLUE AA40
M _GREEN PEG_TX#_13
<18> M _GREEN AD43
M _RED PEG_TX#_14
AC46 CFG19 (DMI Lane Reversal) 0 = Normal Operation
<18> M _ RED PEG_TX#_15
(Lane number in Order) *
1
1
150_0402_1%
150_0402_1%
150_0402_1%
CRT_RED PEG_TX_4
VGA
R47 CFG20 (PCIE/SDVO 0 = Only PCIE or SDVO is operational.
G29
CRT_IRTN
PEG_TX_5
PEG_TX_6
N37
T39 concurrent) 1 = PCIE/SDVO are operating simu.
*
3 V DD CCL PEG_TX_7
<18> 3 V DDCCL H32 U36
3 V DD CDA CRT_DDC_CLK PEG_TX_8
<18> 3 V DDCDA J32 U39
CRT _ HS YNCR68 1 H S Y NC CRT_DDC_DATA PEG_TX_9
<18> CRT _ HS YNC 2 J29 Y39
30.1_0402_1% CRT_HSYNC PEG_TX_10
E29 Y46
CRT _ VSYNC R69 1 V S Y NC CRT_TVO_IREF PEG_TX_11 +3VS
<18> CRT _ VSYNC 2 L29 AA36
30.1_0402_1% CRT_VSYNC PEG_TX_12
AA39
PEG_TX_13
AD42
PEG_TX_14
1
AD46
PEG_TX_15
1
R70 R71 +3VS
1.02K_0402_1% 4.02K_0402_1%
CANTIGA ES_FCBGA1329
B B
2
R72 1 2
<9> CF G16
2
CF G5 4.02K_0402_1%
<9> CF G5
1
@ @ R73 1 2
<9> CF G19
R74 4.02K_0402_1%
2.21K_0402_1%
@R75 1 2
<9> CF G20
4.02K_0402_1%
2
@R76 1 2
Solve 3G WWAN issue <9> CF G11
2.21K_0402_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(3/6)-VGA/LVDS/TV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 11 of 46
5 4 3 2 1
5 4 3 2 1
+ 3VS_DAC_BG +3VS **RED Mark: Means UMA & dis@ Power select**
R 88
1 2 ~It check by INTEL Graphics Disable + VCCP
+1.05VS_DPLLA
+VCCP
0.022U_0402_16V7K
BLM18PG181SN1D_0603
Guidelines~ +VCCP
0.1U_0402_16V4Z
10U_0805_10V4Z
+ V1.05VS_AXF
1
@ 1 1 1 U2 H 1 2 R 93
0_0603_5%
C68
C69
C70
R 90 1 2
R89
0.1U_0402_16V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1U_0603_10V4Z
852mA
VTT
U13 1 @ 10U_FLC-453232-100K_0.25A_10% 0_0603_5%
4.7U_0805_10V4Z
220U_D2_4VM
C73
C74
73mA T13 1 1 1
2 2 2 VTT
220U_6.3V_M
C77
B27 U12 +
1 1 1
2
VCCA_CRT_DAC VTT
C71
C72
C78
C79
A26 T12 +
+ 3VS_DAC_CRT VCCA_CRT_DAC VTT
U11
VTT 2 2 2
2.68mA T11
VTT 2 2 2 2
A25 U10
CRT
+ 3VS_DAC_BG VCCA_DAC_BG VTT
B25 T10
VSSA_DAC_BG VTT
D U9 D
+ 3VS_DAC_CRT +3VS VTT
T9
R 91 VTT
U8
VTT
1 2 +1.05VS_DPLLA F47 64.8mA T8
VCCA_DPLLA VTT
0.022U_0402_16V7K
0.47U_0603_10V7K
4.7U_0805_10V4Z
2.2U_0805_16V4Z
BLM18PG181SN1D_0603 U7
VTT
VTT +1.8V_SM_CK
0.1U_0402_16V4Z
PLL
+1.05VS_DPLLB VCCA_DPLLB VTT 1 1 1
1
C75
C76
U6 +1.05VS_DPLLB + VCCP R 95
1 1 VTT
@
0_0603_5%
0.1U_0402_16V4Z
C80
C81
C82
+1.05VS_HPLL AD1 24mA T6 R 94 1 2
VCCA_HPLL VTT
10U_0805_10V4Z
10U_0805_10V4Z
U5 1 2 0_0805_5%
VTT 2 2 2
R92
0.1U_0402_16V4Z
+1.05VS_MPLL AE1 139.2mA T5 10U_FLC-453232-100K_0.25A_10% @ 1 1 1
2 2 VCCA_MPLL VTT
C86
C87
10U_0805_10V4Z
C84
C85
V3
2
VTT
13.2mA U3 1 1
A LVDS
VTT
C83
+1.8V_TXLVDS J48 V2
VCCA_LVDS VTT 2 2 2
1 U2
C 88 VTT
J47 T2
VSSA_LVDS VTT 2 2
V1
@ R 96 1000P_0402_50V7K VTT
414uA U1
2 VTT
+3VS 1 2
0_0603_5% AD48
+1.5VS_PEG_BG VCCA_PEG_BG
R 97
A PEG
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+1.5VS 1 2
0_0603_5% + 1.05VS_HPLL + VCCP + 1.5VS_TVDAC + 1.5VS
50mA
1 +1.05VS_PEGPLL AA48 R 98 R 99
C 89 VCCA_PEG_PLL
1 2 1 2
0.022U_0402_16V7K
0.1U_0402_16V4Z
MBK2012121YZF_0805 0_0805_5%
0. 1U_0402_16V4Z AR20
2 VCCA_SM
0.1U_0402_16V4Z
10U_0805_10V4Z
AP20 1 1 1 1
VCCA_SM
C90
C91
AN20 720mA
VCCA_SM
POWER
C92
C93
AR17
VCCA_SM
AP17
+VCCP VCCA_SM 2 2 2 2
+1.05VS_A_SM
AN17
VCCA_SM
AT16
R 100 VCCA_SM
AR16
VCCA_SM
A SM
1 2 AP16
C VCCA_SM C
10U_0805_10V4Z
1 0_0805_5%
1 1 1
C94
C95
+ C 96 C 97
+VCC_PEG + VCCP
220U_D2_4VM 4. 7U_0805_10V4Z
2 2 2 2 321.35mA +1.05VS_MPLL + VCCP R 102
1U_0603_10V4Z AP28 R 101 1 2
VCCA_SM_CK 0_0805_5%
AN28 B22 +V1.05VS_AXF 1 2
VCCA_SM_CK VCC_AXF
10U_0805_10V4Z
AP25 26mA B21 MBK2012121YZF_0805 1
AXF
+1.05VS_A_SM_CK VCCA_SM_CK VCC_AXF
220U_D2_4VM
R 103 AN25 A21 1
VCCA_SM_CK VCC_AXF
C101
1 2 AN24 26mA +
VCCA_SM_CK 1 1
1U_0603_10V4Z
0.1U_0402_16V4Z
C98
0_0603_5% AM28 124mA C 99 C100
VCCA_SM_CK_NCTF
10U_0805_10V4Z
AM26
VCCA_SM_CK_NCTF 2 2
1 1 1 1 AM25
VCCA_SM_CK_NCTF A CK 0. 1U_0402_16V4Z
2 2
10U_0805_10V4Z
C103
C104
C105
SM CK
VCCA_SM_CK_NCTF VCC_SM_CK +1.8V_SM_CK
AM24 BH20
1U_0603_10V4Z AL24 VCCA_SM_CK_NCTF VCC_SM_CK BG20
2 2 2 2 VCCA_SM_CK_NCTF VCC_SM_CK
AM23 BF20
VCCA_SM_CK_NCTF VCC_SM_CK
AL23
VCCA_SM_CK_NCTF
118.8mA
TVA 24.15mA + 1.05VS_DMI
K47 +1.05VS_PEGPLL + VCCP + VCCP
TVB 39.48mA VCC_TX_LVDS +1.8V_TXLVDS
B24 L1 R 104
TVX 24.15mA
VCCA_TV_DAC + 3VS_HV
A24 C35 1 2 1 2
TV
0.1U_0402_16V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
A35
HV
VCC_HV
1 1
0.1U_0402_16V4Z
C106
C108
Check Again!!! A32 50mA
HDA
+1.5VS VCC_HDA 1
C109
V48 +VCC_PEG 1
VCC_PEG
C107
1732mA VCC_PEG
U48
V47 2 2
PEG
VCC_PEG 2
U47
D TV/CRT
VCC_PEG 2
+ 1.5VS_TVDAC M25 58.67mA U46
VCCD_TVDAC VCC_PEG
B + 1.5VS_QDAC L28 48.363mA B
VCCD_QDAC
AH48 + 1.05VS_DMI
VCC_DMI
+ 1.05VS_HPLL AF1
VCCD_HPLL
157.2mA VCC_DMI
AF48
AH47
DMI
VCC_DMI
+1.05VS_PEGPLL AA47 50mA AG47
VCCD_PEG_PLL VCC_DMI + VCCP_D
456mA
M38
LVDS
0.47U_0603_10V7K
0.47U_0603_10V7K
+3VS
1 1 1
C110
C111
C112
C ANTIGA ES_FCBGA1329
2 2 2
+ 1.8V_LVDS +1.8V_TXLVDS
40 mils
R 107 R 108
1 2 + 1.8V 1 2 + 1.8V
@ R109
10U_0805_10V4Z
1U_0603_10V4Z
@ R110
1000P_0402_50V7K
0_0603_5% 0_0603_5%
1
+ 1.5VS_QDAC 1 1 1 @
0_0603_5%
C113
C114
0_0603_5%
C116
220U_D2_4VM
+1.5VS
+ 3VS_TVDAC +3VS 1
C115
+
R 111 R 112
1 2 1 2 2 2 2
2
2 2
0.022U_0402_16V7K
0.022U_0402_16V7K
BLM18PG181SN1D_0603 100_0603_1%
1
A A
@ R113
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 @
1
0_0603_5%
C117
C118
@ R114
C119
C120
220U_D2_4VM
1 1 1 1
0_0603_5%
C121
+
2
2 2 2 2 2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(4/6)-PWR
Size D ocument Number R ev
ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C ustom M o n te v ina Blade UMA LA4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: Sat ur day, January 05, 2008 Sheet 12 of 46
5 4 3 2 1
5 4 3 2 1
U2 G + V CCP
3000mA
Extnal Graphic: 1210.34mA AP33
VCC_SM VCC_AXG_NCTF
W28
AN33 V28
integrated Graphic: 1930.4mA VCC_SM VCC_AXG_NCTF 0.1U_0402_16V4Z 4.7U_0603_6.3V6M
+1.8V BH32 W26
U2 F VCC_SM VCC_AXG_NCTF
BG32 V26
+ VCCP VCC_SM VCC_AXG_NCTF
330U_D2E_2.5VM_R7
0.01U_0402_16V7K
BF32 W25 1 1 1
VCC_SM VCC_AXG_NCTF
10U_0805_10V4Z
10U_0805_10V4Z
1 BD32 V25 C127 C128 C129
VCC_SM VCC_AXG_NCTF
1 1 2 BC32 W24
VCC_SM VCC_AXG_NCTF
C126
C122
C130
C123
D AG34 + BB32 V24 D
VCC VCC_SM VCC_AXG_NCTF 2 2 2
AC34 BA32 W23
VCC VCC_SM VCC_AXG_NCTF
AB34 AY32 V23
VCC 2 2 2 1 VCC_SM VCC_AXG_NCTF 0.22U_0402_10V4Z
AA34 AW32 AM21
VCC VCC_SM VCC_AXG_NCTF
Y34 AV32 AL21
VCC VCC_SM VCC_AXG_NCTF
V34 AU32 AK21
VCC VCC_SM VCC_AXG_NCTF
U34 AT32 W21
VCC 0317 change value VCC_SM VCC_AXG_NCTF
AM33 AR32 V21
VCC VCC_SM VCC_AXG_NCTF
AK33 AP32 U21
VCC VCC_SM VCC_AXG_NCTF
POWER
AJ33 AN32 AM20
VCC VCC_SM VCC_AXG_NCTF
0.22U_0402_10V4Z
0.22U_0402_10V4Z
0.1U_0402_16V4Z
AG33 BH31 AK20
VCC VCC_SM VCC_AXG_NCTF
220U_D2_4VM
10U_0805_10V4Z
VCC CORE
VCC VCC_SM VCC_AXG_NCTF
1 1 1 1 BF31 U20
VCC_SM VCC_AXG_NCTF
C131
C124
C132
C133
+ C125
AE33 BG30 AM19
VCC VCC_SM VCC_AXG_NCTF
AC33 BH29 AL19
VCC VCC_SM VCC_AXG_NCTF
AA33 BG29 AK19
2 2 2 2 2 VCC VCC_SM VCC_AXG_NCTF
Y33 BF29 AJ19
VCC VCC_SM VCC_AXG_NCTF
W33 BD29 AH19
VCC VCC_SM VCC_AXG_NCTF
V33 BC29 AG19
VCC SM
VCC VCC_SM VCC_AXG_NCTF
U33 BB29 AF19
www.kythuatvitinh.com
VCC VCC_SM VCC_AXG_NCTF
AH28 BA29 AE19
VCC VCC_SM VCC_AXG_NCTF
AF28 AY29 AB19
VCC VCC_SM VCC_AXG_NCTF
AC28 AW29 AA19
VCC VCC_SM VCC_AXG_NCTF
AA28 AV29 Y19
VCC VCC_SM VCC_AXG_NCTF
AJ26 AU29 W19
VCC VCC_SM VCC_AXG_NCTF
AG26 AT29 V19
VCC VCC_SM VCC_AXG_NCTF
AE26 AR29 U19
VCC VCC_SM VCC_AXG_NCTF
AC26 AP29 AM17
VCC VCC_SM VCC_AXG_NCTF
AH25 AK17
VCC VCC_AXG_NCTF
AG25 BA36 AH17
VCC VCC_SM/NC VCC_AXG_NCTF
AF25 BB24 AG17
VCC VCC_SM/NC VCC_AXG_NCTF
AG24 BD16 AF17
C VCC + V CCP VCC_SM/NC VCC_AXG_NCTF C
AJ23 BB21 AE17
VCC VCC_SM/NC VCC_AXG_NCTF
AH23 AW16 AC17
VCC VCC_SM/NC VCC_AXG_NCTF
AF23 AW13 AB17
VCC VCC_SM/NC VCC_AXG_NCTF
POWER
AM32 AT13 Y17
VCC_NCTF VCC_SM/NC VCC_AXG_NCTF
T32 AL32 W17
VCC VCC_NCTF VCC_AXG_NCTF
VCC_NCTF
AK32 6326.84mA VCC_AXG_NCTF
V17
330U_D2E_2.5VM_R7
U32 Y24 AC16
VCC_NCTF VCC_AXG VCC_AXG_NCTF
AM30 1 1 1 1 1 AE23 AB16
VCC_NCTF C134 C136 C137 C138 VCC_AXG VCC_AXG_NCTF
AL30 AC23 AA16
VCC_NCTF + C135 VCC_AXG VCC_AXG_NCTF
AK30 AB23 Y16
VCC_NCTF 1U_0603_10V4Z VCC_AXG VCC_AXG_NCTF
AH30 AA23 W16
VCC_NCTF 2 2 2 2 VCC_AXG VCC_AXG_NCTF
AG30 AJ21 V16
VCC_NCTF 2 VCC_AXG VCC_AXG_NCTF
AF30 AG21 U16
VCC_NCTF 10U_0805_10V4Z VCC_AXG VCC_AXG_NCTF
AE30 AE21
VCC_NCTF VCC_AXG
AC30 AC21
VCC_NCTF VCC_AXG
AB30 AA21
VCC_NCTF VCC_AXG
AA30 Y21
VCC_NCTF VCC_AXG
Y30 AH20
VCC NCTF
VCC_NCTF VCC_AXG
W30 AF20
VCC_NCTF VCC_AXG
V30 AE20
VCC_NCTF VCC_AXG
U30 AC20
VCC_NCTF VCC_AXG
AL29 AB20
VCC_NCTF VCC_AXG
AK29 AA20
VCC_NCTF VCC_AXG
AJ29 T17
B VCC_NCTF VCC_AXG B
AH29 T16
VCC_NCTF VCC_AXG
AG29 AM15
VCC_NCTF VCC_AXG
AE29 AL15
VCC_NCTF VCC_AXG
AC29 AE15
VCC_NCTF VCC_AXG
AA29 AJ15
VCC_NCTF VCC_AXG
Y29 AH15
VCC_NCTF VCC_AXG
W29 AG15
VCC_NCTF VCC_AXG
V29 AF15
VCC_NCTF VCC_AXG
AL28 AB15
VCC_NCTF VCC_AXG
AK28 AA15
VCC_NCTF VCC_AXG
AL26 Y15
VCC GFX
VCC_NCTF VCC_AXG
AK26 V15
VCC_NCTF VCC_AXG
AK25 U15
VCC_NCTF VCC_AXG
AK24 AN14
VCC_NCTF VCC_AXG
AK23 AM14
VCC_NCTF VCC_AXG VCCSM_LF1
U14 AV44
VCC_AXG VCC_SM_LF VCCSM_LF2
T14 BA37
VCC SM LF
VCC_AXG VCC_SM_LF VCCSM_LF3
AM40
VCC_SM_LF VCCSM_LF4
AV21
VCC_SM_LF VCCSM_LF5
AY5
VCC_SM_LF VCCSM_LF6
AM10
CANTIGA ES_FCBGA1329 VCC_SM_LF VCCSM_LF7
BB13
VCC_SM_LF
C139 0.1U_0402_16V4Z
C140 0.1U_0402_16V4Z
C141
C142
C143
C144
C145
1 1 1 1 1 1 1
P AD T42 AJ14
VCC_AXG_SENSE
P AD T43 AH14
VSS_AXG_SENSE 2 2 2 2 2 2 2
0.22U_0603_10V7K
0.22U_0603_10V7K
0.47U_0402_6.3V6K
1U_0603_10V4Z
1U_0603_10V4Z
A A
CANTIGA ES_FCBGA1329
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(5/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 13 of 46
5 4 3 2 1
5 4 3 2 1
U2 J
U2 I BG21 AH8
VSS VSS
L12 Y8
VSS VSS
AU48 AM36 AW21 L8
VSS VSS VSS VSS
AR48 AE36 AU21 E8
VSS VSS VSS VSS
AL48 P36 AP21 B8
VSS VSS VSS VSS
BB47 L36 AN21 AY7
VSS VSS VSS VSS
AW47 J36 AH21 AU7
VSS VSS VSS VSS
AN47 F36 AF21 AN7
VSS VSS VSS VSS
AJ47 B36 AB21 AJ7
VSS VSS VSS VSS
AF47 AH35 R21 AE7
D VSS VSS VSS VSS D
AD47 AA35 M21 AA7
VSS VSS VSS VSS
AB47 Y35 J21 N7
VSS VSS VSS VSS
Y47 U35 G21 J7
VSS VSS VSS VSS
T47 T35 BC20 BG6
VSS VSS VSS VSS
N47 BF34 BA20 BD6
VSS VSS VSS VSS
L47 AM34 AW20 AV6
VSS VSS VSS VSS
G47 AJ34 AT20 AT6
VSS VSS VSS VSS
BD46 AF34 AJ20 AM6
VSS VSS VSS VSS
BA46 AE34 AG20 M6
VSS VSS VSS VSS
AY46 W34 Y20 C6
VSS VSS VSS VSS
AV46 B34 N20 BA5
VSS VSS VSS VSS
AR46 A34 K20 AH5
VSS VSS VSS VSS
AM46 BG33 F20 AD5
VSS VSS VSS VSS
V46 BC33 C20 Y5
VSS VSS VSS VSS
R46 BA33 A20 L5
VSS VSS VSS VSS
P46 AV33 BG19 J5
VSS VSS VSS VSS
H46 AR33 A18 H5
VSS VSS VSS VSS
F46 AL33 BG17 F5
VSS VSS VSS VSS
BF44 AH33 BC17 BE4
VSS VSS VSS VSS
AH44 AB33 AW17
www.kythuatvitinh.com
VSS VSS VSS
AD44 P33 AT17 BC3
AA44
Y44
VSS
VSS
VSS
VSS
VSS
VSS
L33
H33
R17
M17
VSS
VSS
VSS
VSS VSS
VSS
VSS
AV3
AL3
U44 N32 H17 R3
VSS VSS VSS VSS
T44 K32 C17 P3
M44
F44
VSS
VSS
VSS
VSS VSS
VSS
VSS
F32
C32 BA16
VSS
VSS
VSS
VSS
VSS
F3
BA2
BC43 A31 AW2
VSS VSS VSS
AV43 AN29 AU16 AU2
VSS VSS VSS VSS
AU43 T29 AN16 AR2
VSS VSS VSS VSS
AM43 N29 N16 AP2
VSS VSS VSS VSS
J43 K29 K16 AJ2
C VSS VSS VSS VSS C
C43 H29 G16 AH2
VSS VSS VSS VSS
BG42 F29 E16 AF2
VSS VSS VSS VSS
AY42 A29 BG15 AE2
VSS VSS VSS VSS
AT42 BG28 AC15 AD2
VSS VSS VSS VSS
AN42 BD28 W15 AC2
VSS VSS VSS VSS
AJ42 BA28 A15 Y2
VSS VSS VSS VSS
AE42 AV28 BG14 M2
VSS VSS VSS VSS
N42 AT28 AA14 K2
VSS VSS VSS VSS
L42 AR28 C14 AM1
VSS VSS VSS VSS
BD41 AJ28 BG13 AA1
VSS VSS VSS VSS
AU41 AG28 BC13 P1
VSS VSS VSS VSS
AM41 AE28 BA13 H1
VSS VSS VSS VSS
AH41 AB28
VSS VSS
AD41 Y28 U24
VSS VSS VSS
AA41 P28 AN13 U28
VSS VSS VSS VSS
Y41 K28 AJ13 U25
VSS VSS VSS VSS
U41 H28 AE13 U29
VSS VSS VSS VSS
T41 F28 N13
VSS VSS VSS
M41 C28 L13
VSS VSS VSS
G41 BF26 G13 AF32
VSS VSS VSS VSS_NCTF
B41 AH26 E13 AB32
VSS VSS VSS VSS_NCTF
BG40 AF26 BF12 V32
VSS VSS VSS VSS_NCTF
BB40 AB26 AV12 AJ30
VSS VSS VSS VSS_NCTF
AV40 AA26 AT12 AM29
VSS VSS VSS VSS_NCTF
AN40 C26 AM12 AF29
VSS VSS VSS VSS_NCTF
H40 B26 AA12 AB29
VSS NCTF
VSS VSS VSS VSS_NCTF
E40 BH25 J12 U26
VSS VSS VSS VSS_NCTF
AT39 BD25 A12 U23
VSS VSS VSS VSS_NCTF
AM39 BB25 BD11 AL20
VSS VSS VSS VSS_NCTF
AJ39 AV25 BB11 V20
VSS VSS VSS VSS_NCTF
AE39 AR25 AY11 AC19
VSS VSS VSS VSS_NCTF
N39 AJ25 AN11 AL17
B VSS VSS VSS VSS_NCTF B
L39 AC25 AH11 AJ17
VSS VSS VSS VSS_NCTF
B39 Y25 AA17
VSS VSS VSS_NCTF
BH38 N25 Y11 U17
VSS VSS VSS VSS_NCTF
BC38 L25 N11
VSS VSS VSS
BA38 J25 G11
VSS VSS VSS
AU38 G25 C11 BH48
VSS SCB
VSS VSS VSS VSS_SCB
AH38 E25 BG10 BH1
VSS VSS VSS VSS_SCB
AD38 BF24 AV10 A48
VSS VSS VSS VSS_SCB
AA38 AD12 AT10 C1
VSS VSS VSS VSS_SCB
Y38 AY24 AJ10 A3
VSS VSS VSS VSS_SCB
U38 AT24 AE10
VSS VSS VSS
T38 AJ24 AA10 E1
VSS VSS VSS NC
J38 AH24 M10 D2
VSS VSS VSS NC
F38 AF24 BF9 C3
VSS VSS VSS NC
C38 AB24 BC9 B4
VSS VSS VSS NC
BF37 R24 AN9 A5
VSS VSS VSS NC
BB37 L24 AM9 A6
VSS VSS VSS NC
AW37 K24 AD9 A43
VSS VSS VSS NC
AT37 J24 G9 A44
VSS VSS VSS NC
AN37 G24 B9 B45
NC
VSS VSS VSS NC
AJ37 F24 BH8 C46
VSS VSS VSS NC
H37 E24 BB8 D47
VSS VSS VSS NC
C37 BH23 AV8 B47
VSS VSS VSS NC
BG36 AG23 AT8 A46
VSS VSS VSS NC
BD36 Y23 F48
VSS VSS NC
AK15 B23 E48
VSS VSS NC
AU36 A23 C48
VSS VSS NC
AJ6 B48
VSS NC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cantiga(6/6)-PWR/GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 14 of 46
5 4 3 2 1
5 4 3 2 1
+1.8V +1.8V
2.2U_0805_16V4Z
0.1U_0402_16V4Z
1 2
VREF VSS
C146
C151
<10> DDR_ A _DM[0..7] 3 4 DDR_ A_D5 1 1
DDR_ A_D4 VSS DQ4 DDR_ A_D0
5 6
DDR_ A_D1 DQ0 DQ5
<10> DDR_ A _DQS[0..7] 7 8
DQ1 VSS DDR _A_DM0
9 10
DDR _A_DQS#0 VSS DM0 2 2
<10> DDR_A_MA[0..14] 11 12
DDR _A_DQS0 DQS0# VSS DDR_ A_D6
13 14
DQS0 DQ6 DDR_ A_D7
15 16
DDR_ A_D2 VSS DQ7
17 18
D DDR_ A_D3 DQ2 VSS DDR _A_D13 D
19 20
DQ3 DQ12 DDR _A_D12
Layout Note: DDR_ A_D8
21
VSS DQ13
22
23 24
Place near DDR_ A_D9 DQ8 VSS DDR _A_DM1
25 26
DQ9 DM1
JP3 27 28
DDR _A_DQS#1 VSS VSS M _ CLK_DDR0
29 30 M _ CLK_DDR0 <9>
DDR _A_DQS1 DQS1# CK0 M _ CLK_DDR#0
31 32 M _CLK_DDR#0 <9>
DQS1 CK0#
33 34
DDR _A_D11 VSS VSS DDR _A_D15
35 36
DDR _A_D10 DQ10 DQ14 DDR _A_D14
37 38
+1.8V DQ11 DQ15
39 40
VSS VSS
330U_D2E_2.5VM_R7
41 42
VSS VSS
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 DDR _A_D16 43 44 DDR _A_D20
DDR _A_D17 DQ16 DQ20 DDR _A_D21
1 1 1 1 1 1 1 1 1 45 46
DQ17 DQ21
C152
C147
C153
C154
C155
C156
C148
C149
C157
C150
+ 47 48
DDR _A_DQS#2 VSS VSS
49 50 PM_EXTTS#0 <9>
DDR _A_DQS2 DQS2# NC DDR _A_DM2
51 52
2 2 2 2 2 2 2 2 2 2 DQS2 DM2
53 54
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DDR _A_D18 VSS VSS DDR _A_D23
55 56
DDR _A_D19 DQ18 DQ22 DDR _A_D22
57 58
DQ19 DQ23
59 60
DDR _A_D29 VSS VSS DDR _A_D28
61 62
DDR _A_D24 DQ24 DQ28 DDR _A_D25
63 64
DQ25 DQ29
65 66
DDR _A_DM3 VSS VSS DDR _A_DQS#3
67 68
DM3 DQS3# DDR _A_DQS3
69 70
NC DQS3
71 72
DDR _A_D26 VSS VSS DDR _A_D31
73 74
DDR _A_D27 DQ26 DQ30 DDR _A_D30
75 76
DQ27 DQ31
77 78
C DDR _CKE0_DIMMA VSS VSS DDR _CKE1_DIMMA C
Layout Note: <9> DDR_CKE0_DIMMA 79
CKE0 NC/CKE1
80 DDR_CKE1_DIMMA <9>
81 82
Place one cap close to every 2 VDD VDD
83 84
D DR_A_BS2 NC NC/A15 DDR_A_MA14
pullup <10> DDR_A_BS2 85 86
BA2 NC/A14
87 88
VDD VDD
resistors terminated to +0.9VS DDR_A_MA12 89
A12 A11
90 DDR_A_MA11
D DR_A_MA9 91 92 D DR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
93 94
A8 A6
95 96
D DR_A_MA5 VDD VDD D DR_A_MA4
97 98
D DR_A_MA3 A5 A4 D DR_A_MA2
99 100
D DR_A_MA1 A3 A2 D DR_A_MA0
101 102
+0.9V A1 A0
103 104
DDR_A_MA10 VDD VDD D DR_A_BS1
105 106 DDR_A_BS1 <10>
D DR_A_BS0 A10/AP BA1 DD R_A_RAS#
5 10 <10> DDR_A_BS0 107
BA0 RAS#
108 DDR_A_RAS# <10>
DDR _A_WE# 109 110 DDR _CS0_DIMMA#
<10> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <9>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
111 112
DD R_A_CAS# VDD VDD M_ODT0
<10> DDR_A_CAS# 113 114 M_ODT0 <9>
DDR _CS1_DIMMA# CAS# ODT0 DDR_A_MA13
1 1 1 1 1 1 1 1 1 1 1 1 1 115 116
<9> DDR_CS1_DIMMA# NC/S1# NC/A13
117 118
M_ODT1 VDD VDD
<9> M_ODT1 119 120
NC/ODT1 NC
121 122
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR _A_D37 VSS VSS DDR _A_D32
123 124
DQ32 DQ36
C158
C159
C160
C161
C162
C163
C164
C165
C166
C167
C168
C169
C170
1
10K_0402_5%
10K_0402_5%
2.2U_0603_6.3V4Z
R115
R116
A M_ODT1 1 4 3 2 DDR_A_MA13 C171 C172 C ONN@ A
2 2
SO-DIMM A
2
RP13 56_0404_4P2R_5%
4 1 DDR _CKE1_DIMMA
DDR_A_MA11 1 2 3 2 DDR_A_MA14
R117 56_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 15 of 46
5 4 3 2 1
5 4 3 2 1
+1.8V +1.8V
<10> DDR_ B _DQS#[0..7]
2.2U_0805_16V4Z
0.1U_0402_16V4Z
1 2
VREF VSS DDR_ B_D5
<10> DDR_ B _DQS[0..7] 3 4 1 1
DDR_ B_D0 VSS DQ4 DDR_ B_D4
5 6
DQ0 DQ5
C173
C182
<10> DDR_B_MA[0..14] DDR_ B_D1 7 8
DQ1 VSS DDR _B_DM0
9 10
DDR _B_DQS#0 VSS DM0 2 2
11 12
DDR _B_DQS0 DQS0# VSS DDR_ B_D6
13 14
DQS0 DQ6 DDR_ B_D7
15 16
D DDR_ B_D2 VSS DQ7 D
17 18
DDR_ B_D3 DQ2 VSS DDR _B_D12
Layout Note: 19
DQ3 DQ12
20
DDR _B_D13
21 22
Place near DDR_ B_D8 VSS DQ13
23 24
DDR_ B_D9 DQ8 VSS DDR _B_DM1
JP10 25 26
DQ9 DM1
27 28
DDR _B_DQS#1 VSS VSS M _ CLK_DDR2
29 30 M _ CLK_DDR2 <9>
DDR _B_DQS1 DQS1# CK0 M _ CLK_DDR#2
31 32 M _CLK_DDR#2 <9>
DQS1 CK0#
33 34
DDR _B_D10 VSS VSS DDR _B_D14
35 36
DDR _B_D11 DQ10 DQ14 DDR _B_D15
37 38
+1.8V DQ11 DQ15
39 40
VSS VSS
5
41 42
VSS VSS
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR _B_D21 43 44 DDR _B_D16
DDR _B_D20 DQ16 DQ20 DDR _B_D17
1 1 1 1 1 1 1 1 1 45 46
DQ17 DQ21
C174
C175
C176
C183
C177
C178
C179
C180
C181
47 48
DDR _B_DQS#2 VSS VSS
49 50 PM_EXTTS#1 <9>
DDR _B_DQS2 DQS2# NC DDR _B_DM2
51 52
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2 2 2 2 2 2 2 2 2 DQS2 DM2
53 54
DDR _B_D19 VSS VSS DDR _B_D22
55 56
DDR _B_D18 DQ18 DQ22 DDR _B_D23
57 58
DQ19 DQ23
59 60
DDR _B_D28 VSS VSS DDR _B_D29
61 62
DDR _B_D25 DQ24 DQ28 DDR _B_D24
63 64
DQ25 DQ29
65 66
DDR _B_DM3 VSS VSS DDR _B_DQS#3
67 68
DM3 DQS3# DDR _B_DQS3
69 70
NC DQS3
71 72
DDR _B_D30 VSS VSS DDR _B_D26
73 74
DDR _B_D31 DQ26 DQ30 DDR _B_D27
C
Layout Note: 75
DQ27 DQ31
76
C
77 78
Place one cap close to every 2 DDR _CKE2_DIMMB VSS VSS DDR _CKE3_DIMMB
<9> DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB <9>
CKE0 NC/CKE1
pullup 81 82
VDD VDD
83 84
NC NC/A15
resistors terminated to +0.9VS <10> DDR_B_BS2
D DR_B_BS2 85
BA2 NC/A14
86 DDR_B_MA14
87
VDD VDD
88 0612 add
DDR_B_MA12 89 90 DDR_B_MA11
D DR_B_MA9 A12 A11 D DR_B_MA7
91 92
DDR_B_MA8 A9 A7 DDR_B_MA6
93 94
A8 A6
95 96
D DR_B_MA5 VDD VDD D DR_B_MA4
97 98
+0.9V D DR_B_MA3 A5 A4 D DR_B_MA2
99 100
D DR_B_MA1 A3 A2 D DR_B_MA0
101 102
A1 A0
5 10 103
VDD VDD
104
DDR_B_MA10 105 106 D DR_B_BS1
A10/AP BA1 DDR_B_BS1 <10>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C185
C186
C187
C188
C189
C190
C191
C192
C193
C194
C195
C196
121 122
DDR _B_D32 VSS VSS DDR _B_D36
123 124
DDR _B_D37 DQ32 DQ36 DDR _B_D33
125 126
DQ33 DQ37
127 128
DDR _B_DQS#4 VSS VSS DDR _B_DM4
129 130
DDR _B_DQS4 DQS4# DM4
131 132
DQS4 VSS DDR _B_D39
133 134
DDR _B_D34 VSS DQ38 DDR _B_D38
135 136
DDR _B_D35 DQ34 DQ39
137 138
DQ35 VSS DDR _B_D44
139 140
B DDR _B_D40 VSS DQ44 DDR _B_D45 B
Layout Note: DDR _B_D41
141
DQ40 DQ45
142
143 144
Place these resistor DQ41 VSS DDR _B_DQS#5
145 146
+0.9V DDR _B_DM5 VSS DQS5# DDR _B_DQS5
closely JP3,all 147 148
DM5 DQS5
149 150
VSS VSS
trace length Max=1.5" DDR _B_D42 151
DQ42 DQ46
152 DDR _B_D46
56_0404_4P2R_5% RP14 RP15 56_0404_4P2R_5% DDR _B_D43 153 154 DDR _B_D47
D DR_B_MA3 DDR_B_MA12 DQ43 DQ47
1 4 4 1 155 156
D DR_B_MA1 D DR_B_MA9 DDR _B_D48 VSS VSS DDR _B_D52
2 3 3 2 157 158
DDR _B_D49 DQ48 DQ52 DDR _B_D53
159 160
DQ49 DQ53
161 162
56_0404_4P2R_5% RP16 RP17 56_0404_4P2R_5% VSS VSS M _ CLK_DDR3
163 164 M _ CLK_DDR3 <9>
D DR_B_BS0 DDR_B_MA11 NC,TEST CK1 M _ CLK_DDR#3
1 4 4 1 165 166 M _CLK_DDR#3 <9>
DDR_B_MA10 DDR_B_MA14 DDR _B_DQS#6 VSS CK1#
2 3 3 2 167 168
DDR _B_DQS6 DQS6# VSS DDR _B_DM6
169 170
DQS6 DM6
171 172
56_0404_4P2R_5% RP18 RP19 56_0404_4P2R_5% DDR _B_D54 VSS VSS DDR _B_D50
173 174
D DR_B_MA0 D DR_B_MA5 DDR _B_D55 DQ50 DQ54 DDR _B_D51
1 4 4 1 175 176
D DR_B_BS1 DDR_B_MA8 DQ51 DQ55
2 3 3 2 177 178
DDR _B_D60 VSS VSS DDR _B_D56
179 180
DDR _B_D61 DQ56 DQ60 DDR _B_D57
181 182
56_0404_4P2R_5% RP20 RP21 56_0404_4P2R_5% DQ57 DQ61
183 184
DDR _CS2_DIMMB# 1 DDR_B_MA6 DDR _B_DM7 VSS VSS DDR _B_DQS#7
4 4 1 185 186
DD R_B_RAS# D DR_B_MA7 DM7 DQS7# DDR _B_DQS7
2 3 3 2 187 188
DDR _B_D63 VSS DQS7
189 190
DDR _B_D58 DQ58 VSS DDR _B_D59
191 192
56_0404_4P2R_5% RP22 RP23 56_0404_4P2R_5% DQ59 DQ62 DDR _B_D62
193 194
DD R_B_CAS# D DR_B_MA2 CLK_SMBDATA VSS DQ63
1 4 4 1 <15,17> CLK_SMBDATA 195 196
DDR _B_WE# D DR_B_MA4 CLK_SMBCLK SDA VSS R118
2 3 3 2 <15,17> CLK_SMBCLK 197 198
SCL SA0
+3VS 199 200 1 2 +3VS
VDDSPD SA1
1
10K_0402_5%
2.2U_0603_6.3V4Z
0.1U_0402_16V4Z
R119
A DDR _CS3_DIMMB# 2 3 4 1 DDR_B_MA13 FOX_AS0A426-N8RN-7F A
M_ODT3 1 4 3 2 M_ODT2 C197 C198 C ONN@
2 2 SO-DIMM B
2
RP26 56_0404_4P2R_5%
4 1 DDR _CKE2_DIMMB
DDR _CKE3_DIMMB 1 2 3 2 D DR_B_BS2
R120 56_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 16 of 46
5 4 3 2 1
5 4 3 2 1
+3VS +3VS_CK505
FSC FSB FSA CPU SRC PCI REF DOT_96 USB R121
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz 1 2
1 1 1 1 1 1 1
0_0805_5% C199 C200 C201 C202 C203 C204 C205
0 0 0 266 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2
0 0 1 133 100 33.3 14.318 96.0 48.0
Routing the trace at least 10mil + V CCP +1.05VS_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0
CLK_XTAL_OUT
D CLK_XTAL_IN R122
Place close to U51 D
0 1 1 166 100 33.3 14.318 96.0 48.0
1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
Y1 0_0805_5% 1 1 1 1 1 1 1
1 0 0 333 100 33.3 14.318 96.0 48.0 1 2 C206 C207 C208 C209 C210 C211 C212
14.318MHZ_16PF_7A14300083
2 2 2 2 2 2 2
1 0 1 100 100 33.3 14.318 96.0 48.0
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
1 1 0 400 100 33.3 14.318 96.0 48.0 C213 C214
18P_0402_50V8J 18P_0402_50V8J
1 1
1 1 1 Reserved
Vendor suggests 22pF
R123 +3VS_CK505 +1.05VS_CK505
1 2 + V CCP
1
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CLK_CPU_XDP <6>
CL RP1 R_CPU_XDP# R125 1 2 0_0402_5%
CLK_CPU_XDP# <6>
NO S HORT PADS R126 1 2 475_0402_1% R _CLKREQ#_7 R _MCH_3GPLL R127 1 2 0_0402_5%
<9> CLKREQ#_7 CLK_MCH_3GPLL <9>
2
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
R139 U3
1K_0402_5% +3VS_CK505 +1.05VS_CK505
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
CLKREQ_7#
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
VDD_SRC_IO
SRC_7
SRC_7#
VSS_SRC
CLKREQ_6#
SRC_6
SRC_6#
VDD_SRC
C C
2
@ R141 1 2 0_0402_5%
<22,43> VGATE @ R142 1 2 0_0402_5%
+ VCCP <43> CLK_ENABLE# R140 1 2 0_0402_5% R_ CK P WRGD 1 54 H_STP_PCI# 2MiniC@
<22> CK _ P WRGD CKPWRGD/PD# PCI_STOP# H_STP_PCI# <22>
FSB 2 53 H_STP_CPU# 2MiniC@
FS_B/TEST_MODE CPU_STOP# H_STP_CPU# <22>
3 52 2MiniC@
2
USB_1/CLKREQ_A#
PCI_4/SEL_LCDCL SRC_4 CL K _ PCIE_NCARD <26>
0_0402_5% R161 1 2 33_0402_1% ITP_EN 17 38
LCDCLK#/27M_SS
SRC_0#/DOT_96#
<20> CL K _ PCI_ICH PCIF_5/ITP_EN VDD_SRC_IO R_ C LKREQ#_C R162
18 37 1 2 475_0402_1%
SRC_0/DOT_96
CL KREQ#_C <22>
2
VSS_PCI CLKREQ_3#
VDD_PLL3_IO
LCDCLK/27M
USB_0/FS_A
Ne wC@
VDD_PLL3
VSS_PLL3
VSS_SRC
Ne wC@
VDD_48
SRC_2#
SRC_3#
+ VCCP
VDD_IO
VSS_48
VSS_IO
Ne wC@
SRC_2
SRC_3
Change 33M and 48M damping to 39M by EMI request
1
@
R163 SLG8SP553VTR_QFN72_10x10
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1K_0402_5% +3VS_CK505
+3VS
+3VS
0 = SRC8/SRC8#
ITP_EN +3VS
1 = ITP/ITP# R178 R179
0 = Enable DOT96 & SRC1(UMA) 2.2K_0402_5% 2.2K_0402_5%
PCI_CLK3 @ C215 2 1 C LK_48M_ICH
1 = Enable SRC0 & 27MHz(DIS)
2
Q3A 5P_0402_50V8C
@ C216 2 1 C LK_14M_ICH
<22,24,26> ICH_SMBDATA 6 1 CLK_SMBDATA 4.7P_0402_50V8C
+3VS +3VS @ C217 2 1 CL K _ PCI_ICH
5
<BOM Structure>
ITP_EN P CI_CLK3
1
@
R182 R183
10K_0402_5% 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 17 of 46
5 4 3 2 1
A B C D E
BLUE
GR EEN
R ED
Place close to
@ D5 @ D6 @ D7 JCRT1
1
1 +5VS + RCRT_VCC + CRT VDD 1
DAN217T146_SC59-3
DAN217T146_SC59-3
DAN217T146_SC59-3
D4 F1
2 1 1 2 W=40mils
CRT Connector RB491D_SC59-3 1 .1A_6VDC_FUSE
1
3
+ CRTVDD
0.1U_0402_16V4Z
C220 2
J CRT1
6
11
R ED 1
<34> R E D
7
12
GR EEN 2
<34> GREEN
8
<34> D_ HS Y NC 13
BLUE 3
<34> BLUE
9
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14
<34> D_ V S YNC
4 16
+5VS +5VS 10 17
15
C221 C222 5
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 1 2 SUYIN_070546FR015S263ZR
C ONN@
+3VS
+ CRTVDD + CRTVDD +3VS
5
1
U4
SN74AHCT1G125GW_SOT353-5 R184
P
OE#
1
1
2 CRT _ HS YNC HS Y N C_G_A 2
<11> CRT _ HSYNC 2 4 1 2 0_0603_5% D_ HS Y NC
A Y R185 R186 R187 R188
G
5
1
2.2K_0402_5% 2.2K_0402_5%
2
R189 2.2K_0402_5% 2.2K_0402_5%
P
OE#
3
2
2
A Y D_ DD CDATA 3 V DD CDA
6 1 3 V DDCDA <11>
G
U5 1 @ 1 @
SN74AHCT1G125GW_SOT353-5 C223 C224
3
Q5A
5
5P_0402_50V8C 5P_0402_50V8C 2N7002DW-7-F_SOT363-6
2 2 D_ DDC CLK 3 V DD CCL
3 4 3 V DDCCL <11>
Q5B
2N7002DW-7-F_SOT363-6
D_ DDCDATA <34>
D_ DDCCLK <34>
3 3
C_ R ED L2 1 2 R ED
<11> M _ RED
HLC0603CSCCR11JT_0603
C_ GRN L3 1 2 GR EEN
<11> M _GREEN
HLC0603CSCCR11JT_0603
C_ BLU L4 1 2 BLUE
<11> M_BLUE
HLC0603CSCCR11JT_0603
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
1
1
150_0402_1%
150_0402_1%
150_0402_1%
1 1 1 1 1 1
R195
R196
R197
2
2 2 2 2 2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 18 of 46
A B C D E
5 4 3 2 1
680P_0402_50V7K
680P_0402_50V7K
1
1
1
+ L CDVDD +3VS
+ L CDVDD + L CDVDD +5VALW Q7
SI2301BDS-T1-E3_SOT23-3
2
2
2
1
J LVDS1 1 3
S
D
4.7U_0805_10V4Z
1 2 LVDS_A2- R198 1
1 2 LVDS_A2- <11>
3 4 LVDS_A2+ 1 1 100_0402_5% R199
3 4 LVDS_A2+ <11>
5 6 LVDS_A1- C231 C232 1M_0402_5% C233 1
G
LVDS_A1- <11>
2
5 6 LVDS_A1+ 4.7U_0805_10V4Z
7 8 LVDS_A1+ <11>
6 2
2
7 8 LVDS_A0- 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C234
9 10 LVDS_A0- <11>
9 10 LVDS_A0+ 2 2
11 12 LVDS_A0+ <11>
USB20_P4 11 12 LVDS_ACLK- 2
<22> USB20_P4 13 14 LVDS_ACLK- <11>
USB20_N4 13 14 LVDS_ACLK+ R200
<22> USB20_N4 15 16 LVDS_ACLK+ <11>
15 16
17 18 2 2 1
+3VS 17 18
19 20 11/07 Change R727 to 0805 size
19 20 2N7002DW-7-F_SOT363-6 100K_0402_5%
21 22
1
21 22 DM IC_DAT C238
23 24 Q8A
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23 24 DM IC_DAT <28>
25 26 DM I C_CLK
25 26 DM IC_CLK <28> 0.047U_0402_16V7K
27 28 +3V_LOGO R727 1 2 +5VS
27 28 I NV_PWM 470_0805_5%
29 30 INV_PWM <32>
29 30
3
31 32 BKOFF# BKOFF# <32> Limited Current < 1A 01/03 Change to 0.047u to meet T1 timing
31 32 DA C_ BRIG
11/17 Delete LVDS B 33
33 34
34 DA C_ BRIG <32>
Q8B
35 36 +USB_CAM
35 36 DDC2 _CLK 2N7002DW-7-F_SOT363-6
37 38 DDC2 _CLK <11> <11> E NA VDD 5
37 38 DD C2_DATA
39 40
39 40
1
41 42 DDC2_DATA <11>
4
GND GND R201
ACES_88242-4001 100K_0402_5%
C ONN@
C C
2
1 1
C435 C434
680P_0402_50V7K 680P_0402_50V7K Avoid Panel display garbage after power on.
2 2
DM I C_CLK
L6 1 2
DM IC_DAT FBMA-L11-201209-221LMA30T_0805
2
DDC2 _CLK 2 2
DD C2_DATA
0831 EMI request
11/09 EMI reserver
B B
USB Camera
+5VALW +5VS +USB_CAM
1
U42
1
@ PJP6 PJP5
P A D-OPEN 2x2m P A D-OPEN 2x2m 1 5 R1091
IN OUT 215K_0603_1%
2
GND
1
2
3 4 C1391
SHDN BYP
1
1
10U_0805_6.3V6M R1093 2
R440 100K_0402_1%
2 0_0402_5%
2
1
@ R441 1 2 0_0402_5%
<22> GPIO20
A
11/07 Change U42 to 3.9V LDO(Adjustable) A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 19 of 46
5 4 3 2 1
5 4 3 2 1
+3VS
1
+3VS D2 E3 @
AD15 PAR PCI_RST# R280
F10 R1 P CI_RST# <31,32>
AD16 PCIRST# PCI_DEVSEL# 10_0402_5%
D5 C6
R281 1 AD17 DEVSEL#
2 8.2K_0402_5% P C I_PIRQA# D10 E4 P C I_PERR#
AD18 PERR# P CI_PLOCK#
B3 C2
2
R282 1 AD19 PLOCK#
2 8.2K_0402_5% P C I_PIRQB# F7 J4 P C I_SERR#
P CI_SERR# <32>
AD20 SERR# PCI_STOP#
C3 A4 1
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R283 1 AD21 STOP#
2 8.2K_0402_5% P CI_ PIRQC# F3 F5 P CI _TRDY# @
AD22 TRDY# P CI_FRAME# C425
F4 D7
R284 1 AD23 FRAME#
2 8.2K_0402_5% P CI_ PIRQD# C1 8.2P_0402_50V
AD24 PLT_RST# 2
G7 C14 PLT_RST# <9,25,26,27>
R285 1 AD25 PLTRST#
2 8.2K_0402_5% P C I_PIRQE# H7 D4 CL K _ PCI_ICH
CL K _ P CI_ICH <17>
AD26 PCICLK PCI_PME#
D1 R2 PCI_PME# <32>
R286 1 AD27 PME#
2 8.2K_0402_5% P CI _PIRQF# G5
AD28
H6
AD29 3/28 PCI_PME# Remvoe 8.2k pull high +3VALW resistance.
R287 1 2 8.2K_0402_5% P CI _PIRQG# G1
AD30
H3
R288 2 AD31
1 8.2K_0402_5% P CI_ PIRQH#
C C
P C I_PIRQA# J5
Interrupt I/F H4 P C I_PIRQE#
R289 1 PIRQA# PIRQE#/GPIO2
2 8.2K_0402_5% P CI_REQ0# P C I_PIRQB# E1 K6 P CI _PIRQF#
P CI_ PIRQC# PIRQB# PIRQF#/GPIO3 P CI _PIRQG#
J6 F2
R290 1 PIRQC# PIRQG#/GPIO4
2 8.2K_0402_5% P CI_REQ1# P CI_ PIRQD# C4 G2 P CI_ PIRQH# 1 2 A CCEL_INT <24>
PIRQD# PIRQH#/GPIO5 R291 0_0402_5%
R292 1 2 8.2K_0402_5% P CI_REQ2# ICH9-M ES_FCBGA676 GS@
@R294 0 1 SPI
P CI_GNT3# 1 2
1K_0402_5%
1 0 PCI
1 1 LPC *
+3VALW
@ R295
SPI_CS1#_R 1 2
<22> SPI_CS1#_R
1K_0402_5%
@ R296
P CI_GNT0# 1 2
1K_0402_5%
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(1/4)-PCI/INT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 20 of 46
5 4 3 2 1
5 4 3 2 1
1
0_0402_5%
0_0402_5%
D D
1
C426 @ @ + VCCP
R303 R304 ICH_LAN100_SLP Low = Internal VR Disabled
0.1U_0402_16V4Z @ R305
2 High = Internal VR Enabled(Default) H_DPRSTP# 1 2
2
56_0402_5%
L P C_AD[0..3] <26,31,32>
U12A @ R306
I CH_RTCX1 C23 K5 LPC_AD0 H_DPSLP# 1 2
I CH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1 56_0402_5%
C24 K4
R307 RTCX2 FWH1/LAD1 LPC_AD2
L6
ICH _RTCRST# FWH2/LAD2 LPC_AD3
+ RT CVCC 1 2 A25 K2
20K_0402_5% IC H_SRTCRST# RTCRST# FWH3/LAD3
F20
S M _ INTRUDER# SRTCRST# LPC_FRAME#
C22 K3 LPC_FRAME# <26,31,32>
INTRUDER# FWH4/LFRAME# + V CCP
RTC
LPC
1
1
C427 CLRP2 ICH_ INTVRMEN B22 J3
S HORT PADS LAN100_SLP INTVRMEN LDRQ0#
A22 J1
1U_0603_10V4Z LAN100_SLP LDRQ1#/GPIO23 T54 P AD
2
2 GATEA20
E25 N7 GATEA20 <32>
GLAN_CLK A20GATE H_A20M# R308
AJ27
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A20M# H_A20M# <6>
C13 56_0402_5%
LAN_RSTSYNC H _DPRSTP_R# R309 H_DPRSTP#
AJ25 1 2 H_DPRSTP# <7,9,43>
DPRSTP# H_DPSLP# 0_0402_5%
F14 AE23 H_DPSLP# <7>
1
LAN_RXD0 DPSLP#
G13
LAN_RXD1 R_ H_ FERR# R310 H_ F ERR#
D14 AJ26 1 2
LAN / GLAN
LAN_RXD2 FERR# H_ F ERR# <6>
56_0402_5%
D13 AD22 H_ P W R GOOD 3/28 add 56ohm
+1.5VS LAN_TXD_0 CPUPWRGD H_ P W RGOOD <6,7>
D12
R311 LAN_TXD_1 H_ IG NNE#
E13 AF25 H_ IGNNE# <6>
24.9_0402_1% LAN_TXD_2 IGNNE#
within 2" from R379
1 2 G LAN_COMP B10 AE22 H_ INIT#
GPIO56 INIT# H_ INIT# <6> + V CCP
R312 33_0402_5% 1 2 AG25 H_ I NTR
CPU
C <28> HDA _ BITCLK_CODEC INTR H_ INTR <6> C
R313 33_0402_5% 1 2 B28 L3 KB_RST#
<29> HDA_BITCLK_MDC GLAN_COMPI RCIN# KB_RST# <32>
R207 33_0402_5% 1 2 B27
<9> HDA_BITCLK_NB GLAN_COMPO
1
R316 33_0402_5% 1 2 AF23 H_ N MI
<28> HDA _ S Y NC_CODEC NMI H_ NMI <6>
R314 33_0402_5% 1 2 H DA_BITCLK AF6 AF24 H_SMI# R315
<29> HDA _ S Y NC_MDC HDA_BIT_CLK SMI# H_SMI# <6>
R208 33_0402_5% 1 2 HDA _ S YNC AH4 56_0402_5%
<9> HDA _ S YNC_NB HDA_SYNC
R317 33_0402_5% 1 2 AH27 H_STPCLK#
<28,32> HDA _ RST#_CODEC STPCLK# H_STPCLK# <6>
R318 33_0402_5% 1 2 H DARST# AE7
<29> HDA_RST#_MDC
2
R209 33_0402_5% HDA_RST# T HR MTRIP_ICH# R319
<9> HDA_RST#_NB 1 2 AG26 1 2 54.9_0402_1% H_THERMTRIP# <6,9>
HDA _ SDIN0 THRMTRIP#
<28> HDA _ SDIN0 AF4
HDA _ SDIN1 HDA_SDIN0
<29> HDA _ SDIN1 AG4
HDA_SDIN1 TP12
AG27 placed within 2"
HDA _ SDIN2 AH3
<9> HDA _ SDIN2 HDA_SDIN2 from ICH9M
AE5
IHDA
R320 33_0402_5% HDA_SDIN3
<29> HDA _ SDOUT_MDC 1 2 AH11 SATA_RXN4_C <24>
R321 33_0402_5% HDA _SDOUT SATA4RXN 0.01U_0402_50V7K
<28> HDA _ S DOUT_CODEC 1 2 AG5 AJ11 SATA_RXP4_C <24>
R204 33_0402_5% HDA_SDOUT SATA4RXP SATA_TXN4_C
<9> HDA _SDOUT_NB 1 2 AG12 2 1 C428 SATA_TXN4
SATA_TXN4 <24> ODD
SATA4TXN SATA_TXP4_C
P AD T55 AG7 AF12 2 1 C429 SATA_TXP4
SATA_TXP4 <24>
HDA_DOCK_EN#/GPIO33 SATA4TXP
P AD T56 AE8
HDA_DOCK_RST#/GPIO34 0.01U_0402_50V7K
SATA_LED# AG8
<33> SATA_LED# SATALED#
AH9 SATA_RXN5_C <30>
SATA5RXN 0.01U_0402_50V7K
<24> SATA_RXN0_C AJ16 AJ9 SATA_RXP5_C <30> e-SATA
0.01U_0402_50V7K SATA0RXN SATA5RXP SATA_TXN5_C
<24> SATA_RXP0_C AH16 AE10 2 1 C430 SATA_TXN5
SATA_TXN5 <30>
SATA_TXN0 C431 SATA_TXN0_C SATA0RXP SATA5TXN SATA_TXP5_C
1 2 AF17 AF10 2 1 C432 SATA_TXP5 De-feature disable
P- HDD <24>
<24>
SATA_TXN0
SATA_TXP0
SATA_TXP0 C433 1 2 SATA_TXP0_C AG17
SATA0TXN SATA5TXP ESATA@ 0.01U_0402_50V7K
SATA_TXP5 <30>
SATA0TXP CLK_PCIE_SATA# ESATA@
AH18 CLK_PCIE_SATA# <17>
SATA_CLKN
SATA
0.01U_0402_50V7K AH13 AJ18 CLK_PCIE_SATA
<24> SATA_RXN1_C SATA1RXN SATA_CLKP CLK_PCIE_SATA <17>
0.01U_0402_50V7K AJ13 AJ7
<24> SATA_RXP1_C SATA1RXP SATARBIAS#
SATA_TXN1 C820 1 2 Multi@ SATA_TXN1_C AG14 AH7 R322 1 2
<24> SATA_TXN1 SATA1TXN SATARBIAS
SATA_TXP1 C821 1 2 Multi@ SATA_TXP1_C AF14 24.9_0402_1%
<24> SATA_TXP1 SATA1TXP
0.01U_0402_50V7K Within 500 mils
ICH9-M ES_FCBGA676
B B
@ R325
1 2 HDA _ S DOUT_CODEC
1K_0402_5%
I CH_RTCX1 @ D8
R327 R329 W=20mils 2
R328 10_0402_5% 1 2 1 R330 JBATT1
1 2 I CH_RTCX2 W=20mils 3 1 2 1
0_0402_5% W=20mils 1
W=20mils 2
2
0 1 Y2
1 4
1 0 2 3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(2/4)_LAN,HD,IDE,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 21 of 46
5 4 3 2 1
5 4 3 2 1
SATA
GPIO
E17 AE21
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36
1
1 2 P M _CLKRUN# ME_EC_CLK1 C17 AD20 GPIO37
R334 8.2K_0402_5% ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37 @ R342 @ R343
B18
O CP# SMLINK1 C LK_14M_ICH
1 2 H1 CLK_14M_ICH <17>
R335 10K_0402_5% +3VS ICH_ R I# CLK14 C LK_48M_ICH 10_0402_5% 10_0402_5%
F19 clocks AF3 CLK_48M_ICH <17>
T HERM_SCI# RI# CLK48
1 2
2
@ R336 8.2K_0402_5% P AD T57 SUS_STAT# R4 P1 ICH_ SUSCLK T58 P AD
CL KREQ#_C XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK
1 2 <6> XDP_DBRESET# G19 1 1
1
@ R337 10K_0402_5% SYS_RESET# SLP_S3# @ C440 @ C441
C16 SLP_S3# <32>
D PM_BMBUSY# @ R339 @ R340 PM_BMBUSY# SLP_S3# SLP_S4# D
1 2 <9> PM_BMBUSY# M6 E16 SLP_S4# <32>
@ R338 8.2K_0402_5% 10K_0402_5% 10K_0402_5% PMSYNC#/GPIO0 SLP_S4# SLP_S5# 4.7P_0402_50V8C 4.7P_0402_50V8C
G17
SYS / GPIO
SLP_S5# SLP_S5# <32> 2 2
1 2 E C _SCI# <32> E C_LID_OUT# E C_LID_OUT# A17
R341 8.2K_0402_5% SMBALERT#/GPIO11 S4_STATE#
C10
2
CR _CPPE# H_STP_PCI# S4_STATE#/GPIO26
1 2 <17> H_STP_PCI# A14
R344 8.2K_0402_5% R345 STP_PCI#
<17> H_STP_CPU# 1 2 0_0402_5% R_STP_CPU# E19 G20 PM_PWROK
PM_PWROK <9,32>
R346 10K_0402_5%
C R_WAKE# STP_CPU# PWROK
1 2 1 2
R356 8.2K_0402_5% P M _CLKRUN# L4 M2 R348 1 2 0_0402_5%
Power MGT
CLKRUN# DPRSLPVR/GPIO16 DP RSLPVR <9,43>
1 2 GPIO18
R349 8.2K_0402_5% IC H_PCIE_WAKE# E20 B13 ICH_LOW_BAT#
<25,26> ICH_PCIE_WAKE# WAKE# BATLOW#
1 2 HD DHALT_LED# S I RQ M5
<32> S IRQ SERIRQ
R350 8.2K_0402_5% T HERM_SCI# AJ23 R3 PWRBTN_OUT# 11/17 Add +3VALW GD to EC_RSMRST#
<32> T HERM_SCI# THRM# PWRBTN# PWRBTN_OUT# <32>
1 2 GPIO20
R351 8.2K_0402_5%
<17,43> VGATE
VGATE D21 D20 R_EC_RSMRST# <39>
to fix Battery mode can't boot issue
GPIO21 VRMPWRGD LAN_RST#
1 2
R352 8.2K_0402_5% R353 1 2 P AD T59 A20 D22 R_EC_RSMRST# R354 1 2 100_0402_5%
TP11 RSMRST# EC_RSMRST# <32>
1 2 GPIO36 100K_0402_5% R355 1 2 10K_0402_5%
R357 8.2K_0402_5% <6> OCP# O CP# AG19 R5 CK _ P WRGD
GPIO1 CK_PWRGD CK _ P WRGD <17>
1 2 GPIO37 <27> CR_CPPE# CR _CPPE# AH21
R358 8.2K_0402_5% R225 EC_SCI#_SB GPIO6 M _PWROK
1 2 0_0402_5% AG21 R6
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<32> E C_SCI# GPIO7 CLPWROK M _PWROK <9,32>
1 2 GPIO39 <32> EC_SMI# EC_SMI# A21
R359 10K_0402_5% @ R226 0_0402_5% E C_SCI#_GPIO12 GPIO8 +3VS
1 2 C12 B16
GPIO48 GPIO12 SLP_M#
1 2 P AD T46 C21
R361 8.2K_0402_5% 17/14 GPIO13 C L_CLK0 R360
AE18 F24 CL_CLK0 <9>
GPIO57 GPIO18 GPIO17 CL_CLK0
1 2 K1 B19 1 2
GPIO
Controller Link
GPIO18 CL_CLK1
0.1U_0402_16V4Z
R362 8.2K_0402_5% GPIO20 AF8
<19> GPIO20 GPIO20
1
C R_WAKE# AJ22 F22 CL_DATA0 3.24K_0402_1%
<27> CR_WAKE# SCLOCK/GPIO22 CL_DATA0 CL_DATA0 <9>
DIS /UMA A9 C19 1
GPIO27 CL_DATA1 C442 R363
P AD T47 D19
CL KREQ#_C GPIO28 CL _ VREF0_ICH 453_0402_1%
<17> CL KREQ#_C L1 C25
GPIO38 SATACLKREQ#/GPIO35 CL_VREF0 CL _ VREF1_ICH
+3VS 1 2 AE19 A19
2
GPIO49 R364 8.2K_0402_5% GPIO39 SLOAD/GPIO38 CL_VREF1 2 NA lead free
1 2 AG22
C @ R365 10K_0402_5% R739 1 GPIO48 SDATAOUT0/GPIO39 CL_RST# +3VALW C
<26> EXP_CPPE# 2 AF21 F21 CL_RST# <9>
0_0402_5% GPIO49 SDATAOUT1/GPIO48 CL_RST0#
AH24 D18
GPIO57 GPIO49 CL_RST1# R367
A8
@ R366 1 GPIO57/CLGPIO5
+3VS 2 1K_0402_5% A16 XMIT_OFF
XMIT_OFF <26> 1 2
MEM_LED/GPIO24
0.1U_0402_16V4Z
SB_SPKR M7 C18 GPIO10
<28> SB_SPKR SPKR GPIO10/SUS_PWR_ACK
M CH_ ICH _SYNC# AJ24 C11 GPIO14 3.24K_0402_1%
MISC
<9> M CH_ ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
1
+3VALW ICH_ R SVD B21 C20 L AN_WOL_EN
<21> ICH_ RSVD TP3 WOL_EN/GPIO9 1
AH20 C443 R368
TP8 R370 453_0402_1%
AJ20
LINKALERT# TP9
1 2 R366 AJ21
TP10
2 1 +3VALW 2
R369 10K_0402_5% Low -->default
2
1 2 ICH_LOW_BAT# High -->No boot ICH9-M ES_FCBGA676 100K_0402_5%
R371 8.2K_0402_5%
1 2 IC H_PCIE_WAKE# U1 2D
R372 1K_0402_5% PCIE_RXN1 N29 V27 D MI_RXN0 DMI_RXN0 <9>
<26> PCIE_RXN1 PERN1 DMI0RXN
1 2 ICH_ R I# PCIE_RXP1 N28 V26 DMI_RXP0 DMI_RXP0 <9>
<26> PCIE_RXP1 PERP1 DMI0RXP
R374 10K_0402_5% TV Tuner <26> PCIE_TXN1 C445 1 2 0.1U_0402_16V4Z PCIE_C_TXN1 P27 U29 DMI_TXN0 DMI_TXN0 <9>
PCI - Express
R378 10K_0402_5% PCIE_RXN3 J29 AB27 D MI_RXN2 DMI_RXN2 <9>
<26> PCIE_RXN3 PERN3 DMI2RXN
1 2 GPIO10 PCIE_RXP3 J28 AB26 DMI_RXP2 DMI_RXP2 <9>
<26> PCIE_RXP3 PERP3 DMI2RXP
R379 10K_0402_5% WLAN <26> PCIE_TXN3 C448 1 2 0.1U_0402_16V4Z PCIE_C_TXN3 K27 AA29 DMI_TXN2 DMI_TXN2 <9>
E C_LID_OUT# PETN3 DMI2TXN
1 2 <26> PCIE_TXP3 C449 1 2 0.1U_0402_16V4Z PCIE_C_TXP3 K26 AA28 DMI_TXP2 DMI_TXP2 <9>
R373 10K_0402_5% PETP3 DMI2TXP
1 2 EC_SMI# G LAN_RXN G29 AD27 D MI_RXN3 DMI_RXN3 <9>
<25> GLAN_RXN PERN4 DMI3RXN
R380 8.2K_0402_5% GLAN_RXP G28 AD26 DMI_RXP3 DMI_RXP3 <9>
<25> GLAN_RXP PERP4 DMI3RXP
1 2 GPIO14 LAN <25> GLAN_TXN C452 1 2 0.1U_0402_16V4Z GLAN_TXN_C H27 AC29 DMI_TXN3 DMI_TXN3 <9>
B R381 8.2K_0402_5% C453 1 0.1U_0402_16V4Z GLAN_TXP_C PETN4 DMI3TXN DMI_TXP3 B
<25> GLAN_TXP 2 H26 AC28 DMI_TXP3 <9>
PETP4 DMI3TXP
PCIE_RXN5 E29 T26 CL K _PCIE_ICH#
<27> PCIE_RXN5 PERN5 DMI_CLKN CL K _PCIE_ICH# <17>
PCIE_RXP5 E28 T25 CL K _ PCIE_ICH
+3VS +3VS <27> PCIE_RXP5 PERP5 DMI_CLKP CL K _ PCIE_ICH <17>
Board ID Card Reader <27> PCIE_TXN5 C816 1 2 0.1U_0402_16V4Z PCIE_C_TXN5 F27
PETN5
<27> PCIE_TXP5 C817 1 2 0.1U_0402_16V4Z PCIE_C_TXP5 F26 AF29 R382 24.9_0402_1% Within 500 mils
PETP5 DMI_ZCOMP DM I_ IRCOMP
AF28 1 2 +1.5VS
DMI_IRCOMP
2
PCIE_RXN4 C29
<26> PCIE_RXN4 PERN6/GLAN_RXN
PCIE_RXP4 C28 AC5 USB20_N0
<26> PCIE_RXP4 PERP6/GLAN_RXP USBP0N USB20_N0 <30>
@ R745 @ R747 New Card <26> PCIE_TXN4 C450 1 2 0.1U_0402_16V4Z PCIE_C_TXN4 D27 AC4 USB20_P0 USB-0 Right side
PETN6/GLAN_TXN USBP0P USB20_P0 <30>
10K_0402_5% 10K_0402_5% <26> PCIE_TXP4 C451 1 2 0.1U_0402_16V4Z PCIE_C_TXP4 D26 AD3 USB20_N1
PETP6/GLAN_TXP USBP1N USB20_N1 <30>
Ne wC@ AD2 USB20_P1 USB-1 Right side
USB20_P1 <30>
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
B15 AA3 J26
ICH_ V 5 REF_RUN VCC1_05[02] 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[003] VSS[109]
1 1 A6
V5REF
2mA VCC1_05[03]
C15 AA6
VSS[004] VSS[110]
J27
C462
C454
D15 1 1 AB1 AC22
VCC1_05[04] C457 C455 VSS[005] VSS[111]
E15 AA23 K28
ICH _V5REF_SUS VCC1_05[05] VSS[006] VSS[112]
AE1 2mA F15 AB28 K29
2 2 V5REF_SUS VCC1_05[06] VSS[007] VSS[113]
L11 AB29 L13
VCC1_05[07] 2 2 VSS[008] VSS[114]
AA24 646mA L12 AB4 L15
VCC1_5_B[01] VCC1_05[08] VSS[009] VSS[115]
AA25 L14 AB5 L2
VCC1_5_B[02] VCC1_05[09] VSS[010] VSS[116]
AB24 L16 AC17 L26
VCC1_5_B[03] VCC1_05[10] VSS[011] VSS[117]
AB25 L17 AC26 L27
R387 VCC1_5_B[04] VCC1_05[11] VSS[012] VSS[118]
AC24 L18 AC27 L5
10U_0805_10V4Z VCC1_5_B[05] VCC1_05[12] R385 VSS[013] VSS[119]
+1.5VS 1 2 40 mils AC25
VCC1_5_B[06] VCC1_05[13]
M11 AC3
VSS[014] VSS[120]
L7
D CHB1608U301_0603 AD24 M18 0.01U_0402_16V7K 1 2 AD1 M12 D
1 VCC1_5_B[07] VCC1_05[14] +1.5VS VSS[015] VSS[121]
CHB1608U301_0603
CORE
1 1 1 AD25 P11 AD10 M13
VCC1_5_B[08] VCC1_05[15] VSS[016] VSS[122]
220U_D2_4VM
+ C459 C460 C456 AE25 P18 1 1 AD12 M14
VCC1_5_B[09] VCC1_05[16] VSS[017] VSS[123]
C458
AE26 T11 C461 C463 AD13 M15
VCC1_5_B[10] VCC1_05[17] VSS[018] VSS[124]
AE27 T18 AD14 M16
2 2 2 2 VCC1_5_B[11] VCC1_05[18] 10U_0805_10V4Z VSS[019] VSS[125]
AE28 U11 AD17 M17
VCC1_5_B[12] VCC1_05[19] 2 2 VSS[020] VSS[126]
AE29 U18 AD18 M23
+5VS +3VS 10U_0805_10V4Z 2.2U_0603_6.3V4Z VCC1_5_B[13] VCC1_05[20] VSS[021] VSS[127]
F25 V11 AD21 M28
VCC1_5_B[14] VCC1_05[21] VSS[022] VSS[128]
G25 V12 AD28 M29
VCC1_5_B[15] VCC1_05[22] VSS[023] VSS[129]
H24 V14 AD29 N11
VCC1_5_B[16] VCC1_05[23] VSS[024] VSS[130]
1
VCCA3GP
22U_0805_6.3VAM
J25 V18 AD6 N14
100_0402_5% CH751H-40_SC76 VCC1_5_B[19] VCC1_05[26] VSS[027] VSS[133]
K24 1 AD7 N15
VCC1_5_B[20] C464 VSS[028] VSS[134]
K25 AD9 N16
2
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0.1U_0402_10V6K VCC1_5_B[26] VCC_DMI[2] VSS[034] VSS[140]
N23 AE2 P13
2 VCC1_5_B[27] VSS[035] VSS[141]
N24 AB23 AE20 P14
VCC1_5_B[28]
N25 48mA V_CPU_IO[1] AC23 AE24
VSS[036] VSS[142]
P15
VCC1_5_B[29] V_CPU_IO[2] VSS[037] VSS[143]
4.7U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P24 AE3 P16
VCC1_5_B[30] +3VS VSS[038] VSS[144]
P25 AG29 1 1 1 AE4 P17
+5VALW +3VALW VCC1_5_B[31] VCC3_3[01] VSS[039] VSS[145]
C466
C467
C468
R24 2mA AJ6 AE6 P2
VCC1_5_B[32] VCC3_3[02] VSS[040] VSS[146]
R25 AC10 AE9 P23
VCC1_5_B[33] VCC3_3[07] VSS[041] VSS[147]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R26 AF13 P28
VCC1_5_B[34] VSS[042] VSS[148]
1
2 2 2
R27 AD19 1 1 1 AF16 P29
R388 D10 VCC1_5_B[35] VCC3_3[03] VSS[043] VSS[149]
VCCP_CORE
T24 AF20 AF18 P4
VCC1_5_B[36] VCC3_3[04] VSS[044] VSS[150]
C469
C470
C471
T27 AG24 AF22 P7
10_0402_5% CH751H-40_SC76 VCC1_5_B[37] VCC3_3[05] VSS[045] VSS[151]
T28 AC20 AH26 R11
C VCC1_5_B[38] VCC3_3[06] +3VS 2 2 2 VSS[046] VSS[152] C
T29 (DMI) AF26 R12
2
PCI
VCC1_5_B[44] VCC3_3[11] VSS[052] VSS[158]
2
0.1U_0402_10V6K W24 J2 AG16 R18
2 VCC1_5_B[45] VCC3_3[12] 2 R212 @ VSS[053] VSS[159]
W25 J7 AG18 R28
VCC1_5_B[46] VCC3_3[13] VSS[054] VSS[160]
K23 K7 0_0402_5% AG20 T12
VCC1_5_B[47] VCC3_3[14] VSS[055] VSS[161]
Y24 AG23 T13
VCC1_5_B[48] VSS[056] VSS[162]
Y25 AG3 T14
1
VCC1_5_B[49] 0.1U_0402_16V4Z VSS[057] VSS[163]
47mA 11mA
VCCHDA
AJ4 +1.5VS AG6
VSS[058] VSS[164]
T15
R740 1 AG9 T16
R389 0.1U_0402_16V4Z VSS[059] VSS[165]
11mA AJ3 1 2 180_0402_1% +3VALW C474 AH12 T17
VCCSUSHDA VSS[060] VSS[166]
+1.5VS 1 2 AJ19 1 AH14 T23
VCCSATAPLL VSS[061] VSS[167]
1
1U_0603_10V4Z
C477
2
C478 VCC1_5_A[03] VSS[066] VSS[172]
AE15 AD8 V CC SUS1_5_ICH_1 AH28 U16
2 2 VCC1_5_A[04] VCCSUS1_5[1] T67 VSS[067] VSS[173]
ARX
0.1U_0402_16V4Z
AC11 212mA D16 1 1 AJ8 V1
VCCPSUS
C479
C480
AE11 E22 B14 V15
+1.5VS VCC1_5_A[11] VCCSUS3_3[04] VSS[075] VSS[181]
AF11 B17 V23
VCC1_5_A[12] 2 2 VSS[076] VSS[182]
ATX
1 AG10 B2 V28
C481 VCC1_5_A[13] VSS[077] VSS[183]
AG11 B20 V29
B VCC1_5_A[14] VSS[078] VSS[184] B
AH10 B23 V4
1U_0603_10V4Z VCC1_5_A[15] VSS[079] VSS[185]
AJ10 AF1 B5 V5
2 VCC1_5_A[16] VCCSUS3_3[05] VSS[080] VSS[186]
B8 W26
VSS[081] VSS[187]
AC9 1342mA
VCC1_5_A[17]
C26
VSS[082] VSS[188]
W27
C27 W3
VSS[083] VSS[189]
AC18 E11 Y1
VCC1_5_A[18] VSS[084] VSS[190]
AC19 E14 Y28
VCC1_5_A[19] VSS[085] VSS[191]
T1 E18 Y29
VCCSUS3_3[06] VSS[086] VSS[192]
AC21 T2 E2 Y4
VCC1_5_A[20] VCCSUS3_3[07] VSS[087] VSS[193]
T3 E21 Y5
VCCSUS3_3[08] +3VALW VSS[088] VSS[194]
+1.5VS G10 T4 E24 AG28
VCC1_5_A[21] VCCSUS3_3[09] VSS[089] VSS[195]
G9 T5 E5 AH6
VCC1_5_A[22] VCCSUS3_3[10] VSS[090] VSS[196]
1 11mA 11mA T6 E8 AF2
C483 VCCSUS3_3[11] VSS[091] VSS[197]
VCCPUSB
1 23mA
VCCCL3_3[1]
A24 +3VS 1 @
C485 R390 CHB1608U301_0603 B24 C486 ICH9-M ES_FCBGA676
VCCCL3_3[2]
GLAN POWER
A 1 2 A27 1U_0603_10V4Z A
R391 4.7U_0805_10V4Z VCCGLANPLL
+1.5VS 80mA
2 2
10U_0805_10V4Z
2.2U_0603_6.3V4Z
+1.5VS 1 2 D28
VCCGLAN1_5[1]
D29
CHB1608U301_0603 VCCGLAN1_5[2]
1 1 E26
C487 C488 VCCGLAN1_5[3]
1 E27
VCCGLAN1_5[4]
1mA
A26
2 2
0316 change design
C489
2
+3VS VCCGLAN3_3
ICH9-M ES_FCBGA676
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/03/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH9(4/4)_POWER&GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 23 of 46
5 4 3 2 1
5 4 3 2 1
+3VS_ACL
Pleace near HDD CONN (JP3)
HDD Connector +5VS
ACCELEROMETER (ST)
10U_0805_6.3V6M
0.1U_0402_16V4Z
C713
C714
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
J P3 1 1 1 1 1 1
+3VS +3VS_ACL +3VS_ACL_IO
C490
C491 C492 C493
1
GND SATA_TXP0 GS@ D23 GS@ R564
2 SATA_TXP0 <21>
A+ 2 2 2 2 2 2
GS@
GS@
3 SATA_TXN0 0_0603_5%
A- SATA_TXN0 <21>
4 0.01U_0402_16V7K 2 1 1 2
D GND SATA_RXN0 D
5 2 1 C494 SATA_RXN0_C SATA_RXN0_C <21>
B- SATA_RXP0
6 2 1 C495 SATA_RXP0_C SATA_RXP0_C <21>
CH751H-40PT_SOD323-2
B+ 0.01U_0402_16V7K
7
GND
Near CONN side.
8
V33 + 3VS_HDD1
9
V33
10 Pleace near HDD CONN
V33
11
GND + 3VS_HDD1 IC H_SMBCLK
12 ICH_SMBCLK <17,22,26>
GND @ R392
13
GND
14
14 +3VS 1 2 0011101b
V5
0.1U_0402_16V4Z
1U_0603_10V4Z
1000P_0402_50V7K
15 +5VS 0_0805_5% U29 GS@
V5
16
VDDIO absolute man
1 1 1
SCL / SPC
V5
GND
17 @ C496 @ C497 @ C498 rating is VDD+0.1
18
Reserved
19
GND 2 2 2 ICH_SMBDATA
20 +3VS_ACL_IO 1 13 ICH_SMBDATA <17,22,26>
V12 Vdd_IO SDA / SDI / SDO
21
V12 GS@ R568 R570 GS@
22 2 12
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V12 0_0402_5% GND SDO 0_0402_5%
1 2 3 11 1 2
SUYIN_127072FR022G523_RV Reserved Reserved
C ONN@ 4 10
GND GND
5 9
GND INT 2
+3VS_ACL 6 8 A CCEL_INT <20>
Vdd INT 1
C
CD-ROM Connector C
CS
LIS302DLTR_LGA14_3x5
7
+5VS 2 1
GS@ R569 10K_0402_5%
J P5
Placea caps. near ODD CONN. M ust be placed in the center of the system.
13
GND SATA_TXP4
12 SATA_TXP4 <21>
A+ SATA_TXN4
11 SATA_TXN4 <21>
A-
0.1U_0402_16V4Z
1U_0603_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
10 0.01U_0402_16V7K
GND SATA_RXN4
9 2 1 C510 SATA_RXN4_C SATA_RXN4_C <21> 1 1 1 1
B- SATA_RXP4
8 2 1 C511 SATA_RXP4_C SATA_RXP4_C <21>
C512 C513 C514 C515
B+ 0.01U_0402_16V7K
7
GND
Near CONN side. 2 2 2 2
6
DP
5
V5
V5
MD
4
3
+5VS ACCELEROMETER (Bosch)
2
GND
1
GND
SUYIN_127382FR013GX09ZR
C ONN@
B B
U14 @
BMA150
Multi Bay A CCEL_INT 4
INT
VDDIO
VDD
9
2
+3VS_ACL_IO
+3VS_ACL
+3VS_ACL 1 2 G _CS# 5 3
@ R571 10K_0402_5% CSB GND
+5VS ICH_SMBDATA 6 1
+5VS SCK RSVD
JP12
Placea caps. near Multi Bay CONN. RSVD
10
7
SDO
16 1
VCC5 GND SATA_TXP1 IC H_SMBCLK
15 2 SATA_TXP1 <21> 8 11
VCC5 TX+ SATA_TXN1 SDI RSVD
14 3 SATA_TXN1 <21> 12
VCC5 TX- RSVD
13 4
VCC3 GND
0.1U_0402_16V4Z
1U_0603_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
PCB-MB MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 24 of 46
5 4 3 2 1
5 4 3 2 1
LAN Conn.
J RJ45
Place Close to Chip +3V_LAN 13
U44 Yellow LED+
LAN_ACTIVITY# R697 2 1 300_0402_5% 14
C240 2 Yellow LED-
<22> GLAN_RXP 1 0.1U_0402_16V7K PCIE_PTX_IRX_P2 20 33 L A N_DO 1 16
HSOP LED3/EEDO L A N_DI SHLD1
34 8
D C241 2 LED2/EEDI/AUX PR4- D
<22> GLAN_RXN 1 0.1U_0402_16V7K PCIE_PTX_IRX_N2 21 35 LAN_SK_LAN_LINK# C268 9
HSON LED1/EESK L AN_CS @ 68P_0402_50V8K DETECT PIN1
32 7
EECS 2 PR4+
<22> GLAN_TXP 15
HSIP LAN_ACTIVITY# RJ 45_MIDI1-
38 6
LED0 PR2-
<22> GLAN_TXN 16
HSIN L AN_MDI0+
RTL8102EL MDIP0
2 5
PR3-
<17> CLK_PCIE_LAN 17 3 L AN_MDI0-
REFCLK_P MDIN0 L AN_MDI1+
<17> CLK_PCIE_LAN# 18 5 4
REFCLK_M MDIP1 L AN_MDI1- PR3+
6
MDIN1 RJ 45_MIDI1+
<17> CLKREQ#_9 25 8 3
CLKREQB NC PR2+
9
NC RJ 45_MIDI0-
<9,20,26,27> PLT_RST# 27 11 2
PERSTB NC PR1-
12 10
NC RJ 45_MIDI0+ DETCET PIN2
2 1
R688 1 PR1+
2 2.49K_0402_1% 46 4 15
RSET NC @ C269 SHLD1
+3V_LAN 11
VCTRL12 68P_0402_50V8K Green LED+
<22,26> ICH_PCIE_WAKE# 26 48
ISOLATEB LANWAKEB VCTRL12A LAN_SK_LAN_LINK# 1 R698
28 2 1 300_0402_5% 12
ISOLATEB Green LED-
19 + EVDD12
LAN_X1 VDDTX FOX_JM36113-P1122-7F
41 30
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+3VS CKXTAL1 DVDD12 + LAN_VDD12
LAN_X2 42 36 C ONN@
CKXTAL2 DVDD12
13
DVDD12 L A NG ND
10
DVDD12
1
1 1
R215 39 C271 C272
1K_0402_1% NC
23 44 0.1U_0402_16V4Z 4.7U_0805_10V4Z
NC NC 2 2
Check?? 24 45 + LAN_VDD12
2
ISOLATEB NC VCTRL12D
7 29 +3V_LAN
GND VDD33
14 37
GND VDD33
31
C R216 GND C
47 1
15K_0402_5% GND AVDD33
40
NC
22 43
GNDTX NC
RTL8102EL-GR_LQFP48_7X7
3 1 1000P_1206_2KV7K
D
+3V_LAN 2
LEF8423A-R
2
@
G
2
C255 Q19
SI2301BDS-T1-E3_SOT23-3
1
<32> L A N_POWER_OFF 1 2
R218 10K_0402_5% 0.1U_0402_16V4Z
1 2 +3V_LAN
R695 3.6K_0402_5%
B B
U45
L A N_DO 4 5 2
L A N_DI DO GND C256
3 6
+ LAN_VDD12 +3V_LAN LAN_SK_LAN_LINK# DI NC 0.1U_0402_16V4Z
Close to Pin10,13,30,36 Close to Pin1,37,29 2 7
L AN_CS SK NC
1 8 +3V_LAN
CS VCC 1
AT93C46-10SI-2.7_SO8
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 1
C249 C250 C251 C252 C253 C254 C261 R696 10K_0402_5%
1 1 1 1 1 1 1
Y3
0.1U_0402_16V4Z
Y_KDS_1BX25000CK1A_2P to
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
10U_0805_10V4Z
@ 1 2 27P_0402_50V8J
@ C262 C263 2 27P_0402_50V8J 2
2 2 2 1 Y_6X25000017_2P
C266 C267 C264 C265
A 2 1 A
1 1 1 2
Mini Card 0--TV tuner/WWAN/Robson SIM card Connector Mini Card 2---WLAN
+3VS_WLAN +3VALW +1.5VS_WLAN
+3VALW + 3VS_WWAN
0.1U_0402_16V4Z 0.01U_0402_16V7K 4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.01U_0402_16V7K 4.7U_0805_10V4Z JP4 1
1 1 1 C568 1 1 1 +1.5VS R431 1 2 0_0805_5% +1.5VS_WLAN
UIM _PWR 1 C566 C567 C569 C570 C571
2
2
0.1U_0402_16V4Z
1 1 1 1 UIM_DATA 3
C572 C573 C574 C575 UI M_CLK 3 2
4
2MiniC@ 2MiniC@ 2MiniC@ 2MiniC@ U IM_RST 4 2 2 2 2 2 R432 1 0_0805_5%
5 +3VS 2 +3VS_WLAN
1 UIM_VPP 5 4.7U_0805_10V4Z 1
6 8
2 2 2 2 6 G1 0.1U_0402_16V4Z
7 9
7 G2
0.1U_0402_16V4Z ACES_88266-07001
+ 3VS_WWAN C ONN@
J P6
IC H_PCIE_WAKE# 1 2 J P7
C H_DATA 1 2 IC H_PCIE_WAKE#
3 4 1 2 +3VS_WLAN
CH_ CLK 3 4 C H_DATA 1 2
5 6 +1.5VS_WLAN <30> CH_DATA 3 4
CLKREQ#_10 5 6 UIM _PWR CH_ CLK 3 4
<17> CLKREQ#_10 7 8 <30> CH_ CLK 5 6 +1.5VS_WLAN
7 8 UIM_DATA CLKREQ#_6 5 6 R699 0_0402_5% DE BUG@
9 10 <17> CLKREQ#_6 7 8 1 2 LPC_FRAME# <21,31,32>
9 10 UI M_CLK 7 8 R700 0_0402_5% DE BUG@
<17> CLK_PCIE_MCARD0# 11 12 9 10 1 2 LPC_AD3 <21,31,32>
11 12 U IM_RST CL K_PCIE_MCARD2# 9 10 R701 0_0402_5% DE BUG@
<17> CL K_PCIE_MCARD0 13 14 <17> CLK_PCIE_MCARD2# 11 12 1 2 LPC_AD2 <21,31,32>
13 14 UIM_VPP CL K_PCIE_MCARD2 11 12 R702 0_0402_5% DE BUG@
15 16 <17> CL K_PCIE_MCARD2 13 14 1 2 LPC_AD1 <21,31,32>
15 16 13 14 R703 0_0402_5% DE BUG@
17 18 15 16 1 2 LPC_AD0 <21,31,32>
2MiniC@ 17 18 M_WXMIT_OFF# PLT_RST# 15 16
19 20 17 18
2MiniC@ 0_0402_5% 19 20 PLT_RST# 17 18 XMIT_OFF#
21 22 <17> CLK_DEBUG_PORT_1 19 20
R419 1 21 22 19 20
<22> PCIE_RXN1 2 P CIE_C_RXN1 23 24 @R420 1 2 0_0402_5% +3VALW 21 22 PLT_RST#
23 24 21 22
1 2 PCIE_C_RXP1 25 26 R422 1 2 0_0402_5% R423 1 2 0_0402_5% P CIE_C_RXN3 23 24 R424 1 2 0_0402_5%
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<22> PCIE_RXP1 25 26 + 3VS_WWAN <22> PCIE_RXN3 23 24 +3VALW
R421 0_0402_5% 27 28 2MiniC@ +1.5VS_WLAN <22> PCIE_RXP3 R425 1 2 0_0402_5% PCIE_C_RXP3 25 26 @ R426 1 2 0_0402_5% +3VS_WLAN
27 28 IC H_SMBCLK 25 26
29 30 27 28 +1.5VS_WLAN
PCIE_TXN1 29 30 ICH_SMBDATA 27 28 IC H_SMBCLK
<22> PCIE_TXN1 31 32 29 30
PCIE_TXP1 31 32 PCIE_TXN3 29 30 ICH_SMBDATA
<22> PCIE_TXP1 33 34 <22> PCIE_TXN3 31 32
33 34 PCIE_TXP3 31 32
35 36 USB20_N8 <22> <22> PCIE_TXP3 33 34
R427 0_0603_5% 35 36 33 34
37 38 USB20_P8 <22> 35 36 USB20_N5 <22>
37 38 35 36
+3VS_WWAN 1 2 39 40 37 38 USB20_P5 <22>
39 40 37 38
1 2 41 42 W W _LED# <33> 39 40
R428 0_0603_5% 41 42 39 40
43 44 +3VS_WLAN 41 42
2MiniC@ 43 44 41 42
45 46 43 44 WL_LED# <33>
2MiniC@ 45 46 43 44
47 48 +1.5VS_WLAN 45 46
47 48 45 46
49 50 11/17 Reserve UIM_DATA 47 48 +1.5VS_WLAN
2 49 50 47 48 2
51 52 + 3VS_WWAN 49 50
51 52 PU to UIM_PWR 49 50
51 52 +3VS_WLAN
51 52
53 54
GND1 GND2
53 54
@ R750 GND1 GND2 +3VALW
FOX_AS0B226-S40N-7F UIM _PWR 1 2 UIM_DATA
C ONN@ 47K_0402_5% FOX_AS0B226-S40N-7F
C ONN@
1
@
+3VS_WWAN +3VALW @ R433 R434
10K_0402_5% 100K_0402_5%
0821 Change +3VS to +3VS_WWAN @ R418
2
1 2 XMIT_OFF#
0811 Pins 37 and 43 connect to GND and remove +1.5VS 0_1206_5% UI M_CLK
1
D19 D @
1
D1 1 AP2305GN Q52 C824 @ 1 2 2 Q10
<22> XMIT_OFF
1 2 M_WXMIT_OFF# 2MiniC@ 18P_0402_50V8J G 2N7002_SOT23-3
<22> WXMIT_OFF#
1 3 CH751H-40_SC76
S
S
D
3
CH751H-40_SC76 2
2MiniC@
01/03 Prevent WLAN leakage R435
G
2
<32> W W A N_POWER_OFF 1 2
0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN, WWAN, New Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 26 of 46
A B C D E
5 4 3 2 1
+ 1 . 8VS_CR
09/26 (JMicron)recommend (APVDD, 20 mil width, less than 120mil long)
+ 3VS
1 1 1 1 11/07 Stuff for JMB385 internal LDO
R 1042 1 2 4.7K_0402_5% X D C D 0 # _SDCD# C 1326 C 1329 + V C C _ OUT + V C C _4IN1
R 1041 1 2 4.7K_0402_5% X D C D 1 #_MSCD# 1 0U_0805_10V4Z 0 .1U_0402_16V4Z R 704
2 2 C 1327 2 C 1328 2 0_0603_5%
09/26 (JMicron)recommend
0 .1U_0402_16V4Z 1000P_0402_50V7K 1 2
D + V C C _4IN1 width/length: 12mil / + 3VS D
<250mil for PREXT signal 1
1
+ 3VS C 1325
R 1044 2 1 10K_0402_5% X D W P # _ SDWP#
(pin 7) C 1324 0.1U_0805_50V7M
R 1043 2 1 10K_0402_5% X D _RB# U 36 1 10U_0805_10V4Z
2
2
1 1
3 5 C 1336
<17> C L K _ SRC11# APCLKN APVDD
4 10 0 .1U_0402_16V4Z C 1334 C 1335
<17> C L K _ SRC11 APCLKP APV18 2
30 0 .1U_0402_16V4Z 0 .1U_0402_16V4Z
TAV33 2 2
<22> P C IE_TXN5 9
APRXN
+ 3VS 11/07 Change to 10K(vender) <22> P CIE_TXP5 8
APRXP DV33
19 Use 0603 type and over 20
20
DV33 + 1 . 8VS_CR
R 7 09 1
<22> P C I E_RXN5
C 1321 2 1 0 .1U_0402_16V4Z P C I E _ C_RXN5 11
APTXN DV33
44 mils trace width on both side
2 10K_0603_5% X D _CLE
<22> P C I E_RXP5
C 1322 2 1 0 .1U_0402_16V4Z P C I E _C_RXP5 12 18
APTXP DV18
DV18
37 09/26 (JMicron)recommend change to 0805 Size
R 1048 1 2 10K_0603_5% X D_ALE 11/07 Change to 8.2K(vender) R 402 1 2 8.2K_0402_5%P REXT 7 1 1
APREXT X D _ SD_MS_D0
MDIO0
48 09/26 (JMicron)recommend +VCC_OUT >30mil
01/03 Change Cardreader LED control 47 X D _ SD_MS_D1 C 1332 C 1333
R 972 MDIO1
+ 3VS 1 2 10K_0402_5% X IN 38 46 X D _ SD_MS_D2 0 .1U_0402_16V4Z 0 .1U_0402_16V4Z
X D _RE# R 1046 PCIES_EN MDIO2 2 2
1 2 200K_0402_5% 39 45 X D _ SD_MS_D3
PCIES JMB385 MDIO3
MDIO4
43 S D C M D _ M S BS_XDWE#
09/26 (JMicron)recommend add a 42 S D C L K _ MSCLK_XDCE#
MDIO5 X D W P # _ SDWP#
41
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test point for pin 13 1 4 MDIO6
40 X D _CLE
MDIO7 X D_D4 + V C C _OUT + V C C _4IN1
29
X D CE# MDIO8 X D_D5
2 1 2 1 1 28
@ R 706 @ C 788 <9,20,25,26> P L T_RST# XRSTN MDIO9 X D_D6
2 27
100_0402_5% 100P_0402_25V8K XTEST MDIO10
26 X D_D7 40mil
MDIO11 25 X D _RE# + 3VS @ U37
SDCLK R 404 1 0_0402_5% MDIO12 X D _RB#
1 2 1 2 <22> C R _ C P PE# 2 13 23
@ R 707 @ C 789 T78 SEEDAT MDIO13 X D_ALE
14 22 3 1
100_0402_5% 100P_0402_25V8K SEECLK MDIO14 IN OUT
4 5
C EN OUT C
34 1
1
M S C LK D18 X D C D 1 #_MSCD# NC
1 2 1 2 15 35 2 1
@ R 708 @ C 790 X D C D 0 # _SDCD# CR1_CD1N NC C 1330 GND
<22> C R _ W A KE# 1 2 16 36
100_0402_5% 100P_0402_25V8K C H 751H-40PT_SOD323-2 CR1_CD0N NC 0 .1U_0402_16V4Z G5250C2T1U_SOT23-5
6 2 @ R 1050
APGND C 1331 2 150K_0402_5%
11/09 Add D18 for cardreader wake up + V C C _OUT 17
2
CR1_PCTLN 1 U_0603_10V4Z
use for PWR_EN# 24
GND
31
R 710 GND
S D C L K _ MSCLK_XDCE# 1 2 22_0402_5% SDCLK C R _ L ED# 21 32
R 711 CR1_LEDN GND
1 2 22_0402_5% M S C LK 8mA sink current 33
R 712 GND
1 2 22_0402_5% X D CE# reserved power circuit
D41
11/07 BOM delete for JMB385 internal LDO
XDCD1#_MSCD# 2
1 1 X D _ CD#
X D C D 0 # _SDCD# 3
C 1047
D A N 2 0 2U_SC70 270P_0402_50V7K
2
09/26 Must change P mos FET
+ 1 . 8VS_CR + 1.8VS
X D_D6 5 27 X D_D4
R 719 X D_D7 4 XD-D6 SD-DAT4 23 X D_D5
470_0402_5% XD-D7 SD-DAT5 X D_D6
18
S D C M D _ M S BS_XDWE# 34 SD-DAT6 16 X D_D7
X D W P # _ SDWP# XD-WE SD-DAT7 S D C M D _ M S BS_XDWE#
33 25
2
X D _RB# 39 2 X D W P # _ SDWP#
D 15 W hite X D _RE# XD-R/B SD-WP-SW
38
X D CE# XD-RE
H T - F 1 96BP5_WHITE 37
X D _CLE XD-CE M S C LK
36 26
XD-CLE MS-SCLK 17 X D _ SD_MS_D0
MS-DATA0 X D _ SD_MS_D1
11 15
1 1
S 41
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB CardReader&CONN
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
C u s t om Mo n te v in a Bla d e UMA LA4 1 0 1P 0 .3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: S a turday, January 05, 2008 Sheet 27 of 46
5 4 3 2 1
A B C D E
CODEC POWER
(4.75V(4.56~4.94V))
+1.5VS_HDA +1.5VS 300mA
+ 3 V DD_CODEC + V DDA _CODEC_R +5VALW + V DDA_CODEC
W=40Mil U39
R1051 R1052 R1053
1 2 +3VS 1 2 1 2 + V DDA_CODEC C1341 1 2 1
IN
2.2U_0805_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0603_10V4Z
BLM18BD601SN1D_0603 BLM18BD601SN1D_0603 0_0603_5% 0.1U_0402_16V4Z 5
OUT
0.1U_0402_16V4Z
1U_0603_10V4Z
1 1 1 1 2 1
GND
C1342
1
C1343
1 3 4 1
<26,32,36,38,40,41> SUSP# SHDN BYP
2 2 2 2 2
C1337
C1338
C1339
C1340
G9191-475T1U_SOT23-5 1
2 C1344
11/07 Change to 4.75V LDO 0.1U_0402_16V4Z
2
U38
+ 3 V DD_CODEC 9 47 E A P D_CODEC
DVDD_CORE* EAPD/ SPDIF OUT 0 or 1 / GPIO 0 E A P D_CODEC <32>
1 2
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DVDD_CORE VOL_UP/DMIC_0/GPIO 1 DM IC_DAT <19>
4
VOL_DN/DMIC_1/GPIO 2
+ V DDA _CODEC_R 25
AVDD1*
30
GPIO 3
38
AVDD2**
31
HDA _BITCLK_CODEC VREFOUT-E / GPIO 4
+1.5VS_HDA 3 43
DVDD_IO GPIO 5
1
@
R1054 32 44
47_0402_5% MONO_OUT GPIO 6
45 S PDIF_OUT
2 SPDIF OUT1 / GPIO 7 S PDIF_OUT <34> 2
HDA _BITCLK_CODEC 6
<21> HDA _ BITCLK_CODEC
2
BITCLK
1 48 01/03 Change SPDIF to SPDIF1
@ HDA _ S DOUT_CODEC SPDIF OUT0
<21> HDA _ S DOUT_CODEC 5
C1345 SDO
33P_0402_50V8K R1055 1 2 HDA _ S DI N0_CODEC 8
2 <21> HDA _ SDIN0 SDI_CODEC
33_0402_5% 28 VREFOUT_B
VREFOUT-B VREFOUT_B <29>
HDA _ S Y NC _CODEC 10
<21> HDA _ S Y NC_CODEC SYNC + V DDA _CODEC_R
11/09 reserve EC_BEEP 29
HDA _RST#_CODEC VREFOUT-C
<21,32> HDA _RST#_CODEC 11
@ R445 RESET# R1056 1 2 5.1K_0402_1%
47K_0402_5% R1057 1 2 20K_0402_1% EXTMIC_DET# <29>
EC_BEEP 1 2 13 SENSE R1059 1 2 39.2K_0402_1% JACK_DET# <29,34> 11/07 Change R1059 39.2K
<32> EC_BEEP SENSE_A
R1058 1 2 22_0402_5% 46 R683 1 2 10K_0402_1% INTMIC_DET# <29>
<19> DM IC_CLK DMIC_CLK C1346 1 2 0.1U_0402_16V4Z
R1060 1 2 47K_0402_5% C1347 2 1 33 41 HP _OUTR
<22> SB_SPKR HP _OUTR <29>
1U_0603_10V4Z CAP2 PORTA_R
HP Jack & Dock
R1061 1 2 10K_0402_5% 1 2 M ONO_ INR 12 39 HP_OUTL
PCBEEP PORTA_L HP_OUTL <29>
C1348 0.1U_0402_16V4Z
C1349 1 2 0.1U_0402_16V4Z
22 MIC_EXTR 1 2
PORTB_R MIC_EXT_R <29>
@ C1358 40 C1350 1U_0603_10V6K Jack MIC
R1062 1 NC / OTP
1 2 + V DDA _CODEC_R 2 5.1K_0402_1% 21 MIC_EXTL 1 2 MIC_EXT_L <29>
0.1U_0402_16V4Z R1063 1 PORTB_L
<34> SENSE_B# 2 39.2K_0402_1% SENSEB# 34 C1351 1U_0603_10V6K 1 2 M IC_ IN_R <29>
SENSE_B / NC C1352 0.022U_0402_16V7K
1
1
@ C1359 37 24 M IC_ I NR
C1353 NC PORTC_R @ R1064
1 2 11/08 Change C1352 C1354 (recommend)
0.1U_0402_16V4Z 0.1U_0402_16V4Z 18 23 M IC _INL 0_0603_5%
2 NC PORTC_L
@ C1360
Internal MIC
19
2
NC L I NE_OUT_R
1 2 36 L INE_OUT_R <29> 1 2 M IC_IN_L <29>
0.1U_0402_16V4Z PORTD_R C1354 0.022U_0402_16V7K
20
NC LINE_OUT_L
35 LINE_OUT_L <29> Internal SPKR.
3 @ C1361 C1355 PORTD_L 3
1 2 10U_0805_10V4Z
0.1U_0402_16V4Z 1 2 V C_REFA 27 15 DOCK _ MICR 1 2 DOCK _ M ICR_C R733 1 2 10K_0402_5%
VREFFILT PORTE_R DOCK _MIC_R <34>
C1356 1U_0603_10V6K DOCK MIC
C1362 26 14 DOC K_MICL 1 2 DOCK _MICL_C R734 1 2 10K_0402_5%
AVSS1* PORTE_L DOCK_MIC_L <34>
1 2 C1357 1U_0603_10V6K
0_0402_5% 42
AVSS2**
1
17
R1065 PORTF_R R735 R736
7
DVSS** 1.21K_0402_1% 1.21K_0402_1%
1 2 16
0_1206_5% PORTF_L
1/10*Vin
2
R596
1 2 92HD71B7X5NLGXA1X8_QFN48_7X7 need close to
GNDA <29,34>
0_1206_5% Codec
GND GNDA
11/07 Stuff 0 Ohm for AGND and GND
SENSE A SENSE B
4
A 39.2K E 39.2K 4
B 20K F 20K
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
C282 C283 C284
+5VS 5
1 1 1 1 GND1
1 10U_0805_10V4Z 1
2 2 2 1 1 21.6dB 6
GND2
15.6 dB
C1378
C1377
C1376
C1375
0.1U_0402_16V4Z 11/17 Change to15.6 dB E&T_3806-F04N-02R
2
2 2 2 2 C ONN@
16
15
6
1
U40 11/07Change JP60 PCB
@ D55
VDD
PVDD1
PVDD2
@ R395 R396 PSOT24C_SOT23-3 Footprint from
100K_0402_5% 100K_0402_5%
ACES_85204-04001_4P to
1
2
2
C285 1 2 0.022U_0603_25V7K 7
RIN+ GAIN0
2 8/31EMI request ACES_88231-04001_4P
1 2
C286 0.022U_0402_16V7K 3
GAIN1 D56 @
1
C287 1 2 0.022U_0603_25V7K17 PSOT24C_SOT23-3
<28> L INE_OUT_R RIN- SPKR+
1 2 18
C288 0.022U_0402_16V7K ROUT+ R397 @ R398
100K_0402_5% 100K_0402_5%
14 SPKR-
2
C289 ROUT-
1 2 0.022U_0603_25V7K 9
Audio/B & CIR
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LIN+
1 2
2N7002DW-7-F_SOT363-6
C290 0.022U_0402_16V7K 4 SPKL+ <28,34> JACK_DET#
LOUT+
C291 1 2 0.022U_0603_25V7K 5 B+ JP49
<28> LINE_OUT_L LIN- SPKL- +3VALW MIC_EXT_R
1 2 8 1
LOUT- 1
3
C292 0.022U_0402_16V7K MIC_EXT_L 2
2
1
Q16B 3
3
2
DOCK@ R678 HP _OUT_R 4
+3VALW R676 330K_0402_5% HP_OUT_L 4
5 5
10K_0402_5% DOCK@ 5
12 6
NC DOCK@ EXTMIC_DET# 6
<28> EXTMIC_DET# 7
2
7
THERMAL PAD
2
10 Keep 10 mil width HP_DET# 8
1
2 EC_MUTE# BYPASS R401 8 2
19 9
<32> EC_MUTE# SHUTDOWN 10K_0402_5% 9
1 10
10
2N7002DW-7-F_SOT363-6
1 <32,34> CIR_ IN CIR_ IN 11
11
6
GND1
GND2
GND3
GND4
C293 +5VL 12
1
1U_0805_25V6K Q16A Q46 C270 12
13
13
1
2 DOCK@ D 2N7002_SOT23-3 0.01U_0402_25V7K 14
HP_DET# DOCK@ 2 14
2 2 DOCK@
20
13
11
1
21
G ACES_87213-1400G
TPA6017A2_TSSOP20 C ONN@
11/07 Add 10K PU S
3
12/18 Shut down pop noise Q17B HP OUT
5
DOCK@
C295
R409 1 2 47_0402_5%
+
<28> HP _OUTR 3 4 1 2 DOCK_LOUT_R <34>
Q17A DOCK@ 150U_B_6.3VM_R40M DOCK@
2
DOCK@ 2N7002DW-7-F_SOT363-6
C296 HP OUT For Docking
R410 1 2 47_0402_5%
+
<28> HP_OUTL 6 1 1 2 DOCK_LOUT_L <34>
R684 DOCK@ 150U_B_6.3VM_R40M DOCK@
<28> VREFOUT_B 2 1 C787 1 2 2N7002DW-7-F_SOT363-6
0_0402_5% 11/07 Add Capacitor avoid DC lever to Docking audio
1U_0603_10V4Z
1
R685 R686
C785 1 HP _OUT_R
+
2
4.7K_0402_5% 4.7K_0402_5% 150U_B_6.3VM_R40M
2
+
2
<28> MIC_EXT_R MIC_EXT_R 150U_B_6.3VM_R40M
0_0402_5%
+ V DDA_CODEC
R1077 C1379
+ V DDA _CODEC 0_0402_5% 1U_0603_10V4Z INTMIC IN
2 1 1 2
2
1
1
R951
1
+3VS JP51
2
JP8 1 2 +1.5VS 1
R475 0_0603_5% 1
<28> M IC_IN_L 2
@ 1 2
1 2 2 +3VS <28> M IC_ IN_R 3
GND1 RES0 3
C619
C620
@C621
0.1U_0402_16V4Z
4.7U_0805_10V4Z
1000P_0402_50V7K
2N7002DW-7-F_SOT363-6
<28> INTMIC_DET# ACES_88231-04001
3
2 1 1 2 Q18B C ONN@
6
2N7002DW-7-F_SOT363-6
@ R478 @ C618 Q18A
GND
GND
GND
GND
GND
GND
10_0402_5% 10P_0402_25V8K
H12 H14 5
HOLEA HOLEA ACES_88018-124G 2
13
14
15
16
17
18
4
1
4 Connector for MDC Rev1.5 4
1
C ONN@
MDC Standoff
US B _VCCC
U4 1 US B _VCCC
1 8 W=100mils JP53
GND OUT USB
2 7 1
IN OUT VBUS
150U_D_6.3VM
0.1U_0402_16V4Z
1000P_0402_50V7K
D 3 6 R1080 1 2 0_0402_5% U SB20_N2_R 2 D
IN OUT 1 <22> USB20_N2 D-
1 USB_EN# 4 5 1 1 R1081 1 2 0_0402_5% USB20_P2_R 3
EN# OC# <22> USB20_P2 D+
C1380
C1382
C1383
C1381 + 4
TPS2061IDGNR_MSOP8 GND
5
2 2 2 2 SATA_TXP5 GND
<21> SATA_TXP5 6
SATA_TXN5 A+ ESATA
<21> SATA_TXN5 7
A-
8
4.7U_0805_10V4Z C1385 2 GND
<21> SATA_RXN5_C 1 0.01U_0402_16V7KSATA_RXN5 9
B-
<21> SATA_RXP5_C
C1384 2 1 0.01U_0402_16V7KSATA_RXP5 10
ESATA@ B+
11
R1083 GND
1 2 10K_0402_5% +5VALW ESATA@
12
GND
13
GND
14
GND
15
GND
TYCO_1759576-1
C ONN@
D45
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+5VALW 4 2 USB20_N2
VIN IO1
D46
USB20_P2 3 1
IO2 GND SATA_TXP5
+5VALW 4 2
@ PRTR5V0U2X_SOT143-4 VIN IO1
SATA_TXN5 3 1
IO2 GND
@ PRTR5V0U2X_SOT143-4
C C
3 1 1 2 7 @ R1087 1 2 1K_0402_5%
D
D4 7
2
USB_EN# GND2
2 JP24 ACES_88231-08001 USB20_P6_R
+5VALW 4 2
C ONN@ VIN IO1
1
R634 1 1
<22> USB20_N7 2 0_0402_5% U SB20_N7_R 2 U SB20_N6_R 3 1
R635 1 2 IO2 GND
<22> USB20_P7 2 0_0402_5% USB20_P7_R 3
3 +3VS @ PRTR5V0U2X_SOT143-4
FP@ 4
3
@ R405 4 R235
FP@ 5
5
1 2 6 1 2
0_0402_5% 6
7
@ D30 GND +3VALW 0_0603_5% +3VAUX_BT
8
PACDN042_SOT23-3~D GND Q105 SI2301BDS_SOT23
B ACES_85201-06051 @ R236 B
1
0.1U_0402_16V4Z
S
C ONN@ 1 2 3 1
D
11/07 Change PCB Footprint 0_0603_5%
G
1 1 1 1
2
to ACES_85201-06051_6P C1387 C1388 C1389
C1386 R1090
1U_0603_10V4Z 100K_0402_5%
2 2 2 2
2
0.01U_0402_16V7K 4.7U_0805_10V4Z
R1092 C1390
1 2 1 2
USB cable connector for Right side <22> BT_OFF
47K_0402_5% 0.1U_0402_16V4Z
JP55
+5VALW 1
1
2 01/03 Change BT power to +3VS
2
3
USB_EN# 3
<32> USB_EN# 4
4
<22> USB20_N0 5
5
<22> USB20_P0 6
6
7
7
8
<22> USB20_N1 8
9
<22> USB20_P1 9
10
10
11
A GND1 A
12
GND2
ACES_87213-1000G
C ONN@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB, BT, eSATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 30 of 46
5 4 3 2 1
5 4 3 2 1
D SPI ROM D
+3VL
U27
20mils 8 4
VCC VSS
1
C712
0.1U_0402_16V4Z
3
7
W
LPC Debug Port
2 HOLD
1 2 SPI_FSEL# 1
<32> FSEL# S
R553 0_0402_5% Change from +3VL to +3VS. 6/9
1 2 S PI_CLK_R 6
<22,32> SPI_CLK C
R554 0_0402_5% Removed +3VS. 6/13
<32> F W R# 1 2 S P I_FWR# 5 2 SPI_SO 1 2 F RD# F RD# <32>
R556 0_0402_5% D Q R555 0_0402_5%
W IESON G6179 8P SPI
B+
SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH
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@ R230 @ C307 WIESO_G6179-100000_8P JP18
SPI_FSEL# 2 1 2 1 1
Ground
<17> CLK_DEBUG_PORT_0 2
33_0402_5% 15P_0402_50V8J LPC_PCI_CLK
3
Ground
<21,26,32> LPC_FRAME# 4
@ R231 @ C308 LPC_FRAME#
5
S PI_CLK_R 2 +V3S
1 2 1 11/16 Change TO +3VALW <20,32> P CI_RST# 6
LPC_RESET#
7
33_0402_5% 15P_0402_50V8J +V3S
<21,26,32> L PC_AD0 8
+3VALW +3VALW LPC_AD0
<21,26,32> L PC_AD1 9
@ R232 @ C309 LPC_AD1
<21,26,32> L PC_AD2 10
S P I_FWR# 2 LPC_AD2
1 2 1 <21,26,32> L PC_AD3 11
LPC_AD3
1
C C
1 12
33_0402_5% 15P_0402_50V8J C711 ON/ OFFBTNLED# VCC_3VA
13
R552 PWR_LED#
14
0.1U_0402_16V4Z 100K_0402_5% CAPS_LED#
15
2 U28 V CC1 P WRGD NUM_LED#
12/27EMI request 16
2
SPI_CLK_JP18 VCC1_PWRGD
8 1 Connect pin3 & 23 17
VCC A0 SPI_CS#_JP18 SPI_CLK
7 2 18
WP A1 together and pin 24 SPI_SI_JP18 SPI_CS#
<32,33,37> SMB_EC_CK1 6 3 19
SCL A2 SPI_SO_JP18 SPI_SI
5 4 20
<32,33,37> SMB_EC_DA1 SDA GND to GND in 6/29. SPI_HOLD#_0 21
SPI_SO
AT24C16AN-10SI-2.7_SO8 SPI_HOLD#
22
Reserved
23
Reserved
24
Reserved
1 R557 ACES_87216-2404_24P
100K_0402_5% C ONN@
2
SPI_CLK 1 2 SPI_CLK_JP18
R558 0_0402_5%
DE B UG@
FSEL# 1 2 SPI_CS#_JP18
+3VS R559 0_0402_5%
DE B UG@
+3VS +3VALW F W R# 1 2 SPI_SI_JP18
R560 0_0402_5%
1 DE B UG@
R561 1 2 HOL D# 1 2 SPI_HOLD#_0
B R411 1 2 SPI_WP# +3VS C304 3.3K_0402_5% R562 0_0402_5% B
3.3K_0402_5% 0.1U_0402_16V4Z DE B UG@
2 F RD# SPI_SO_JP18
1 2
R412 1 2S PI_HOLD# U6 R563 0_0402_5%
2
3.3K_0402_5% 8 4 DE B UG@
@ R413 VCC VSS ON /OFFBTN_LED# ON/ OFFBTNLED#
1 2
1K_0402_5% SPI_WP# <32,33> ON/OFFBTN_LED# R565 0_0402_5%
3
W DE B UG@
S PI_HOLD# 7 V CC1 _ PWRGD 1 2 V CC1 P WRGD
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS ROM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 31 of 46
5 4 3 2 1
C301
+3VL_EC
BATT_OVP 2 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K
1 1 1 1 1 100P_0402_50V8J
111
125
+5VL +3VS
22
33
96
67
9
U30 KSO15 @ C792 1 2 100P_0402_50V8J
SMB_EC_DA1 R573 1 2 4.7K_0402_5%
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
SMB_EC_CK1 R577 1 2 4.7K_0402_5% KSO10 @ C793 1 2 100P_0402_50V8J
SMB_EC_DA2 R574 1 2 4.7K_0402_5%
SMB_EC_CK2 R575 1 2 4.7K_0402_5% KSO11 @ C794 1 2 100P_0402_50V8J
GATEA20 1 21 I NV_PWM
<21> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INV_PWM <19>
KB_RST# 2 23 F AN_PWM KSO14 @ C795 1 2 100P_0402_50V8J
<21> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 F AN_PWM <6>
S I RQ 3 26 EC_BEEP
<22> S IRQ SERIRQ# FANPWM1/GPIO12 EC_BEEP <28>
LPC_FRAME# 4 27 A C OFF KSO13 @ C796 1 2 100P_0402_50V8J
<21,26,31> LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 A COFF <38,39>
@ C722 @ R576 <21,26,31> L PC_AD3 LPC_AD3 5 0.01U_0402_16V7K
LPC_AD2 LAD3 C720 E CA G ND KSO12 @ C797 1
1 2 1 2 <21,26,31> L PC_AD2 7 PWM Output 1 2 2 100P_0402_50V8J
33_0402_5% LPC_AD1 LAD2 BATT_TEMP
<21,26,31> L PC_AD1 8 63 BATT_TEMP <37>
15P_0402_50V8J LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_OVP KSO3 @ C798 1 2 100P_0402_50V8J
LAD0 LPC & MISC
<21,26,31> L PC_AD0 10 64 BATT_OVP <37>
BATT_OVP/AD1/GPIO39 A DP_I
65 A DP_I <38>
CL K_PCI_EC ADP_I/AD2/GPIO3A A D P_ID KSO6 @ C799 1
<17> CLK_PCI_EC 12 AD Input 66 A DP _ID <37> 2 100P_0402_50V8J
PCI_RST# PCICLK AD3/GPIO3B TP_BTN#
<20,31> P CI_RST# 13 75 TP_BTN# <33>
ECRST# PCIRST#/GPIO05 AD4/GPIO42 ANA_MIC_DET KSO8 @ C800 1
+3VL 1 2 37 76 ANA_MIC_DET <29> 2 100P_0402_50V8J
R578 47K_0402_5% ECRST# SELIO2#/AD5/GPIO43
<22> E C_SCI# 20
R403 1 SCI#/GPIO0E
<21,28> HDA _ RST#_CODEC 2 0_0402_5% 38 KSO7 @ C801 1 2 100P_0402_50V8J
CLKRUN#/GPIO1D DA C_ BRIG
68 DA C_ BRIG <19>
DAC_BRIG/DA0/GPIO3C
1
www.kythuatvitinh.com
EN_DFAN1/DA1/GPIO3D V CTRL <38>
C721 0.1U_0402_16V4Z DA Output 71 IRE F
J OPEN KSI0 IREF/DA2/GPIO3E AC_SET IRE F <38> KSO2 @ C803 1
11/09 Add HDA_RST# to EC 55 72 2 100P_0402_50V8J
2
KSO7 SDIDI/GPXID0
46 SPI Device Interface
2
BATT_CHGI_LED#/GPIO52 CAPS_LED#
91 CAPS_LED# <33>
@ R585 R191 SMB_EC_CK1 CAPS_LED#/GPIO53 BAT_LED#
<31,33,37> SMB_EC_CK1 77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BAT_LED# <33>
10K_0402_5% 10K_0402_5% SMB_EC_DA1 78 93 ON /OFFBTN_LED#
<31,33,37> SMB_EC_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 ON/OFFBTN_LED# <31,33> +3VS
11/15 Delete PCI_PME# OPP@ SMB_EC_CK2 79 S M Bus 95 S Y SON R407
<6> SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56 S Y S ON <26,33,36,41>
SMB_EC_DA2 80 121 V R _ON 10K_0402_5%
<6> SMB_EC_DA2 V R_ ON <43>
1
9
1
Y5 CH751H-40PT_SOD323-2 KSO7
GND
GND
GND
GND
GND
1
@ C724 R714 KSO4 10
3 4
NC OUT R595 4.7U_0603_6.3V6K 10K_0402_5% KSO2 11
EC DEBUG port 2 1 20M_0402_5% KB926QFB0_LQFP128_14X14 2 KSI0 12
11
24
35
94
113
69
NC IN KSO1 13
2
2
JP20 NM I_DBG# 15
1 2 P C I_SERR# P CI_SERR# <20>
KSI3
@ C RY 1 Revision KSI2 16
1 1 2
1 U RX R442 1 +3VL_EC +3VL 17
2 2 L A N _POWER_OFF_R CH751H-40PT_SOD323-2 KSO0
2 UTX R233 2 18
3 1 0_0402_5% C725 KSI5
E CA G ND
1
4 R715 KSO9 20
ACES_85205-0400 + E C_AVCC L30 10K_0402_5% KSI6 21
C ONN@ 0_0603_5% KSI7 22
R443 KSI1 23
L A N _POWER_OFF_R L31 D13 24
<25> L A N_POWER_OFF 1 2
2
2
1 2 1 2 A C_ IN 2 1 A CIN ACES_85201-2405
A CIN <38>
0_0402_5% C726 0.1U_0402_16V4Z 0_0603_5% C ONN@
CH751H-40PT_SOD323-2
1 2
+3VL +3VL C791 100P_0402_50V8J
Vendor
1
Recommend
R1099
R1100 4.7K_0402_5%
4.7K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title
2
1
1 2 1 2 +5VS_LED
<32> CAPS_LED#
HT-F196BP5_WHITE 470_0402_5%
Cap lock R611 @
10K_0402_5% +5VS_LED
1 S W1 1
TJG-533-V-T/R_6P
2
White 3 1 TP_BTN# <32>
1
D52 R1097
<32> BAT_LED# 1 2 1 2 +5VALW_LED Battery 4 2
11/07 Change part number
R610
820_0402_5%
R609
200_0402_5%
HT-F196BP5_WHITE 470_0402_5%
Charge LED
5
6
2
D53
White R1098
2
470_0402_5% +5VS
White 1 2 1 2
AMBER White
<21> SATA_LED# +5VS_LED
Amber
White
D1 2
1
GS@ QSMF-C16E_AMBER-WHITE
<22> HDDHALT_LED#
AMBER
3 4 1
R728
2 +3VS HDD LED R718
1
470_0402_5% 10K_0402_5%
Amber
2
QSMF-C16E_AMBER-WHITE TP_LED# TP_LED# <32>
www.kythuatvitinh.com
1
D
2
D17 White R980 G
ON /OFFBTN_LED# 1 2 1 2 +5VALW_LED System Q4 S
3
2N7002_SOT23-3
HT-F196BP5_WHITE 470_0402_5% On (TP_LED#=L)-> White
Power LED Off (TP_LED#=H)-> Amber
TP_DATA
2 TP_CLK 2
2
D28
PSOT24C_SOT23-3
1
+5VALW +5V_TP @
R51 R53
0_0805_5% 0_0805_5% R691 1 2 0_0603_5%
1
Main@ OPP@ +5V_TP
2
EMI request
S
OPP@ R151 1 2 0_0402_5% 3 1
D
<32> WL_BLUE_BTN
WL_BLUE_LED# OPP@ R169 1 2 0_0402_5% JP59 1
1 Q23 @ C729
1
1
2 SI2301BDS-T1-E3_SOT23-3 0.1U_0402_16V4Z
G
2
SMB_EC_CK1 R729 2
<31,32,37> SMB_EC_CK1 1 2 0_0402_5% 3 @ R612
ESB_CLK Main@ R56 3 2
<32> ESB_CLK 1 2 0_0402_5% 4 10K_0402_5% JP23
ESB_DAT Main@ R149 4
ENE <32> ESB_DAT 1 2 0_0402_5% 5 1
5 1 TP_CLK
<32> I2 C_INT 6 2 TP_CLK <32>
2
6 2 TP_DATA
7 5 3 TP_DATA <32>
7 G1 3
<32> NUM_LED# 8 6 4
SMB_EC_DA1 R730 8 G2 4
<31,32,37> SMB_EC_DA1 1 2 0_0402_5% 9
9 ACES_85201-04051
10
10
1
1
D
11 C ONN@ 1 1
R1101 GND S Y SON 2 @ Q24
Cypress 10K_0402_5% 1
12
GND <26,32,36,41> S Y S ON
2N7002_SOT23-3 @ C730 @ C731
G
@ R234 @ C310 4.7U_0603_6.3V6K ACES_85201-1005N S 100P_0402_50V8J 100P_0402_50V8J
3
ESB_CLK C ONN@ 2 2
2 1 2 1
2
C313
33_0402_5% 15P_0402_50V8J 2
3
01/03 EMI request 3
ON/OFF Button Connector Keyboard backlight Conn Mini card LED +3VS
1
+3VS
R193
10K_0402_5%
2
3
+5VALW_LED 47K Q14
R205 JP9 DTA114YKAT146_SOT23-3
WL_BLUE_LED# <32>
2N7002DW-7-F_SOT363-6
JP10 +5VS_LED 1 2 1
1
1 2 <26> WL_LED# 2 10K
1 2
6
ON/ OFFBTN 2 0_0805_5% 3 5
<32> ON/OFFBTN 2 3 G1
ON /OFFBTN_LED# 3 5 4 6 Q11A
<31,32> ON/OFFBTN_LED# 3 G1 4 G2
4 6
4 G2 ACES_85201-04051
<30> BT_LED 2
ACES_85201-04051 C ONN@ +3VS
1
C ONN@
1
R716
100K_0402_5%
2N7002DW-7-F_SOT363-6
47K Q20
01/03 Keyboard backlight reserve a 0805 size resistor DTA114YKAT146_SOT23-3
2
2MiniC@
3
<26> W W _LED# 2 10K
Q11B
1
1
4
R717
4 +3VALW 100K_0402_5% 4
JP11
1
2
1
<32> L ID_SW# 2
2
3 5 11/20 Reserve WW_LED function
3 G1
4 6
4 G2
ACES_85201-04051
CONN@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/08/28 Deciphered Date 2006/07/26 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KBD, ON/OFF, SW, CIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina B lade UMA LA 4101P 0.3
01/03 Change Lid switch connector type MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 33 of 46
A B C D E
Atlas/ Saturn Dock
J DOCK1
www.kythuatvitinh.com
<36,42> S Y SON# PJP3 + DOCKVIN
G 10K_0402_5% 41
Q58 DOCK@ GND
S B+ 1 2 42
3
2N7002_SOT23-3 GND
45 43
DOCK@ GND GND + DOCKVIN
P AD-OPEN 2x2m 46 44
GND GND
C305 1 2
C ONN@ FOX_QL1122L-H212AR-7F @ 1000P_0402_50V7K
1
C306 1 2
@ 1000P_0402_50V7K C734
1000P_0402_50V7K
2 DOCK@
11/12 Change to +3VL
GNDA
Dock PRESENT +3VL
11/17 Reserve
2
R621
10K_0402_5%
MIC_Dock R_VOL_UP# DOC K_LOUT_R
1
R_ V OL_DWN# D OCK_LOUT_L
<32> CONA#
Need 600 Ohm 500 mA 1 1
1000P_0402_50V7K
1000P_0402_50V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
1
R979 D
1 1
D OCK_PRESENT 1 2 2 L36 DOCK@ C740 C741
G Q27 FBM-11-160808-601-T_0603 DOCK@ 2 2 DOCK@
22_0402_5% S 2N7002_SOT23-3 <28> DOCK _ MIC_R 1 2 DOCK _ MIC_R_C C744 C745
3
1
C754 C755
220P_0402_50V7K 220P_0402_50V7K 11/17 Recommend
DOCK@ 2 2 DOCK@
GNDA GNDA
+3VS
2
2
R625
R626 10K_0402_5%
2
10K_0402_5% DOCK@
1
DOCK@ D R722 @
1
2 Q29 33_0402_5%
1
1 G 2N7002_SOT23-3
C S DOCK@
1 1
Q32 2 C64 R977
MMBT3904_NL_SOT23-3 B D DOCK@ DOCK@
1
3
2
1
DOCK@ 1
C757 S PDIFO_L 1 2
R633 0_0603_5% C819 R978
47K_0402_5% 1 220P_0402_25V8J 110_0402_5%
1
2
1U_0603_10V6K
DOCK@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DOCK CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 34 of 46
5 4 3 2 1
+3VS_LS +3VS_LS
48
47
46
45
44
43
42
41
40
39
38
37
U43
D +3VS_LS R648 1 2 0_0603_5% D
VCC3V
GND
VCC3V
GND
IN_D4-
IN_D3-
IN_D2-
IN_D1-
IN_D4+
IN_D3+
IN_D2+
IN_D1+
+3VS +3VS_LS
1 36
GND GND
1
Follow Intel R649 R650
+3VS_LS 2
VCC3V FUNCTION4
35
2
FUCNTION2 VCC3V
5 32 @ R652 2 1 0_0402_5%
R653 GND DDC_EN
2 1 1K_0402_5% 6 31
ANALOG1(REXT) GND
TMDS_B_HPD 7 30 H DMI_DETECT
HPD_SOURCE HPD_SINK
8 29 HD MIDAT
<9> HDMIDAT_NB SDA_SOURCE SDA_SINK
www.kythuatvitinh.com
9 28 HDM ICLK
<9> HDM ICLK_NB SCL_SOURCE SCL_SINK
10 27
ANALOG2 GND
+3VS_LS 11 26 +3VS_LS @ R654 2 1 0_0402_5% +3VS_LS
VCC3V VCC3V
+3VS_LS 12 25 R655 2 1 0_0402_5%
GND OE*
OUT_D4+
OUT_D3+
OUT_D2+
OUT_D1+
OUT_D4-
OUT_D3-
OUT_D2-
OUT_D1-
VCC3V
VCC3V
1
GND
GND
R742
20K_0402_5%
C C
13
14
15
16
17
18
19
20
21
22
23
24
CH7318A-BF-TR_QFN48_7X7
2
TMDS_B_HPD#
TMDS_B_HPD# <11>
HDMI_TX_0-
1
R743 2N7002_SOT23-3
20K_0402_5% HDMI_TX_1-
2
68_0402_5% 68_0402_5%
HDMI_TX_2- 0.5P_0402_50V8B 0.5P_0402_50V8B
Follow Vendor Feedback
11/07 correct TMDS_B_HPD# connection to North bridge
R206 1 2 0_0402_5%
L38 @
HDMI Connector +5VS
HDM ICLK- 1 2 HDM I_CLK-
1 2
2
WCM-2012-900T_0805
HDM ICLK+ 4 3 HD MI_CLK+
B 4 3 RB411D T146 _SOT23-3 B
Vendor suggests 4K PU D31
R211 1 2 0_0402_5% 11/07 Follow recommend change to 3.9K
1
1 2 +5VS_HDMI
R214 0_0402_5%
1
L39 @
3.9K_0402_1%
3.9K_0402_1%
HDMI_TX_0- 1 2 HDMI_TX0- 0.1U_0402_16V4Z
1 2
1
C773
WCM-2012-900T_0805 2
R49
R50
HDMI_TX_0+ 4 3 HDMI_TX0+
4 3
2
R217 1 2 0_0402_5%
1 2 J HDMI1
R219 0_0402_5% 18
HD MIDAT +5V
16 13
L41 @ R665 L40 HDM ICLK SDA CEC
15 14
HDMI_TX_1- HDMI_TX1- H DMI_DETECT SCL Reserved
1 2 1 2 1 2 19
1 2 1K_0402_1% HP_DET
2
GND
1
1
WCM-2012-900T_0805 FBML10160808121LMT_0603 1 HDM I_CLK- 12 5
HDMI_TX_1+ HDMI_TX1+ HD MI_CLK+ CK- GND
4 3 10 8
4 3 D32 R666 HDMI_TX0- CK+ GND
9 11
SKS10-04AT_TSMA 10K_0402_1% C774 HDMI_TX0+ D0- GND
7 20
R220 1 330P_0402_50V7K 2 D0+ GND
2 0_0402_5% HDMI_TX1- 6 21
2
1 2
R222 0_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI LS & Conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 35 of 46
5 4 3 2 1
5 4 3 2 1
S
10U_0805_10V4Z
D
8 1 8 1 3 1
D S D S
1
10U_0805_10V4Z
7 2 1 7 2
D S D S
1
0.1U_0402_16V4Z
10U_0805_10V4Z
1 6 3 R636 C759 6 3 1
1
G
1 1 1 1
2
D R223 D G C761 C762 330K_0402_5% 10U_0805_10V4Z D G C763 C764 10K_0402_5% 0.1U_0402_16V4Z D
AO4466_SO8 2 AO4466_SO8
2
330K_0402_5% 2 2
2
2 2 2 2 D IM_LED#
2
RUNO N_3VS
1
3
1
R U NON R638 0.1U_0402_16V4Z D
1
DI M_LED 2 Q35
<32> DIM_LED
6
470_0402_5% G 2N7002_SOT23-3
@ R224 SUSP 5 S
3
470_0402_5% 1
SUSP 2 01/03 Sparate+5VS C765
4
Q34B
1 and +3VS power 0.01U_0402_16V7K
1
Q34A 2
@ C65 timing 2N7002DW-7-F_SOT363-6 +5VS +5VS_LED
2N7002DW-7-F_SOT363-6 0.01U_0402_16V7K Q15
2 SI2301BDS-T1-E3_SOT23-3
S
3 1
D
www.kythuatvitinh.com
1
C294
G
2
0.1U_0402_16V4Z
+1.8V to +1.8VS Transfer D IM_LED#
2
+1.8V +1.8VS
U34 @
8 1 +3VL +3VL
D S
7 2
D S
0.1U_0402_16V4Z
10U_0805_10V4Z
C C
6 3
D S
1
10U_0805_10V4Z
5 4 1 1
D G @ C767 @ C768 R639 R640
1
@ C766 AO4466_SO8
100K_0402_5% 100K_0402_5%
2 2
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2
2
2 S Y SON# SUSP
<34,42> S Y SON# SUSP <42>
R U NON
3
Q13A Q13B
S Y SON 2 5 SUSP#
<26,32,33,41> S Y S ON SUSP# <26,28,32,38,40,41>
11/07 BOM Delete +1.8VS for Cardreader internal LDO
4
H1 H2 H3 H4 H5 H6 H7 H8 H9 H1 0
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
Discharge circuit
1
+5VS +3VS +1.5VS + VCCP +1.8V +0.9V +1.8VS
B B
H15 H16 H17 H18 H1 9 H20
1
1
HOLEA HOLEA HOLEA HOLEA HOL EC HOLEC
R641 R642 R644 R645 R643 R646 @ R647
1
2
2
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
2N7002DW-7-F_SOT363-6
6
3
FM1 FM2 FM3 FM4
1
Q6A Q6B Q9A Q9B Q12A Q12B D @ Q44 1 1 1 1
SUSP 2
SUSP 2 SUSP 5 SUSP 2 SUSP 5 S Y SON# 2 SUSP 5 G
S
3
2N7002_SOT23-3
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 36 of 46
5 4 3 2 1
A B C D
+3VALW
PQ3
3
T P0610K-T1-E3_SOT23-3
BATT
1
2 AC_LED <38> 1
499K_0402_1% 340K_0402_1%
P R1 1
+5VALW
ADP_ID <32>
0.01U_0402_25V7K
2 1
PC12
2
1
1
P C1
PR8 PD4 @1000P_0402_50V7K
P R4 1
100_0402_5% P R2
10K_0402_5%
VIN +DOCKVIN
2
1
2
ACES_88334-057N RLZ3.6B_LL34
AD P _SIGNAL 1 2
8
5 P R3 P R5
5 10K_0402_5% 10K_0402_5%
4 3
P
4 PL1 PL2 +
3
3
0
1 2 1 BATT_OVP <32>
2 SMB3025500YA_2P SMB3025500YA_2P 2
2 -
G
105K_0402_1%
1 AD P IN 1 2 2 1
www.kythuatvitinh.com
1
P R6 1
0.01U_0402_25V7K
4
1
PJP1 P U1A
100P_0402_50V8J
P C6
LM358ADT_SO8
1000P_0402_50V7K
2
2
100P_0402_50V8J
P D1
2
1
1
P C5
P C4
P C3
2
2
P C2
1000P_0402_50V7K
@PJSOT 24C_SOT23-3
1
2 2
VMB
PL3 BATT
PJP2 HCB2012KF-121T50_0805
8 1 2
8 PL4
7
7
6 EC_SMD P D2 HCB2012KF-121T50_0805
PH1 under CPU botten side :
6 EC_SMC @SM05_SOT23
5
5
4 3
1 2 CPU thermal protection at 90 +-3 degree C
4
1
3
3
2 2
1 Recovery at 47 +-3 degree C
2 P C9
1 PC8
2
1 1000P_0402_50V7K 0.01U_0402_50V4Z P R7
9
GND +5VS
10 47K_0402_1%
GND
3
1 2
3 SUYIN_200275MR008GXOLZR CPU 3
1
1
1
PD3
1
P R14 @SM24.TC_SOT23-3 P H1
P R13 100_0402_5% 10K_T H11-3H103FT_0603_1%
100_0402_5%
2
ENTRIP1 <39>
2
2
SMB_EC_DA1 SMB_EC_DA1 <31,32,33> PR10
8
15K_0402_1%
1
D
1 2 5
P
SMB_EC_CK1 + PQ1
SMB_EC_CK1 <31,32,33> 7 2
0 G SSM3K7002FU_SC70-3
+5VALW 1 2 6
-
G
BAT _ID <38> PR11 PU1B S
3
1 150K_0402_1%
4
1
1
LM358ADT_SO8
1
P C10 PR12
PR16 2.55K_0402_1%
6.49K_0402_1% +3VL 0.22U_0603_10V7K P R15
2
1 2 150K_0402_1% PC11
2
2
1000P_0402_50V7K ENTRIP2 <39>
2
1
1
PR17 D
1K_0402_5% 2 PQ2
G SSM3K7002FU_SC70-3
2
BATT_TEMP <32>
S
3
4 4
Security Classification
2007/05/29
Compal Secret Data
2008/05/29 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Connector/CPU_OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size D o cument Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS M ontevina Blade UMA LA4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: Saturday, January 05, 2008 Sheet 37 of 46
A B C D
A B C D
P4 B+
BATT
V IN P2
PQ102
AM4 8 3 5EP-T1-PF_SO8
PQ101 PQ103
1 8
@1 0 0 0P_0402_50V7K
1
PR102 PL101 2 7 1
AM4 8 35EP-T1-PF_SO8 AM4 8 3 5EP-T1-PF_SO8 0 .0 12_2512_1% HCB2 0 1 2KF-121T50_0805 3 6
1
8 1 1 8 1 2 1 2 CHG _ B+ 5
PC1 32
7 2 2 7 PR103
1
6 3 3 6 4 7 K_0402_5%
2
4 .7 U_0805_25V6-K
4 .7 U_0805_25V6-K
4 .7 U_0805_25V6-K
5 5 PC133 1 2 1 2
PR101 4 7 0 P_0402_50V7K V IN
1
4 7 P_ 0402_50V8J
1
0 .1 U_0603_25V7K
PC1 03
PC1 04
PC1 05
1 2 0_0402_5% 1 U_ 0 6 03_6.3V6M
<32> AC_ SET 1 2 ACSET
2
1
3
PR1 05
PC101
1
0 .2 2 U_0603_16V7K
1 0 K_0402_5%
PC1 08
1
1
2
2
1
2 0 0 K_0402_5%
2 PC1 07 PR1 40 PC1 09 ACO F F#
2
1
1 0 0 K_0402_5% @0 .1 U_ 0 603_25V7K
2 7 0 P_0402_50V7K
PC1 06
PR1 06
@0 .0 1 U_0402_16V7K
1
1 0 0 0P_0402_50V7K
4 7 0 P_0402_50V7K
2
2
PR107 C H G EN# CHG _ B+ <37> AC_LED PR1 39
2
+3VLP
PC129
PC130
47K_0402_1% PQ104 PR1 08 1 0 0 K_0402_5%
1 2 2 DT A1 4 4 EUA_SC70-3 10_1206_5% 1 2
1
1
1 2 2 ACO F F <32,39>
1
D
LPREF
ACSET
ACDET
ACP
LPMD
ACN
CHGEN
1
PC134
PQ105 29 P A C IN 2
TP
5
6
7
8
DT C1 1 5 EUA_SC70-3 <2 6 ,2 8,32,36,40,41> S USP# PR110 PC110 G
3
3
1
www.kythuatvitinh.com
SSM3 K7 0 0 2FU_SC70-3 PR1 09 PC128 1 2 8 28 1 2 SSM3 K7 0 0 2FU_SC70-3 PQ106
1 5 0 K_0402_5% IADSLP PVCC DT C1 1 5 EUA_SC70-3
2 1 2
G PC111 PQ108
2
S @1 8 0 P_ 0402_50V8J 9 27 BST _ CHG 1 2 4 AO 4 466_SO8
3
AGND BTST
PC1 12 BQ 2 4 7 40VREF PU1 0 1 0 .1 U_ 0402_10V7K
1 2 10
VREF
BQ 2 4 7 4 0 RHDR_ QFN28_5X5
HIDRV
26 D H_ CHG
PL102 PR112
BATT
3
2
1
PR1 11 PQ109 1 U_ 0 6 03_6.3V6M +3VL 1 0 U_ L F 9 1 9 AS-100M-P3_4.5A_20% 0 .0 15_1206_1%
1
3K_0402_1% D L X_ CHG
11 25 1 2 1 2
P A C IN SSM3 K7 0 0 2 FU_SC70-3 VDAC PH
1 2 2
1
G PD1 02
5
6
7
8
S PR113 V A DJ 12 24 R E GN 2 1 PR1 41
3
4 .7 U_ 0805_25V6-K
4 .7 U_ 0805_25V6-K
4 .7 U_ 0805_25V6-K
4 .7 U_ 0805_25V6-K
@1 0 0 0P_0402_50V7K
2 ACO F F# 1 2 PR114 RL S4148_LL34-2 2
@0_0402_5% 13 23 D L _ CHG
2
2 2
EXTPWR LODRV
1
1 SS3 5 5_SOD323-2 <32> VCT RL 1 2
PC113
PC114
PC115
PC116
PC131
4
1
14 22 PC135
2
ISYNSET PGND
1
4 7 0 P_ 0603_50V8J
1
1
DPMDET
PC117 PR115 PQ110 1 2
IADAPT
SRSET
CELLS
1
1 U_ 0 6 03_10V6K 100K_0402_1% PC119
SRN
2
3
2
1
SRP
BAT
PR1 16 AO 4 466_SO8
2
2
0 .1 U_ 0 402_10V7K
15
16
17
18
19
20
21
PR117
100K_0402_5% BQ 2 4 7 4 0VREF
IADAPT
PR118 1 2
Charge Detector
1
10K_0402_5%
1 2 4 7 K_0402_5%
<32> ADP_I
1
D
0 .2 2 U_0603_10V7K
PR119
1 0 0 P_0402_50V8J
1
1
PQ111 2 BAT _ ID <37>
2
PC1 20
PC1 21
SSM3 K7 0 0 2 FU_SC70-3 G
S
2
3
BATT
0 .1 U_ 0603_25V7K
@0 .1 U_0603_25V7K
PR1 20
2 1 IREF <32>
PC1 22
PC124
133K_0402_1%
1
PC123
1
0 .1 U_ 0 402_10V7K PR122
2
PR121 6 8 1 K_0402_1%
200K_0402_1% 1 2
2
PR123
2
1M_0402_5%
3
1 2 3
P2 PR1 24
+3VL V IN 1 K_ 0402_5%
V IN
1 2
1
1
PR1 25
47_1206_5% PR1 26
1
10K_0402_5%
100K_0402_1% PR127
V IN PR130 1 0 K_0402_1%
2
8
+3VL
1 0 K_0402_1%
PR1 28
2 .1 5K_0402_1% PU1 0 2B
2
1 2 5
P
+
1
PR129
7 P A C IN
2
O
1
1
100K_0402_5%
PR131 6
-
G
1 3 3 K_0402_1% PC125 C H G EN#
2
1
PR1 32
1
0 .0 4 7 U_0402_16V7K
1 0 K_0603_0.1%
2
PR134
2
2
1
D PD103 10K_0402_5%
3
P
2
+ PQ112 RL Z4 .3 B_LL34
1 2
O
1
2 G SSM3 K7 0 0 2 FU_SC70-3
2
-
G
PU1 0 2A S
3
PR135
L M3 93DG_SO8 F ST CHG#
4
1 0 K_ 0603_0.1% PR1 36
4 9 .9K_0402_1%
2
D
1 2 P2
<32> F ST CHG 2 PQ113
1 .2 4 VREF
G SSM3 K7 0 0 2 FU_SC70-3
S
3
STD_ADP <32>
PU1 0 4
4 3 1 .2 4 VREF
ACDET REF CATHODE
1 2
1
PC127 2
PR137 NC
2 2 P_ 0 402_50V8J
1
1 0 0 K_0402_1%
4 4
20K_0402_1% 5 1
2
ANODE NC
PR138
L MV4 3 1ACM5X_SOT23-5
2
Security Classification
2007/05/29
Compal Secret Data
2008/05/29 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
Size Do cu me n t Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Mo ntevina Blade UMA LA4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: Sa tu r d a y, Ja n u a ry 05, 2008 Sheet 38 of 46
A B C D
A B C D E
2VREF_51125
0.22U_0603_10V7K
1
1 1
PC302
2
PR301 PR302
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2
PR303 PR304
B+ B++
20K_0402_1% 20K_0402_1%
B++
PL301 1 2 1 2
HCB2012KF-121T50_0805
www.kythuatvitinh.com
1 2 +3VLP
ENTRIP2
ENTRIP1
@0.1U_0402_25V4K
2200P_0402_50V7K
4.7U_0805_25V6-K
@0.1U_0402_25V4K
PR305 PR306
174K_0402_1% 147K_0402_1%
1
1
PC316
PC301
PC303
10U_0805_6.3V6M
2200P_0402_50V7K
10U_1206_25V6M
PC317
1 2 1 2
1
PC304
PC305
2
2
2
2
PQ301
5
6
7
8
PC306
PU301
1
1 8 U G1_3V
ENTRIP2
VFB2
TONSEL
VREF
VFB1
ENTRIP1
D1 1G PQ302
2 7 25
2 D1 1S/2D P PAD AO4466_SO8 2
3 6
2
G2 1S/2D
4 5
S2 1S/2D
7 24 4
VO2 VO1
UG1_5V
SP8K10S-FD5_SO8 PR308 PC308
8 23
PR307 VREG3 PGOOD 0_0402_5% 0.1U_0402_10V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2
3
2
1
0_0402_5% VBST2 VBST1
PL302 PC307 U G_3V 10 21 U G_5V PL303
4.7UH_SIQB74B-4R7PF_4A_20% 0.1U_0402_10V7K DRVH2 DRVH1 10U_LF919AS-100M-P3_4.5A_20%
2 1 LX_3V 11 20 LX_5V 1 2
+3VALWP LL2 LL1
5
6
7
8
LG_3V 12 19 LG_5V +5VALWP
DRVL2 DRVL1
SKIPSEL
@4.7_1206_5%
@4.7_1206_5%
150U_D_6.3VM
1
VREG5
1
1
VCLK
1
GND
EN0
PC309
220U_6.3VM_R15
VIN
+
PR315
PR316
PC310
4 +
13
14
15
16
17
18
2 T PS51125RGER_QFN24_4X4
2
2
2
620K_0402_5%
1
@680P_0603_50V7K
@680P_0603_50V7K
3
2
1
VL PQ304
1
1
PC314
PR311
PC315
FDS6690AS_NL_SO8
2
2
1
PC311
10U_0805_10V6K
2
3 3
1
PR318
0.1U_0603_25V7K
B++ 1 2
0_0805_5% R_EC_RSMRST# <22>
2
PC312
2VREF_51125
1
D D
PQ305 2 2 PQ306
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
+5VL
3
VL
PJP304
2 1
+3VL PJP302
PU302 P AD -OPEN 2x2m
74LVC1G14GW_SOT353-5 1 2 1 2 (4.5A,180mils ,Via NO.= 9)
VL + 5VALWP +5VALW
PR313 +3VLP +3VL
P AD -OPEN 4x4m
5
NC
32,38> ACOFF 2
A Y
4 1 2 2 2
+3VALWP
1 2 +3VALW (3A,120mils ,Via NO.= 6)
G G P AD -OPEN 2x2m
G
0.022U_0402_25V7K
PR317 S S SSM3K7002FU_SC70-3
EC_ON <32>
3
P AD -OPEN 4x4m
604K_0402_1%
3
1
PC318
4 4
100K_0402_5%
2
PR314
2
Security Classification
2007/05/29
Compal Secret Data
2008/05/29 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3.3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size D o cument Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS M ontevina Blade UMA LA4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: Saturday, January 05, 2008 Sheet 39 of 46
A B C D E
A B C D
1 1
PR401
0_0402_5%
1 2 PL401
6,38,41> SUSP#
HCB1608KF-121T30_0603
1
PR410 1.05V_B+ 1 2 B+
1
@0.1U_0402_25V4K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2200P_0402_50V7K
@10K_0402_5%
PC401
www.kythuatvitinh.com
@1000P_0402_50V7K
2
5
6
7
8
1
+ 5VALW
2
PC414
PC403
PC404
PC405
PC406
BST _1.05V
1 2 BST 1_1.05V
1 2 @680P_0402_50V7K
2
PR402 PC402
1
0_0402_5% 0.1U_0402_10V7K 4
PR403
15
14
1
316_0402_1% PU401
PR404
EN_PSV
TP
VBST
2 255K_0402_1% PQ401 2
2
3
2
1
PR411
1 2 2 13 D H_1.05V 1 2 AO4466_SO8 PL402
TON DRVH 2.2UH_PCMC063T -2R2MN_8A_20%
PR405 0_0402_5%
+1.05V_VCCP 2 1 3 12 LX_1.05V 1 2 +1.05V_VCCP
VOUT LL
220U_6.3VM_R15
0_0402_5%
1
4 11 1 2
V5FILT TRIP
5
6
7
8
PR406 PR407
1
5 10 + 5VALW 18.7K_0402_1% 4.7_1206_5%
VFB V5DRV
PC408
+
1
PC409 6 9 PC415
2 2
PGOOD DRVL
1
PGND
1U_0603_10V6K 4.7U_0805_10V6K
GND
4 2
2
PC412
2
+1.05V_VCCP T PS51117RGYR_QFN14_3.5x3.5 220P_0603_50V8J
7
1
PR408
1 2
10.5K_0402_1% PQ402
3
2
1
DL_1.05V FDS6690AS_NL_SO8
1
PR409
25.5K_0402_1%
2
3 3
PJP401
+1.05V_VCCP 1 2 + VCCP (6A,240mils ,Via NO.=12)
P AD -OPEN 4x4m
4 4
Security Classification
2007/05/29
Compal Secret Data
2008/05/29 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05V_VCCP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size D o cument Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS M ontevina Blade UMA LA4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: Saturday, January 05, 2008 Sheet 40 of 46
A B C D
5 4 3 2 1
D D
PR501 PR502
73.2K_0402_1% 75K_0402_1% PR503 PR504
10.2K_0603_0.1% 14.3K_0603_0.1%
+1.5VSP 1 2 1 2 1 2 1 2 +1.8VP
B+++
2
PR505 B+++ B+
2200P_0402_50V7K
@0.1U_0402_25V4K
0_0402_5% PL502
4.7U_0805_25V6-K
HCB2012KF-121T50_0805
2 1
1
1
1
PC501
PC502
PC520
2
www.kythuatvitinh.com
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2200P_0402_50V7K
@0.1U_0402_25V4K
1
8
7
6
5
5
6
7
8
1
PC516
PU501
1
PC504
PC505
PC521
PQ502
VO2
VFB2
TONSEL
GND
VFB1
VO1
2
AO4466_SO8 25 PQ501
2
P PAD AO4466_SO8
2
4 7 24 4
C PGOOD2 PGOOD1 C
PC507
PC506 PR506 8 23 PR507
EN2 EN1 0.1U_0402_10V7K
0.1U_0402_10V7K 0_0402_5% 0_0402_5%
+1.5VSP 2 1 2 1 BST _1.5V 9 22 BST _1.8V 2 1 1 2
1
2
3
3
2
1
VBST2 VBST1
+1.8VP
PL503 UG1_1.5V 2 1 U G_1.5V 10 21 U G_1.8V 2 1 UG1_1.8V PL501
3.3UH_PCMC063T -3R3MN_6A_20% 0_0402_5% PR508 DR VH2 DR VH1 PR509 3.3UH_PCMC063T -3R3MN_6A_20%
2 1 LX_1.5V 11 20 LX_1.8V 0_0402_5% 1 2
LL2 LL1
LG_1.5V 12 19 LG_1.8V
DR VL2 DR VL1
8
7
6
5
PQ504
1
5
6
7
8
1
PGND2
PGND1
V5FILT
1
PR515
TRIP2
TRIP1
1
V5IN
1
PC517
220U_B2_2.5VM
220U_D2_4VY_R25M
+ @4.7_1206_5% PR516
PC508
PC509 @4.7_1206_5% +
4.7U_0805_6.3V6K 4 T PS51124RGER_QFN24_4x4 PC510
2
1 2
13
14
15
16
17
18
2 4 4.7U_0805_6.3V6K
1 2
1
2
2
AO4466_SO8 PC518 PQ503
1
2
3
3
2
1
17.8K_0402_1% 16.5K_0402_1% @680P_0603_50V7K
1 2
1
PR513
10K_0402_5% PR512
2 1 0_0402_5%
<26,28,32,36,38,40> SUSP# 1 2
B
1 2 SYSON <26,32,33,36> B
+ 5VALW
PR514
3.3_0402_5%
1
PR517
1
1
PC514 PC515 PC512 100K_0402_5%
1U_0603_10V6K 4.7U_0805_10V6K @0.1U_0402_16V7K
PC513
2
2
0.1U_0402_16V7K
2
PJP501
PJP502
+1.8VP 1 2 +1.8V (7A,280mils ,Via NO.= 14)
P AD -OPEN 4x4m
A A
Security Classification
2007/05/29
Compal Secret Data
2008/05/29 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VSP/1.8VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size D o cument Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS M ontevina Blade UMA LA4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D ate: Saturday, January 05, 2008 Sheet 41 of 46
5 4 3 2 1
5 4 3 2 1
D D
+1.8V
P U 601
1 6
VIN VCNTL +5VALW
@ 1 0U_0805_10V4Z
2 5
GND NC
P C 602
1
P C 601 3 7
1
VREF NC
1 0U_0805_10V4Z
2
P R 601 P C 603
4 8
1K_0402_1% VOUT NC 1U_0603_16V6K
2
9
2
TP
G 2 9 92F1U_SO8
1 2
<34,36> SYSON#
0.1U_0402_16V7K
P R 602
www.kythuatvitinh.com
+0.9VP
1
@ 0_0402_5%
P Q601
S S M 3K7002FU_SC70-3 P R 603
1
D
1K_0402_1%
1 2 2 P C 605
<36> SUSP
P C604
P R 604 G 10U_0805_6.3V6M
2
0_0402_5% S
3
1
C P C 606 C
2
@ 0.1U_0402_16V7K
P JP601
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.9VP/1.1V_PCIE
Size D o c u m ent Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Mo n te v in a Bla d e UMA LA4 1 0 1P 0 .3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D a te: S a turday, January 05, 2008 Sheet 42 of 46
5 4 3 2 1
5 4 3 2 1
+5VS
B+
C PU_B+
2
CP U_ V ID6
U_ V ID5
CP U_ V ID4
CP U_ V ID3
CP U_ V ID2
CP U_ V ID1
CP U_ V ID0
<7>
<7>
<7>
<7>
<7>
<7>
<7>
P R202 PL201
V R_ ON
SMB3025500YA_2P
CP<32>
1_0603_5%
2 1
6 8 U_25V_M_R0.44
470P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2200P_0402_50V7K
1000P_0402_50V7K
2200P_0402_50V7K
@ 0.1U_0402_25V4K
1 1 1
1
P C233
P C234
P C205
P C206
6 8 U_25V_M_R0.44
6 8 U_25V_M_R0.44
P R201 499_0402_1%
D D
1
P C242
P C204
P C207
P C241
P C239
P C208
P C240
<9,22> DP RS L PVR 1 2 P C203 + + +
P C237
P C202 2 .2U_0603_6.3V6K
2
P R203 0_0402_5% 0.022U_0402_16V7K
2
2 2 2
P R208
P R209
P R210
P R211
P R212
P R205
P R213
P R207
< 7,9,21> H_ DPRSTP# 1 2
5
6
7
8
P R204 0_0402_5% P Q201
D
D
D
D
<17> CL K_ENABLE# 1 2 AO4474_SO8
1
1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
P R206 0_0402_5%
G
S
S
S
+3VS 1 2
4
3
2
1
+3VS
1U_0603_6.3V6M
2
2
1.91K_0402_1%
2.2_0603_5% 0.22U_0603_10V7KUGA T E_CPU1-2 PL202
1
P C201
P R214 P C209 0 .3 6 UH_ PCMC104T-R36MN1R17_30A_20%
1
B OO T_CPU1 1 2 1 2 2 1 + VC C_CORE
2
5
6
7
8
5
6
7
8
P R216
P R215
1
4.7_1206_5%
3.65K_0805_1%
10K_0402_1%
1
P R218
P R219
P R220
@499_0402_1%
49
48
47
46
45
44
43
42
41
40
39
38
37
1 2
0_0603_5% P R223
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2
P R217 1_0402_5%
GND
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
4 4 P R224
1 2
2
470P_0603_50V7K
1 36 @0_0603_5%
2
< 17,22> VGATE PGOOD BOOT1 PQ202 1 2
P C210
< 7> H_ P SI# 2 35 UGA T E_CPU1-1 F DS6676AS_SO8 V S UM P C211
PSI# UGATE1
1 2
3
2
1
3
2
1
2
1 P R221 2 3 34 P HA S E_CPU1 PQ203 V CC_ P RM
@0_0402_5% P R222 147K_0402_1% PMON PHASE1 F DS6676AS_SO8 IS E N1
1 2 4 33 0.22U_0603_10V7K C PU_B+
RBIAS PGND1
VR_TT# 5 32 L G ATE_CPU1
VR_TT# LGATE1
2200P_0402_50V7K
5
6
7
8
C C
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@0.1U_0402_25V4K
6 31
1
NTC PVCC PQ204
D
D
D
D
1
P C212
P C213
P C235
P C236
7 30 L G ATE_CPU2 AO4474_SO8
1
SOFT LGATE2
P C214
IS L6262ACRZ-T_QFN48_7X7
P C238
8 29
2
G
OCSET PGND2
S
S
S
0.022U_0603_25V7K P C215
2
1 2 9 28 P HA S E_CPU2
4
3
2
1
VW PHASE2 P R225
P R226 13K_0402_1% 10 27 UGA T E_CPU2-1 1 2 UGA T E_CPU2-2
COMP UGATE2 0_0603_5% 0 .3 6 UH_ PCMC104T-R36MN1R17_30A_20%
1 2
11 26 B OO T_CPU2
1 2 1 2 2 1
FB BOOT2 P R227 PL203
1 2
5
6
7
8
5
6
7
8
1
4.7_1206_5%
DROOP
1
FB2 NC
VDIFF
VSUM
ISEN2
ISEN1
VSEN
3.65K_0805_1%
10K_0402_1%
P R229
P R228 6.81K_0402_1% 0.22U_0603_10V7K
GND
VDD
RTN
DFB
1
VIN
P R231
P R232
VO
1 2
P R230
1 2 P U201
13
14
15
16
17
18
19
20
21
22
23
24
1 2
4 4 1_0402_5%
2
P C218 1000P_0402_50V7K
2
P C219
470P_0603_50V7K
IS E N1 P Q205 P R233 @0_0603_5%
IS E N2 F DS6676AS_SO8 1 2
2
1 P R236 2
@0_0402_5%
3
2
1
3
2
1
2 P R237 1
1K_0402_1%
1 2 2 1 F DS6676AS_SO8 V S UM P C223
1
P R234 1_0603_5% 1 2
470P_0402_50V7K P C221
1 2 1U_0402_6.3V6K
2
0.22U_0603_10V7K
P C222 220P_0402_50V7K V CC_ P RM
P R239 IS E N2
255_0402_1% P C224 1000P_0402_50V7K 10_0603_5%
1 2 1 2 1 2 C PU_B+
B B
1
P R2381 2 P C225
0.1U_0603_25V7K
P R240 1K_0402_1%
2
P C226 820P_0603_50V7K
< 7> V CCS E NSE 1 2
V S UM
1
2.61K_0402_1%
P C227 P C228
P R241
@0.022U_0603_50V7K 0.01U_0603_50V7K
2
11K_0402_1%
P C229 180P_0402_50V8J
P R242
1 2
2
10KB_0603_5%_ERTJ1VR103J
1 2 1 2 P H201
2
V CC_ P RM 1 2
P C232 0.22U_0402_6.3V6K
P C231 2 1 2 1
0.22U_0603_10V7K
A A
Item Fixed Issue (Reason for change) PAGE Modify List Date Phase
2 Disable TV out function from Docking 1134 R61R62R63 change to 75 OhmTV_DCONSEL_0TV_DCONSEL_1 connect to GND 11/07 SI-1
CRT(JCRT1)HDMI(JHDMI1)ESATA(JP53)Finger print(JJP24)FAN(JP2)Speaker(JP60)Multi
3 Update Connetor Library 11/17 SI-1
D bay(JP12)Dual LED(D53D12) D
5 USB camera Footprint error 19 Change U42 to G916-390T1UF SOT23, it adjustable mode, R1091=215KR1093=100K 11/07 SI-1
6 Reserve Card reader D3E function 2227 GPIO6= CR_CPPE#GPIO22=CR_WAKE# 11/17 SI-1
7 Swap PCIE LAN and New card 22 Swap PCIE4 and PICE6 11/17 SI-1
8 Add HDCP ROM for ICH9M 2231 Add HDCP ROM for ICH9M 11/17 SI-1
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9 Change G sensor control from SBLED drive by +5VS 2233 Change G sensor control from SB 11/17 SI-1
10 Avoid Battery mode can't boot issue 2239 Add +3VALW GD to EC_RSMRST# to fix Battery mode can't boot issue 11/17 SI-1
11 Add G sensor ST and Bosch 24 Add G sensor ST and Bosch 11/17 SI-1
C C
12 Change LAN solution (Marvell to Realtek) 25 Change LAN solution (Marvell to Realtek) 11/17 SI-1
13 LAN can't work 25 U46 Change to correct transformer type 11/17 SI-1
14 Cardreader schematic review and update, add D3E function 27 R709-->10KR402-->8.2KR704-->StuffR705-->@U37-->@Cardreader LED-->+5VSadd D3E function 11/17 SI-1
15 Jack can't detect normal 28 R1059 change from 39.2 to 39.2K 11/17 SI-1
17 HP audio team recommend 2829 C285~C292C1352C1354 change to 0.022UAmp output setup to 15.6 dBReserve C305C306 for GNDA and GND 11/17 SI-1
18 Audio jack can't detect normal 29 Add Pull up resistor R401 to +3VALW 11/17 SI-1
19 Docking HP audio test fail 29 Add C295 BC296 to avoid DC level, and add R409R410 to reduce HP out level 11/17 SI-1
B B
24 HDMI can't detect 35 DDC _EN must enable TMDS_B_HPD# inverse 11/07 SI-1
25 LVDS power on timing 19 C238 change to 0.047u to meet TI timing 01/03 SI-2
26 Prevent WWAN nosie 21 Add 12p on HDA_SDOUT and HDA_SDOUT 01/03 SI-2
27 Power leakage 2131 Change HDCP ROM to +3VS power plane 01/03 SI-2
A A
28 Prevent WLAN leakage 26 Add Diode prevent WLAN leakage 01/03 SI-2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 44 of 46
5 4 3 2 1
5 4 3 2 1
Item Fixed Issue (Reason for change) PAGE Modify List Date Phase
29 New card PTH connector GND 26 New card PTH connector GND 01/03 SI-2
30 Change Cardreader LED control 27 Change Cardreader LED control 01/03 SI-2
35 Reserver 0 ohm co lay with common choke 35 Reserver 0 ohm co lay with common choke 01/03 SI-2
36 Sparate+5VS and +3VS power timing 36 Sparate+5VS and +3VS power timing 01/03 SI-2
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37 Keyboard backlight reserve a 0805 size resistor 33 Keyboard backlight reserve a 0805 size resistor 01/03 SI-2
38 Change Lid switch connector type 33 Change Lid switch connector type 01/03 SI-2
39
C C
40
41
42
43
44
45
46
47
B B
48
49
50
51
52
53
54
55
A A
56
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR 2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 45 of 46
5 4 3 2 1
Version Change List ( P. I. R. List ) for Power Circuit
A B C D E
Item Page# Title Date Request Issue Description Solution Description Rev.
Owner
1 1
DC Connector Add PD4 & PC12
1 37 /CPU_OTP 11/06 Compal Add PD4 & PC12
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5 39 3.3VALWP/5VALWP 11/14 Compal for Layout Change PL303 and PC310
6 38 Charger 12/31 Compal EMI solution Add PC129, PC130, PC131, PC132, PC133
2 2
8 39 3.3VALWP/5VALWP 12/31 Compal PWR request Add PU302, control signal changed to ACOFF
10
11
3 3
12
13
14
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Do c ument Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cu s tom Montevina B lade UMA LA 4101P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Da te: S aturday, January 05, 2008 Sheet 46 of 46
A B C D E