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Quartus2 Introduction
Quartus2 Introduction
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The Qsys system integration tool saves significant time and effort in the
FPGA design process by automatically generating interconnect logic to
connect IP functions and subsystems. Qsys is the next-generation SOPC
Builder tool powered by a new FPGA-optimized Network-on-a-Chip
(NoC) technology delivering high-performance, scalable systems, and
improved design reuse opportunities.
Power-Optimized Design
Verification
Quartus II software offers several tools to help you analyze the results of compilation and fitting. Verification with the
SignalTap II logic analyzer and the System Console allows you to probe your design as it functions on the device
and in the system.
Control A Control B
32 Bit 32 Bit
Memory A
Address
Data
Address
Data
Interrupt
Controller
Arbiter
Width Match Width Match Width Match Width Match Width Match
Arbiter
Data
Memory B Memory C
Quartus II Project
Quartus II Project
Step 2 (No Partitions) Step 2
AA B
B C
C
Simulation
You can perform functional and Altera provides functional simulation libraries for designs that contain
timing simulation of your design with Altera-specific components, and atom-based timing simulation libraries for
the ModelSim-Altera Edition software designs compiled in Quartus II software.
or any EDA simulators supported by
Quartus II software also allows you to use the EDA tools you are familiar with
Quartus II software. Quartus II
for other stages of the design flow, including synthesis, timing analysis, and
software provides the following
formal verification.
features for performing simulation:
NativeLink integration with
simulation tools Links to Online Resources
System Console
System Console provides you with Tcl scripts and a GUI to perform low-level hardware debugging of your design, to
identify a Qsys module by its path, and to open and close a debugging connection to a module. You can use the
Transceiver Toolkit component of the System Console to set up channel links in your transceiver-based designs, and
then automatically run EyeQ and Auto Sweep testing for a graphical view of your test.
Quartus II Handbook
http://www.altera.com/literature/hb/qts/
quartusii_handbook.pdf
The Quartus II Handbook provides comprehensive
information about the programmable logic design
cycle from design to verification.
Copyright 2011 Altera Corporation. All rights reserved. Altera, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks
are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera
products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. PDF, April 2011 GB-1003-1.0