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    US6756823B1

    Uploaded by

    Sesharatnam Koppula
    ssaspl

    Copyright:

    © All Rights Reserved
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    ‘US0067568. «2 United States Patent Chen et al. DIFFERENTIAL SENSE LATCH SCHE Inventors: Feng Chen, Porland, OR (US); Tom Fletcher, Portland, OR (US) (73) Assignee: Intel Corporation, Santa Clara, CA (vs) (2). Notice: Subject to any diselaimer the term of this patent is extended or adjusted under 35 USC. 154(b) by 0 days, (21) Appl. No. 09/606,367 (22) Filed Jun. 28, 2000 Hose 3/48 ‘327/82; 327/55; 327/57 327851, 96, 97, 98, 330) Fleld of Search 327/57, 2663 188, 205 60) References Cited US. PATENT DOCUMENTS. US 6,756,823 BL 682381 (10) Patent No. (5) Date of Patent: Jun. 29, 2004 5982.99 A 11/199) Takahashi sess 6.160.782 A 122040 Chang Basins 6.163501 A * 122000 Ohshima eta 3657283 6.299528 BL * S/2001 Yong eta wm88 * cited by examiner Primary Examiner-—My-Teang Nu Ton iep Neuyen (74) Attorney, Agent, or Firm Woessner & Kluth, PA. Assistant Examiner Schwegman, Lundberg, on ABSTRACT A circuit including diferentil sense cecut and alte, the feretil sense circuit and the latch coupled so ato form adierenial sense atch such that, in operation, an electronic signal stored in the latch is retained for atleast one clack evel. ims, § Drawing Sheets US 6,756,823 BL Sheet 1 of 5 Jun. 29, 2004 U.S. Patent (Uy Hd) [bey US 6,756,823 BL Sheet 2 of 5 2004 Jun. 29, U.S. Patent (LY ted) gly pd US 6,756,823 BL Sheet 3 of 5 Jun. 29, 2004 U.S. Patent [if tg] gbey no ie . US 6,756,823 BL Sheet 4 of 5 Jun. 29, 2004 U.S. Patent U.S. Patent Jun. 29, 2004 Sheet 5 of 5 US 6,756,823 B1 PROCESSOR a0 wm DIFFERENTIAL, DOMINO LOGIC / Ce aL on x LOH VOLTAGE ac SWING LOGIC SING ORCUTRY ligb US 6,756,823 BL 1 DIFFERENTIAL SENSE LATCH SCHEME BACKGROUND 1. Fila This disclosure relates to latches, and, more particularly, to differential sense latches, 2, Background Information ‘Two typical competing conceras in circuit design are performance versus power consumption and performance versus silicon area. Fypcaly, improving the performance of Acireuit, such as one embodied oa an integrated cecuit UC), for example, results at least, in corresponding increases in power consumption andor silicon area, for example, bath of ‘which may be undesirable. For examp, with such circuits, ‘electron system and IC packaging costs may increase due to measures that are employed to dissipate the heat gener- ated by such increases in power consumption. Also, for ‘example, increases in power consumption may prescat add tional circuit design coocers, such as IC reliability and rout immunity Wo electronie noise, Current methods ‘employed to achieve such performance Improvements may als rest in increases to silicon area of sich an TC, which 's typically directly related to increases in power consump- In this regard, dynamic and differential circuitry may be ‘subject to at least some of the foregoing concems, though Additional concerns may exist. These types of circuits arc, for example, typically employed in high-speed circuitry this context, highspeed circuitry is circuitry that is capable ‘of processing electronic signals ata relatively fast rate a5, ‘compared o other types of circuitry, such as static log, for ‘example. The term high-speed, in this context, is well- Kknown to those of skill in the ar. In cenain situations, for such circuit embodiments, it may be desirable o relain, for some specie time duration, at ‘electronic signal, or signals produced by such differential and/or dynamie circuitry. Similar eoncemns regarding meth- ‘xs for improving the performance or speed of ICs employ= fing such dynamic and diferentialcirevitry may also be felevant to sich astociated circuitry for retaining such ‘sigoal(s) In this respec, such methoss may actually result, Jn adverse impacts on performance, such as “speed”, for ‘example, duc, at least in part, to the capacitive loading typically associated with circuits employed in implementing ‘such techniques, Therefore, alternatives for achieving sueb Performance improvements may be desirable BRIEF DESCRIPTION OF THE DRAWINGS The subject matter regarded as the invention is particu larly pointed out and distinelly claimed in the concluding portion ofthe specification, The iaventoa, however, both as to onganization and method of operation, together wilh features and advantages thereof, may best be understood by reference to the following detailed description when read ‘with the accompanying drawings in which FIG. 1 is a schematic diagram illustrating two current differential Lach embodiments. FIG.2 isa schematic diagram illustrating embodiments of Paype and N-ype differential sense amplifiers. FIG. 34 schematic diagram illustrating an embodiment of a differential domino (dynamic) circuit FIG. 4s a schematic diagram illustrating an embodiment ‘of an Netype sense latch in accordance with the invention. FIG. 5 isa schematic diagram illustrating an embodiment ‘of Paype sense latch in accordance withthe invention % o 2 FIG. 6 is a block diagram illustrating an embodiment of 4 processor in accordance with the inveation DETAILED DESCRIPTION In the following detailed description, sumerous specific etails are set forth in order to provide a thorough under standing of the invention. However, it wll be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, ‘well-known methods, procedures, components and cicevits hhave not been described in detail so a8 not to obscure the present invention, As was previously jnicated, dynamic andor diferetial circuitry may be employed in ercuis, such as those embod jed on an integrated circuit, to achieve, for example, improvements in performance of such circuits. As was also indicated above, in certain situations, it may be desirable 10 retain an eleetconic signal value produced by such dileren- ior dynamic eireutry for certain period of time. Though itmay depend on the specific embodiment, this time may be substantially equal to one clock period fora circuit in which such a scheme is employed, though, of course, altematives ‘may exist. Typically, as those of skill inthe art would be Aware, such electronic signal values ate typically produced by such differential andor dynamic circuitry asa result of an evaluate operation. Evaluate operations will be discussed in further detail hereinafter. However, ata high level, as those ‘of skill in the art would bo aware, such a technique typically ‘comprises pre-charging such circuitry, applying input sig- nals to such cizcuity and then applying an electronic signa, ‘which causes such circuitry to “evaluate” the input signals and produce corresponding output signa. In such aeieuit fonce such an evaluate operation is complete the circuit ‘ypically is retumed to pre-charge mode to facilitate execu- tion of a subsequent evaluate operation. Typically, this sequence occurs. in ess than one clock eyele. To this scenario, the results of the prior evaluate would typically no Tonger be available. Depending on the particular embodiment, the above see~ nario may be undesirable. For example, if such different andlor dynamic cizcuitey were employed to interface With Static logic, sich as traditions! complementary metal-oxide silicon (CMOS) logic gates, it may be desirable to retain the result from such an evaluate uni that result is replaced with ‘a resll from subsequent evaluate operation, Io this regaed, IG. 1 illustrates two current techniques for retaining such results, FIG. 1 illustrates wo embodiments of curtent latches that may be employed with cedaia types of differential or dynamic circuitry to retain such evaluation results. Ia this respoct, the circuit in block 100 may be employed with ilferenial andor dynamic circuits that are designed 10 pre-charge their differential output terminals oa voltage that Js substantially equal to ground or “pulled low”, suet as pesense amp 110. Such sense amps will be discussed in further detail bereatter, For the embodiment illustrated in block 100, the output ‘erminals ofa p-sense amplifier (amp), 10, are each coupled to one input terminal of each of the cross-coupled NOR gates 120 and 130, These cross-coupled NOR gates form a tiferenial latch, In this regard, during pre-charge, such @ latch would retain a result stored by a previous evaluate operation. The latch would retsin such a result diring pre-charge due, atleast in pat, o the aspect thatthe output ferminals of the amp are pulled low during. pre-charge Because of the cross-coupled configuration of the NOR US 6,756,823 BL 7 ates, pling a single input terminal low on eack gate will fot result in modification of the contents of such a latch During an evaluation of p-sense amp 110, one of the two dliflereatial outputs wold be pulled igh while the other wl, femain low. This may, depending on the contents of the Tatch,resull inthe modification of the contents of the latch In this regard, if an evaluate operation pulls the inverted ‘output terminal, designated “d#", of p-sense amp 110 high and then a subsequent evaluate pulls the noa-inverted output terminal, designated “a, high, this sequence would result in the latch contents being modified FIG. 1 als illustrates, in block 180, another embodiment ‘of a curent latch that may be employed with differential andior dynamic citeitry. Here, the differential latch com- prises cross-coupled NAND gates 170 and 180, Such Lach ‘may be employed with differential andlor dynamic circuitry that is designed to have output terminals which are pr charge to a voltage substantially equal to » power sippy voltage for such a circuit, or “pulled high”, such as nsense amp 120, As was te case with he circuit illustrated in block 100, result stored in such a lateh would be retained during ‘apro-charge operation as pulling only a single input terminal ‘of each NAND gate high would not result in the contents of such a latch being modified! FIG, 2 ilusieates an embodiment of a p-sease amp, 210, and an embodiment of an n-sense amp, 260. These sense amps may be employed by the configurations illustrated in FIG. I. In this repard, for p-sense amp 210, pre-charge would occur when a clock signal asserted on the terminal designated "pelk#” is pulled high. For a-sense amp 260, pre-charge would occur when a clock signal asserted oa its pelk terminal is pulled low. Likewise, “evalvate” would ‘occur whe such a clock signals pulled iow for pense amp 210 and pulled high for macnse amp 260 In certain embod ‘ments employing a global clock signal, it may be desirable to invert the clock input signal for p-sense amps, as is ‘discussed in more detail hereafter, This may be advantae _geous in, for example, synchronous circuits, as pre-charge snd evaluate for n-sense amps and p-sense amps in such sn ‘embodiment may occur substantially simultancously ‘While the foregoing technique addesses the concern of retaining an evaluation result from dlllerential and/or ‘dynamic circuitry fora time substantially equivalent to one ‘lock eyele, sich embodiments also have certain disadvan- tages. For example, because of the cross-coupled configu- ration of the latches employed in these embexliments, wo full CMOS gate delays would be added to a signa path ia whit such a latch is employed. These gate delays may, therefore, adversely affect tbe perfomance of suet a signal path, One way the concern with gate delay may be addressed Js to decrease sch gate delays by increasing transistor sizes in such gates. This technigue, however, may result in Jncreased power consumption and increased silicon area for ‘such circuits, which are embodied on an integrated circuit, (IC), for example. This result may also be undesirable FIG. 3 is schematic disgrum of a differential domino ruil, which may be used to ilusieate additional conccens Jn ths regard. As is well-known to those of skill in the at, ‘domino circuits are typically used in high performance «iccuit embodiments, such as various types of processors, for ‘example, Such domino cicuits typically operate in a case ‘ade fashion. That is, one stage of circuitry typically triggers the next stage, or “dominoes” into the next stage, The ‘operation of such circuits is well-known to thase of skill in the act. Such domino circuits typically have pre-charge and ‘evaluate phases, in a similar fashion as was previously discussed. However, because such circuitry typically % o 4 ‘employs a pulbe clock, such results may be available for a relatively short period of time. Such puke clocks, when employed in dynamic andlor differential circuitry, present pulse width conceras that are discussed hereafler ‘The embodiment, 300, ilustrated in FIG. 3 shows one technique thal, at kast in part, addresses the foregoing concern of retaining evaluate rel in a dlfeeatial domino circuit. In this regard, transistors 378 and 388 may function 458 diferential latch fo retain such a result, However, sich ‘result would be present until he differential domino eireut began its next pre-charge operation, which is typically a shorter duration than is desired in certain situations. In this respect, tbe differential output terminals, designated “out” and “out” may be pre-charged high via keepers 308 and ‘310 when a clock signal applied via the terminal designated ‘pel is pulled low: Input signals may then be applied to transistors 315-338 and 345-865 in block 390, These Iean- sistors represent a logic function to be evaluated for this particular embodiment of a differential domino cieuit. A pulse clock may then be asserted on te pel terminal. This ‘wll turn on vansistors 340 and 370, which will “evaluate” the log function and the differential result wil be “latched” by transistors 375 and 380, As those of skill nthe art would kno, in differential domino eirevts, such as 300, one of the ‘wo differential output terminals would be pulled Tow as result of sich an evaluate while the other remains high, ‘Although, the result will be “latched” in such an ‘embodiment, that result will ypically no longer be available ‘once the next pre-charge operation begins, that is, when the elk terminal is pulled low after the pulse clock duration. In Situations where it may be desirable to retain the result of| such an evaluate operation for a longer duration, such ‘nll the next evaluate operation, a latch comprising ross coupled NAND gates, such as was previously discussed, ‘would typically be employed. However, employing such & latch may reslt in the previously discussed corresponding disadvantages ‘As was previously indieated, the use of pulse elocks in ilfewntial citeuts, such as’ the previously discussed embodiments, presents concerns associated with the width of such a pulse. Typically, reductions in such pulse wid ‘may, in turn, result in performance improvements. In this regard, assuming a fixed time Fora pre-charge operation, @ shorter pulse clock duration may result in improved perfor ance a more pulses may be generated over a given tn period. As those of skill inthe art would be aware, short ‘ning such 4 pulse clock's duration may result in adverse ellets due 19 what is typically referred to as sigoal evapo- ‘ation, In this context, signal evaporation may be due, at least in par, tothe intrinsic delay of transistors or loge pates| associated with such a pulse clock. Ata high level if the pulse clock duration is not as long or longer than such associated intrinsic delays, signals in a circuit path may ‘evaporate or disappear as evaluate results are aot available {ors salicieat period of time, Ths phenomenon is typically addressed by what may be referred to asa pulse width to gate ‘elay ratio and is well-known to those of skill ia the ar. [Based on the foregoing concerns, alternative techniques for retaining evaluate results from differential and dynamic circuitry may be desirable. FIG, 4illusates an embodiment of a differential sense chin accordance with the invention that may address at east some of the foregoing conceros. While the invention is ‘ot limited in scope in this respec, ths particular embod ‘ent ofa dilferentil sense latch may bo employed with a sense amp, as is illustrated in FIG. 4. This particular embodiment comprises n-sense amp 460, dilfereatial sease US 6,756,823 BL 5 ‘iccuit 470 and late, or jam latch, 480, Both n-sense amps nd jam latches ate well-known to those of skill in the aft As was previously indicated, such a sense amp’s output terminals would be pre-charged high while a signal asserted ‘on the terminal that is designated “clock” is low. In this patcular embodiment, during pre-charge, transistors 408, ‘410, 420 and 428 would be off. This would allow jam latch 480 10 maintain a cureenly stored value as difleretial sense ‘iccuit would not be applying any voltage to the latch via the ‘couplings illusrated in FIG. 4. Transistors 418 and 430 ‘would be on, but would not affect the lateh contents a they ‘would be electrically isolated from the latch by trnsisors 10 and 42. Once the output terminals are pre-charged, ‘differential input signals may then be applied On the input terminals, designated “in” and “ind.” For the sake of ‘lustatioa, though the invention i not so Limited, it wil be assumed that terminal “in” i at a Voltage greater tha terminal “ing” Aler applying these input signals, genral- ing @ pulse clock on “elock” would result in these input signals heing “evalated.” This evaluate operation would ia turn, esult in “di”, the inverted outpul terminal of nscnse amp 460, being pulled low. The pulse clock would also tura ‘on transistors 410 and 428, allowing the differential sense ‘circuit to be evaluated in a dynamic fashion. Since “0”, the ron-iverted output terminal of a-sense amp 460 would remain high, transistor 408 would remain off and 418 would remain on, Since“, the inverted output termina, is pulled low, transistor 420 would turn on and transistor 430 would turnoff. In tis situation, the terminal of jam latch 480 ‘designated “ould” would be pulled low while the terminal ‘designated “out” would be pulled high. This may be referred to as push-pull configuration and would typically result in the contents of such a latch becoming stable faser than if ‘one lerminal of the latch Was pulled high or low to change its contents, for example ‘Such an embodiment may be advantayeous over eureat ‘embodiments in a umber of respects. For example, the time ‘employed to latch an evaluate result using such a configu Fation may be reduced relative to erosecoupled NAND ‘ates, for example. This is dic, at least in part, 19 $60 factors, though, of eourse, the invention is not limited in scope inthis respect. Firs, as was previously indicated, the time employed 0 latch such a result in a cross-coupled NAND latch comprises two CMOS gate delays. In contrast the time employed for this particular embodiment comprises a single simple gate delay. In this context, « simple gute ‘delay means that transistor 420 may pull the terminal of latch 480, designated “out”, high without any significant pull-down contention and, therefore, may be faster than & ‘ingle CMOS gate delay. In such an embodiment, fo reduce ‘such pull-down contention, a pulse clock signal would be generated once transistor 428 was oll, or “di” was pulled low: There are aumber of techniques that may be employed to achieve such a resll and the invention i not limited ia scope to any particular technique for reducing pull-down ‘contention, Second, sich a configuration may employ ess time t latch a result du, at least in pat, o the previously «discussed push-pull configuration. Because one terminal of Jatch 480 would be pulled high and one terminal pulled low at substantially the sa the time to “late” a result may be reduced as compared 1 the two CMOS gate delays typically employed by prior embodiments, An additional beneiit of this panicular embodiment is due, at least in part, to the aspect tha such embodiments latch evaluate resis based, a least in part, on a clock signal Therefore, such & “ifferental sense amp may alternatively be employed 38 a Alip-op, which may provided additional design flexibility in ‘certain embodinents 6 As was previously discussed with respect o prior embod ‘ment laches, this particular embodiment also may address ‘concen celted f0 signal evaporation. Beeause such differ nlal sense litches operate ins substantially static manner they may have higher gain than conventional latch circuits ‘Therefore, such differential sense latehes may refresh sia- nals to a voltage substantially equivalent tothe power supply vollage for cizcuts in which they are employed. Therefore, the adverse alfeets of evaporation may be reduced. ‘Additionally, this particular embodiment may employ less silicon area and consume less power than prior embodiments {ora variety of reasons. For exampl, due at least in part to the differential sense circuit being, operated with reduced pull-up and pulldown contention, the transistors employed ‘may be smaller, as less drive current may be employed 10 achieve similar performance, or even improved perfor ‘mance. Also, ths lck of contention may reduce the amount ‘of power consumption as switching current may be reduce. Adkliionally, due at least in part to the fact that such embodiments are not configured in a cross-coupled contiguration, reductions in transistor sizes may also be realized, as output terminal loading and gate-delays may be reduced Therefore, embodiments such as 400 my consume Jess power and silicon area than prior embodiments without an adverse effect or with a reduced adverse effect, and perhaps « poteaial improvement in performance. Another potential advantage of embodiments, such 3s 400, as compared to other typicil dlferenial or dynamic circuit elements is hased, at least in part, om the aspect that they operate in a substantially static masner and that they ‘may be evaluated in a dynamic fashion, These aspects of such embodiments may allow them 10 be employed 10 interface wit static logic, such as CMOS gates, differential circuitry, such as sense amps, and dynamic circuity, such as ‘domino or diffecemtial domino circuits. This flexibility may result in desiga and performance benefits, such as those that hhave been previously discussed. The invention i, of course, ‘ot limited in scope to the Toregoing advantages or applications, and additional benefits and techniques may {exis in allermative embodiments, FIG. 5 illustrates an alternative embodiment of a difer- cnlal sense latch, which may be employed with differential circuitry, for example, For this particular embodiment, the ‘ferential sense latch comprises difereaial sense circuit ‘S80 and jam latch $90, As i illustated in FIG. 8, such 2 ferential sense latch may be employed, for example, with ‘p-sense amp, though the invention isnot limited in seope in this respect. Alternatively, sich a latch might be employed ‘with a lilferentil p-type domino circuit, for example ‘As was previously indiated, p-sense amp ott tpi cally are pulled low during pre-charge. For this particular embodiment, during such a pre-charge operation, transistors ‘S40, $50, 560 snd 570 would be off axl, therefore, the ‘ult terminals of differential sense circuit S80 would not be deiven by the differential sense circuit, or ui-stated as it is typically called, For this embodiment, since the clock input signal is inverted, pre-charge would occur when a signal applied to “clock” & pulled low, in a similae manner as discussed with respect to FIG, 4. This may be advanta- {geous as p-sense amps and n-sense amps employed in the Same circuit would pre-charge and evsluste substantially simultaneously and, therefore, facilitate synchronous of sequential operation of such cies For this particular embodiment, jam latch $90 would retain a previously stored result during such a pre-charge ‘operation, as may be desired. As is illustrated in FIG. ‘ferential sense circuit $80 is not coupled with the “clock” US 6,756,823 BL 1 ‘erminal. This may be advantageous, a the diferetial sense circuit would aot add addtional loud to a clack distribution twee in Such embadimenis, which may, in turn, reduce area and power consumption over alternative techniques that might be employed, Again, for illustrative purposes, it will be assumed that a signal applied tothe terminal designated “in” is ofa voltage greater than a signal applied to the terminal designated “ini.” P-sense amp S10 woul “evaluate” these input signals Jn response to, for example, # pulse clock signal on the terminal designated “clack” in FIG. 8. For this particular ‘example, the non-averted output terminal, designated “<, ‘of p-sense amp S10 may be pulled high as a resul of suck puke clock sigaal This, in tur, would result in turning on Transistors S40 and S60, which would, espectively, pull the terminal of jam late $90, designated “out, Tow and the terminal desigeated “out” high. For this particular cembostiment, two parallel gate delays are present. The terminal of jam latch $90 being pulled down will be on a signal path with a simple gate delay; as was previously discussed, The terminal of jam latch $90 being pulled up will, be on a circuit pith with a full gate delay, due to either inverter $20 or $30, plus a simple gate delay, de to either transistor $40 or $60. While this configuration may have additional gate delay as compared to the embodiment ilus- trated in FIG. 4, it may provide performance advantages ‘over prior embodiments that comprise two full CMOS gate ‘delays. These performance advantages woul be due, atleast Jn pan, to a reduction in gate delay. Additionally, perfor mance advantages may result dic, at least in part to the reduetion of pull-upipull

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