EE348SUMMER2011 NAME:SOLUTION

FINALEXAM,120minutes SURNAME:

Q1)(12pts)
C Assumecomplementsofinputvariablesareavailable.ForF,
F: CD findout
00 01 11 10
AB a)minimalANDORimplementation:
00 x 1 1 F=BD+CD(primeimplicantswithsolidlines)

01 x x x B
B D F
11 1
A C
10 1 x x D



D

b)minimalORANDimplementation: c)Minimal2levelNANDANDimplementation:
F=BD+CD(primeimplicantswithdottedlines) UseF,implementasANDNORandthenconvertto
F=(F)=(B+D)(C+D) NAND_ANDbyshiftingbubblestoleft

B
D F B B
D F D F
C
D
C C
D D





Q2)(8pts)
F AssumethatcomplementsoftheinputvariablesareNOT
available.Insertminimumnumberofinvertersin(a)
below,sothattheresultingcircuitwilloperatethesame
astheonegiveninleft.Repeatitfor(b).

G


a) b)
H

F
F

G G

H H

 Q3)(15pts)

Binarytograyconversionalgorithm: Giveastatetransitiondiagramwithminimalnumberof
stateswhichwillproducethecorrespondinggraycodeat
CopythefirstbitandthenstartingwiththeMSB theoutputywhenanynbitgraycodegivenasinputserially
ofthebinarynumber,compareeachpairof atinputXd.AssumethatMSBarrivesfirstandanotherinput
succeedingbits.Iftheyarethesameplace0in XfsignalsthearrivaloftheLSBbit.UseorderXfXd/yfor
thegraycodeword.Iftheyaredifferentplacea input/output.
oneinthegraycode1. 10/0,11/1
Example:
10/0,11/1 10/1,11/0
S
binary 1 1 0 1 1 0 0 1
00/0 01/1
binaryprev 1 1 0 1 1 0 0
01/1
= = =
Gray 1 0 1 1 0 1 0 1 S 0 S 1
00/0 01/0
00/1

statesS0andS1rememberthepreviousinput

Statereduction
Afterstatereduction
PS NS Y 01/1
00 01 10 11 00 01 10 11
S S0 S1 S S 0 1 0 1 S 0 S 1
00/0 01/0
S0 S0 S1 S S 0 1 0 1 10/0,11/1 00/1,
S1 S0 S1 S S 1 0 1 1 10/1,11/0
SS0
Q4)(10pts)
Forthecircuitgivenleft,completethestatetransition
Y diagramwherestateorderisQAQB.


J Q A 0
Clk
C
1
X K QA 00/0 01/1

T Q B 0,1 1
0 0,1
C
QB 11/1 10/1


JA=QA+QB,KA=TB=QA+x,Y=QA+QB

PS FF inputs NS Y
X=0 X=1 X=0 X=1
Q AQ B J AK A T B J AK A T B

00 00 0 01 1 00 01 0

01 10 0 11 1 11 10 1
10 11 1 11 1 01 01 1
11 11 1 11 1 00 00 1

Q5)(15pts)

Youaregiventhecharacteristic a)Findoutcharacteristicequation
tableforABFF.
AB Q(t+1) A
00 0 Q(t+1):
01 Q(t) 0 0 1 1
10 Q'(t) Q(t+1)=QA+QB
11 1 Q 0 1 1 0

B

b)Findoutexciationtable c)ImplementABFFusingDFF A
D:
QAB D
Q(t)Q(t+1) AB 000 0
0 0 1 1
00 0x 001 0
01 1x 010 1 Q 0 1 1 0
10 x0 011 1
11 x1 100 0 B

101 1
D=AQ+BQ
110 0

111 1

Q6)(10pts)
Consideringthegivenstatetransition
PS NS Y
table
Q1Q0 x=0x=1
a)writeoutputequation
01 01 10 0
Q 1
10 10 01 0 Y:

11 11 10 1 x 0 1 0

x x 0 1 0 Y=Q1Q0

Q 0
b)MinimalsumofproductsexpressionsfortheSRFFinputs
Q1transition: Q
1 Q0transition: Q
1
Q1Q0 00 Q 1Q 0
01 11 10 00 01 11 10
x x
x 00 11 11 x 11 11 00
x x 01 11 10 x x 10 10 01

Q0 Q0

Q(t)Q(t+1) SR Q 1 Q 1
S1: S0:
00 0x x 0 x x x x x 0 S1=xQ0orxQ1
01 10
x x 1 x 0 x x 0 0 1 R1=xQ0
10 01
Q 0 Q 0
11 x0
Q 1 Q 1 S0=xQ0
R1: R0: R0=xQ0
x x 0 0 x 0 0 x

x x 0 0 1 x x 1 1 0

Q 0 Q 0

Q7)(15pts)

C Implementthefunctionusingonlyone4x1multiplexer.
F: CD DoNOTuseanyextragate.Complementsoftheinput
00 01 11 10
AB variables,0and1areavailable.
00 1 x 1 D D
D=0 D=1 D=0 D=1
B B
01 1 1 1 C C B=0 I 0 I1 B=0
B
11 1 x x B A C B=1 B I 2 I 3 B=1
A
10 1 1 x
D D

D C I 0
4x1 F
2
C I 1 Y
MUX
A I 2
C I 3 S1S0

B D

Q8)(15pts) You aregiven 4 bitbidirectionalshiftregisterA:A3A2A1A0.Theregisterhasnoparallel
load capability. If SH=0 it shifts right, otherwise it shifts left. SI is the serial input to be loaded to
eithertoA3orA0appropriatelyaccordingtothevalueofSH.Itisrequestedtodesignacounterwhich
willcountthesequence:0000,1000,0100,1010,0101,0010,0001.

Youareallowedtouseanynumberofinvertersbutthenumberofothergatesshouldbeminimal.0
and1areavailable.Drawyourcircuitbelow.
A3A2A1A0 SI=A3(t+1)
0000 1
0001 0
0010 0 1
0011 x SH4BitSHIFTREGISTER
0100 1 clk
0101 0 SIA3A2A1A0
0110 x
0111 x
A 1
1000 0 F A1A0
1001 x 00 01 11 10
:A3A2
1010 0 A200 1 0 x 0
1011 x
01 1 0 x x
1100 x A2
1101 x 11 x x x x
1110 x A 3
10 0 x x 0 SI=A3A1A0
1111 x
A 0