Design of Buck-boost regulator for the USBC

application
Architecture and control loop description:
For this application we need to have a buck regulator from 9.6V to 5V and a boost regulator from 12.6V to 20V. Hence
a non-inverting buck-boost regulator configuration is chosen to accomplish this. There are various architectures
available to achieve this which includes cuk-regulator, SEPIC regulator and 4-switch non-inverting buck-boost regulator.
I avoided using the cuk-regulator, since it is inverting in nature. A SEPIC architecture makes use to 2 inductors and 2
capacitors and hence to reduce the no. of components it is not chosen. Finally, in this design I am using the non-
inverting buck boost architecture.
The figure below shows the open loop implementation of the non-inverting buck-boost regulator.

This configuration employs 4 switches, a single L and C (or 2-pole) filter to remove or average out the switching
ripple. For duty cycle, D < 0.5 the regulator operates in bucking mode and for duty cycle, D>0.5 the regulator operates
in boost mode. Since the regulator operates in CCM mode and there is no stringent requirement for monitoring the
current sensing a voltage mode control loop is considered. The current sense is used to limit the current so that the
inductor never saturates.
A 5V LDO is used for the generating supply for all the logic gates, comparators, generating the thresholds for current
limits.

Current limit operation:

The current sense is done using a 10mohms sense resistor in series with the inductor. A gain stage adds a gain
of 20. The voltage is then compared with the reference threshold to generate the current limits. When out=5V, the
current limit is set to 4.4A. On current limit, the comparator U1 triggers HIGH and the AND gate (A1) forces nodes c1
and c2 to be LOW and HIGH respectively, as that the current build up is limited. Similarly, when out=20V, the
current limit threshold is changed to 12.2A. When the current limit occurs, the comparator U1 triggers HIGH and the
AND gate (A1) forces nodes c1 and c2 to be LOW and HIGH respectively, so that the current build up is limited. In
case of the reverse current limit (charging the battery source), when the inductor current reaches -12.2A (which means
ILOAD=-3A), the comparator U3 triggers HIGH and the OR gate (A5) forces nodes c1 and c2 to be HIGH and LOW
respectively, so that the reverse current build up is limited.
For VOUT=5V, ILOAD=2A and VIN=9.6V we have:
ILmax = (IL+ILp2p)max*1.2=4.37A (20% more the max current)
Rsense=10e-3 ohm
vsense=ILmax*Rsense=43.7mV
Vcs=gain*vsense=20*43.7m = 874mV.
Hence for VOUT=5V (operating point 1), the current limit threshold is set to 4.4A
Similarly, for VOUT=20V, ILOAD=3A and VIN=9.6V we have:
ILmax = (IL+ILp2p)max*1.2= 12.18 (20% more the max current)
Rsense=10e-3 ohm
vsense=ILmax*Rsense=122mV
Vcs=gain*vsense=20*122m = 2.44V.
Hence for VOUT=20V (operating point 2), the current limit threshold is set to 12.2A

Inductor selection:
There is only one inductor used in the design and following is the brief way how the L value is chosen.
DC value IL of the inductor current at the worst-case operating point: include equations used to
calculate IL, and report IL value as a number with units.

(1)2

For Vbat=12.6V. Vout=20V and Iout=3A is the corner with IL=7.76A and D=Vout/(Vout+Vbat)=
0.613

Selected inductance L: include equations used to calculate L, and report inductance L as a number
with units.

=
_2
_= 0.9*Imax,
And above Worst-case operating point (ILmax+delta_ilmax=12.2A) returns,
Choosing Fsw=500 kHz Tsw=2us
L= 17.2uH

From the appendix D a core EECORE EE16 is chosen and following are the inductor parameters
Parameter Notation Value Units Value SI units
Geometrical Constant Kg 4.07E-3 cm^5
Cross sectional area Ac 0.23 cm^2 23.00E-6 m^2
Bobbin Winding Area Wa 0.384 cm^2 38.40E-6 m^2
Mean length per turn MLT 3.69 cm 36.90E-3 m
Magnetic path Length lm 3.94 cm 39.40E-3 m
Core Weight 4.83 gms
Air gap length Lg 1.4E-3 m
No of turns n 28 turns
Wire Gauge AWG 6.9E-3 cm^2 685.71E-9 m^2

Capacitor selection:
Depending on the ripple on the output the value of the capacitor is chosen.
Cout=68uF, Cin=68uF, 2 bootstrap capacitors Cdd1, Cdd2=10uF
Ctotal = 156uF