Schedule

Weeks Days Start Date

START DATE: 11/09/15
0.5 Release Tasks

SPM 1.25 6.25

Total 1.25 6.25

Total with 20% Debug (1 Resource) 1.50 8
Total with 20% Debug (2 resources, 1
resource at 70%) 0.88 5
0.5 Release Date

START DATE: 11/20/2015

0.8 Release Tasks

Functional Coverage 0 0
Regressions 0.4 2

Total 0.4 2
Total with 20% Debug (1 Resource) 0.48 3
Total with 20% Debug (2 resources, 1
resource at 70%) 0.28 2
0.8 Release Date

START DATE: 11/26/2015

1.0 Release Tasks

Code Coverage -0.02 -0.1

0
Total -0.02 -0.1
Total with 20% Debug (1 Resource) -0.024 -0.12
Total with 20% Debug (2 resources, 1
resource at 70%) -0.01 -0.071
1.0 Release Date
1.15 6.9294

Holidays
Complete Date Actual Status Comments Owner

11/19/2015

11/25/2015

11/25/2015
Coverpoint Test Name

full_mem_sweep_aligned

full_mem_sweep_unaligned

narrow_txfs_and_unaligned_combined

Write_and_read_at_same_time

err_1bit_crc_2bit_det_aligned

err_1bit_crc_2bit_det_unaligned

err_1bit_crc_2bit_det_narrow

Cont_and_rand_loc_narrow_txfs_with_errs

ecc_bypass
Read_burst_in_the_middle_of_write_burst

No_wait_states

Mult_unaligned_txs
 Bins Checkers
Self Checking Test case with Read will
check for expected value and compare
with actual

Addr,awlen, awsize
Self Checking Test case with Read will
check for expected value and compare
with actual

Addr,awlen, awsize
Self Checking Test case with Read will
check for expected value and compare
Addr,awlen, awsize with actual
Self Checking Test case with Read will
check for expected value and compare
with actual
Addr,awlen, awsize
Self Checking Test case with Read will
check for expected value and compare
with actual

Addr,awlen, awsize, intr1 and intr2

Self Checking Test case with Read will
check for expected value and compare
with actual
Addr,awlen, awsize, intr1 and intr2
Self Checking Test case with Read will
check for expected value and compare
with actual

Addr,awlen, awsize, intr1 and intr2

Self Checking Test case with Read will
check for expected value and compare
with actual
Addr,awlen, awsize
Self Checking Test case with Read will
check for expected value and compare
with actual
bypass
 Self Checking Test case with Read will
check for expected value and compare
Addr,awlen, awsize with actual
 This is a Full mem sweep
test. In this test write and
reads to the full mem
exercised. It has following
variations.
1)Some write/reads are
back to back
2) Will be sending a small
This is aburst
aligned Full mem
of write sweep
then
test. In this
similar length test write and
burst of read.
Remarks
reads to the full
Randomization across the mem
exercised.
above two Itvariations
has followingwith
variations.
rand delay
1)Some
Every test write/reads
has enum which are
back to back
will randomly selects the
2) Will
type be sending
of data ALL_1,aALL_0, small
un-aligned burst
RAND, ALL_5A,ALL_A5. of write
then similar length burst of
read.
Randomization across the
above two variations with
rand delay
Every test has enum which
will randomly selects the
type of data ALL_1, ALL_0,
RAND, ALL_5A,ALL_A5.
one narrow tx'f immediately
followed by burst of
unaligned
ErrTest to checktransfer.
inj sequence how rtl is
will corrupt
handling
the data in writes and reads
memory. And the to
the same location
same is responsible to initiated
simultaneously
create 1bit, 2bit forandsingle
more
Errnumber port mem.
of errors
inj sequence willincorrupt
the
the dataprovided 128 bits.
in memory. And the
Aslo
same checks for interrupts
is responsible to
create and clears
1bit, 2bit them
and more
appropriately.
number of errors Will havein the rand
Err injvariable
provided
sequence to128
clear the
bits.
will corrupt
theAslo
data interrupts.
checks
in for interrupts
memory. And the
same andisclears them to
responsible
appropriately.
create 1bit, 2bit Willand
have morerand
variable
number ofto clearinthe
errors the
interrupts.
provided 128 bits.
Aslo checks for interrupts
and clears them
appropriately. Will have rand
variable to clear the
interrupts.

Narrow transfers will be sent

continuously to successive
locations and also to
random locations.

in bypass mode ecc engine

will be bypassed and we
can expect erros
 Need to ensure no wait
states in the middle of
write/read bursts.
16byte line will be filled by
multiple un-aligned transfers
.