T.Y.EII Microprocessor-III N.

KAPOOR 1
Instructions: It is a binary pattern designed inside a µ p to perform specific function. The entire
group of instructions is called instruction set & determines what functions the µ p can perform.
The instruction may be one , two or three byte in length. The first byte indicates the operation to
be performed & 2nd & 3rd if present contain either operand or the address of operand on which
operation has to be performed.
Instruction format : An instruction is a command to the µ p to perform a given task on
specified
data. In instruction the 1st byte indicates the operation to be performed & ∴
called operation code
( opcode ). The 2nd & 3rd byte if present, contain either operand or the address of operand on
which operation is to be performed.
Instruction word size : Instruction can be One word (1-byte ) , Two word (2-byte ) or Three
word
(3-byte ) .
1-Byte instruction : A one byte instruction includes the opcode & operand in the same byte.
Opcode e.g. (i) MOV C A → 4FH → copy the content of accumulator in register C
ADD C → 81 H → add content of register C to accumulator. CMA → 2FH ,
SUB B → 90 H, INR A → 3C , DCR A → 3D
2- Byte instruction :In a two byte instruction first byte specifies the opcode & second byte either
opcode operand/ add operand or address.
e.g. MVI R,data(8),MVI B data(8) [ 06 DATA] , SUI R data(8) , ANI data(8), ORI data(8),IN
add(8)
OUT add(8)
3-Byte instruction : 1st byte specifies the . & 2nd & 3rd byte specifies 16-bit address. 2nd byte is
lower order address & 3rd byte is higher order address. e.g. LDA add(16), STA add(16), LHLD
add(16), JMP add(16)
Op-code Format : In 8085 µ p all operation registers & status flags are identified with a
specific code.
code Register code Register
000 B 110 Memory related operations
001 C 111 A
010 D 00 BC
011 E 01 DE
100 H 10 HL
101 L 11 AF or SP

Addressing Modes→ Each instruction specifies an operation to be performed on certain data.

There are different techniques by which address of the data to be operated upon may be
specified. These techniques are known as “ addressing modes”. The four modes of addressing
in 8085 are -- (1) Implied Addressing → (Inherent addressing) In implied addressing, no address
is necessary because the location is implied in the instruction itself. e.g. (I) NOP-- No operation.
(No address is necessary) (ii) STC -- Set carry flag.
(2) Direct Addressing→ In direct addressing the address of operand is explicitly specified within
the instruction itself. All such instructions are 3-byte long. e.g. LDA add (16), STA add (16).
(3) Register Addressing→ When operands for any operation are in the general purpose register,
only the registers need to be specified as the address of operands. Such addressing modes is
called register addressing. These are 1 byte within that byte, operation code & register is
specified. e.g. MOV A, B, ADD B.
(4) Indirect Addressing→ In this mode contents of specified registers are assumed to be
address of operand instead of being the operand itself. In this case instead of specifying
register, a register pair is specified to hold the 16-bit address of the operand. MOV A M- Move
contents of memory location, pointed by HL-pair to the accumulator. JMP add (16).
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(5) Immediate Addressing→ In the immediate addressing, operand is specified within the
instruction itself. Here operand address is not given explicitly but 1 or 2 bytes within the
instructions are used for specifying the data itself. e.g. MVI (8) , LXI (8) ADI (8)

The 8085 µ p’s instructions are usually classified under five heads, → (i) Data transfer group
(ii) Arithmetic group (iii) logic group (iv) Branch group (v) Stack , I / o & machine control group.
DATA TRANSFER INSTRUCTIONS
 Explanation of
Opcode Operand Description
Instruction
Rd, Rs This instruction copies the contents of the source register into
T.Y.EII Microprocessor-III
Copy from the destination register; the contents of theN.KAPOOR 3
source register are not
MOV M, Rs source(Rs) to altered. If one of the operands is a memory location, its location
ARITHMETIC INSTRUCTIONS
destination(Rd) is specified by the contents of the HL registers.
Rd, M Example: MOV B, C or MOV B, M
The 8-bit data is stored in the destination register or memory. If
Rd, data
Move immediate the operand is a memory location, its location is specified by the
MVI
8-bit contents of the HL registers.
M, data
Example: MVI B, 57H or MVI M, 57H
The contents of a memory location, specified by a 16-bit address
16-bit in the operand, are copied to the accumulator. The contents of
LDA Load accumulator
address the source are not altered.
Example: LDA 2034H
The contents of the designated register pair point to a memory
B/D location. This instruction copies the contents of that memory
Load accumulator
LDAX Reg. location into the accumulator. The contents of either the register
indirect
pair pair or the memory location are not altered.
Example: LDAX B
Reg. The instruction loads 16-bit data in the register pair designated in
Load register pair
LXI pair, 16- the operand.
immediate
bit data Example: LXI H, 2034H or LXI H, XYZ
The instruction copies the contents of the memory location
pointed out by the 16-bit address into register L and copies the
16-bit Load H and L
LHLD contents of the next memory location into register H. The
address registers direct
contents of source memory locations are not altered.
Example: LHLD 2040H
The contents of the accumulator are copied into the memory
location specified by the operand. This is a 3-byte instruction,
16-bit
STA 16-bit address the second byte specifies the low-order address and the third
address
byte specifies the high-order address.
Example: STA 4350H
The contents of the accumulator are copied into the memory
Reg. Store accumulator location specified by the contents of the operand (register pair).
STAX
pair indirect The contents of the accumulator are not altered.
Example: STAX B
The contents of register L are stored into the memory location
specified by the 16-bit address in the operand and the contents of
H register are stored into the next memory location by
16-bit Store H and L incrementing the operand. The contents of registers HL are not
SHLD
address registers direct altered. This is a 3-byte instruction, the second byte specifies the
low-order address and the third byte specifies the high-order
address.
Example: SHLD 2470H
The contents of register H are exchanged with the contents of
Exchange H and L register D, and the contents of register L are exchanged with the
XCHG none
with D and E contents of register E.
Example: XCHG
The instruction loads the contents of the H and L registers into
the stack pointer register, the contents of the H register provide
Copy H and L
the high-order address and the contents of the L register provide
SPHL none registers to the stack
the low-order address. The contents of the H
pointer
and L registers are not altered.
Example: SPHL
The contents of the L register are exchanged with the stack
location pointed out by the contents of the stack pointer register.
Exchange H and L The contents of the H register are exchanged with the next stack
XTHL none
with top of stack location (SP+1); however, the contents of the stack pointer
register are not altered.
Example: XTHL
The contents of the register pair designated in the operand are
T.Y.EII Microprocessor-III N.KAPOOR 4

Explanation of
Opcode Operand Description
Instruction
The contents of the operand (register or memory) are added to the
contents of the accumulator and the result is stored in the
R Add register or
accumulator. If the operand is a memory location, its location is
ADD memory, to
specified by the contents of the HL registers. All flags are modified
M accumulator
to reflect the result of the addition.
Example: ADD B or ADD M
The contents of the operand (register or memory) and M the Carry
flag are added to the contents of the accumulator and the result is
R Add register to
stored in the accumulator. If the operand is a memory location, its
ADC accumulator
location is specified by the contents of the HL registers. All flags
M with carry
are modified to reflect the result of the addition.
Example: ADC B or ADC M
The 8-bit data (operand) is added to the contents of the accumulator
Add immediate and the result is stored in the accumulator. All flags are modified to
ADI 8-bit data
to accumulator reflect the result of the addition.
Example: ADI 45H
The 8-bit data (operand) and the Carry flag are added to the
Add immediate contents of the accumulator and the result is stored in the
ACI 8-bit data to accumulator accumulator. All flags are modified to reflect the result of the
with carry addition.
Example: ACI 45H
The instruction loads 16-bit data in the register pair designated in
Reg. pair, Load register
LXI the operand.
16-bit data pair immediate
Example: LXI H, 2034H or LXI H, XYZ
The 16-bit contents of the specified register pair are added to the
Add register pair contents of the HL register and the sum is stored in the HL register.
DAD Reg. pair to H and L The contents of the source register pair are not altered. If the result
registers is larger than 16 bits, the CY flag is set. No other flags are affected.
Example: DAD H
The contents of the operand (register or memory ) are subtracted
from the contents of the accumulator, and the result is stored in the
R Subtract register
accumulator. If the operand is a memory location, its location is
SUB or memory from
specified by the contents of the HL registers. All flags are modified
M accumulator
to reflect the result of the subtraction.
Example: SUB B or SUB M
The contents of the operand (register or memory ) and M the
Borrow flag are subtracted from the contents of the accumulator
R Subtract source and the result is placed in the accumulator. If the operand is a
SBB and borrow from memory location, its location is specified by the contents of the HL
M accumulator registers. All flags are modified to reflect the result of the
subtraction.
Example: SBB B or SBB M
The 8-bit data (operand) is subtracted from the contents of the
Subtract
accumulator and the result is stored in the accumulator. All flags
SUI 8-bit data immediate from
are modified to reflect the result of the subtraction.
accumulator
Example: SUI 45H
Subtract The contents of register H are exchanged with the contents of
immediate from register D, and the contents of register L are exchanged with the
SBI 8-bit data
accumulator contents of register E.
with borrow Example: XCHG
T.Y.EII Microprocessor-III N.KAPOOR 5
The contents of the designated register or memory) are incremented
R Increment by 1 and the result is stored in the same place. If the operand is a
INR register or memory location, its location is specified by the contents of the HL
M memory by 1 registers.
Example: INR B or INR M
The contents of the designated register pair are incremented by 1
Increment
INX R and the result is stored in the same place.
register pair by 1
Example: INX H
The contents of the designated register or memory are M
R Decrement decremented by 1 and the result is stored in the same place. If the
DCR register or operand is a memory location, its location is specified by the
M memory by 1 contents of the HL registers.
Example: DCR B or DCR M
The contents of the designated register pair are decremented by 1
Decrement
DCX R and the result is stored in the same place.
register pair by 1
Example: DCX H
The contents of the accumulator are changed from a binary value to
two 4-bit binary coded decimal (BCD) digits. This is the only
instruction that uses the auxiliary flag to perform the binary to BCD
conversion, and the conversion procedure is described below. S, Z,
AC, P, CY flags are altered to reflect the results of the operation.
Decimal adjust If the value of the low-order 4-bits in the accumulator is greater
DAA none
accumulator than 9 or if AC flag is set, the instruction adds 6 to the low-order
four bits.
If the value of the high-order 4-bits in the accumulator is greater
than 9 or if the Carry flag is set, the instruction adds 6 to the high-
order four bits.
Example: DAA

BRANCHING INSTRUCTIONS
Explanation of
Opcode Operand Description
Instruction
The program sequence is transferred to the
16-bit Jump memory location specified by the 16-bit
JMP
address unconditionally address given in the operand.
Example: JMP 2034H or JMP XYZ
Flag 16-bit Jump The program sequence is transferred to the
Opcode Description address conditionally memory location specified by the 16-bit
Status
address given in the operand based on the
Jump on
JC CY = 1 specified flag of the PSW as described below.
Carry
Example: JZ 2034H or JZ XYZ
Jump on no
JNC CY = 0
Carry
Jump on
JP S=0
positive
Jump on
JM S=1
minus
Jump on
JZ Z=1
zero
Jump on no
JNZ Z=0
zero
T.Y.EII Microprocessor-III N.KAPOOR 6
Jump on
JPE P=1
parity even
Jump on
JPO P=0
parity odd

Flag
Opcode Description
Status
Call on
CC CY = 1
Carry
Call on no
CNC CY = 0
Carry
The program sequence is transferred to the
Call on memory location specified by the 16-bit
CP S=0
positive address given in the operand. Before the
16-bit Unconditional
Call on transfer, the address of the next instruction after
CM S=1 address subroutine call
minus CALL (the contents of the program counter) is
CZ Call on zero Z=1 pushed onto the stack.
Example: CALL 2034H or CALL XYZ
Call on no
CNZ Z=0
zero
Call on
CPE P=1
parity even
Call on
CPO P=0
parity odd
The program sequence is transferred from the
subroutine to the calling program. The two
Return from
bytes from the top of the stack are copied into
RET none subroutine
the program counter,and program execution
unconditionally
begins at the new address.
Example: RET
Flag
Opcode Description
Status
Return on
RC CY = 1
Carry
Return on
RNC CY = 0
no Carry
Return on The program sequence is transferred from the
RP S=0 subroutine to the calling program based on the
positive
Return from specified flag of the PSW as described below.
Return on
RM S=1 none subroutine The two bytes from the top of the stack are
minus
conditionally copied into the program counter, and program
Return on execution begins at the new address.
RZ Z=1
zero Example: RZ
Return on
RNZ Z=0
no zero
Return on
RPE P=1
parity even
Return on
RPO P=0
parity odd
PCHL none Load program The contents of registers H and L are copied
counter with into the program counter. The contents of H are
HL contents placed as the high-order byte and the contents
of L as the low-order byte.
T.Y.EII Microprocessor-III N.KAPOOR 7
Example: PCHL
The RST instruction is equivalent to a 1-byte
call instruction to one of eight memory
locations depending upon the number. The
instructions are generally used in conjunction
with interrupts and inserted using external
hardware. However these can be used as
software instructions in a program to transfer
program execution to one of the eight locations.
The addresses are:
Restart
Instruction
Address
RST 0 0000H
RST1 0008H
RST 2 0010H
RST RST 3 0018H
0-7 Restart RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
The 8085 has four additional interrupts and
these interrupts generate RST instructions
internally and thus do not require any external
hardware. These instructions and their Restart
addresses are:
Restart
Interrupt
Address
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

CONTROL INSTRUCTIONS
Explanation
Opcode Operand of Description
Instruction
No operation is performed. The instruction is fetched and decoded.
NOP none No operation However no operation is executed.
Example: NOP
Halt and The CPU finishes executing the current instruction and halts any further
HLT none enter wait execution. An interrupt or reset is necessary to exit from the halt state.
state Example: HLT
The interrupt enable flip-flop is reset and all the interrupts except the
Disable
DI none TRAP are disabled. No flags are affected.
interrupts
Example: DI
EI none Enable The interrupt enable flip-flop is set and all interrupts are enabled. No
interrupts flags are affected. After a system reset or the acknowledgement of an
interrupt, the interrupt enable flipflop is reset, thus disabling the
interrupts. This instruction is
necessary to reenable the interrupts (except TRAP).
T.Y.EII Microprocessor-III N.KAPOOR 8
Example: EI
This is a multipurpose instruction used to read the status of interrupts
7.5, 6.5, 5.5 and read serial data input bit. The instruction loads eight
bits in the accumulator with the following interpretations.
Example: RIM
Read
RIM none
interrupt mas

This is a multipurpose instruction and used to implement the 8085

interrupts 7.5, 6.5, 5.5, and serial data output. The instruction interprets
the accumulator contents as follows.
Example: SIM

Set interrupt
SIM none
mask

LOGICAL INSTRUCTIONS
Explanation of
Opcode Operand Description
Instruction
The contents of the operand (register or memory) are M compared
with the contents of the accumulator. Both contents are preserved .
Compare The result of the comparison is shown by setting the flags of the
R
register or PSW as follows:
CMP
memory with if (A) < (reg/mem): carry flag is set
M
accumulator if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
Example: CMP B or CMP M
CPI 8-bit data Compare The second byte (8-bit data) is compared with the contents of the
immediate with accumulator. The values being compared remain unchanged. The
accumulator result of the comparison is shown by setting the flags of the PSW as
follows:
if (A) < data: carry flag is set
T.Y.EII Microprocessor-III N.KAPOOR 9
if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset
Example: CPI 89H
The contents of the accumulator are logically ANDed with M the
contents of the operand (register or memory), and the result is placed
Logical AND in the accumulator. If the operand is a memory location, its address
R
register or is specified by the contents of HL registers. S, Z, P are modified to
ANA
memory with reflect the result of the operation. CY is reset. AC is set.
M
accumulator Example: ANA B or ANA M

The contents of the accumulator are logically ANDed with the

Logical AND 8-bit data (operand) and the result is placed in the
8-bit
ANI immediate with accumulator. S, Z, P are modified to reflect the result of the
data
accumulator operation. CY is reset. AC is set.
Example: ANI 86H
The contents of the accumulator are Exclusive ORed with M the
Exclusive OR contents of the operand (register or memory), and the result is placed
R
register or in the accumulator. If the operand is a memory location, its address
XRA
memory with is specified by the contents of HL registers. S, Z, P are modified to
M
accumulator reflect the result of the operation. CY and AC are reset.
Example: XRA B or XRA M
The contents of the accumulator are Exclusive ORed with the 8-bit
Exclusive OR
8-bit data (operand) and the result is placed in the accumulator. S, Z, P are
XRI immediate with
data modified to reflect the result of the operation. CY and AC are reset.
accumulator
Example: XRI 86H
The contents of the accumulator are logically ORed with M the
Logical OR contents of the operand (register or memory), and the result is placed
R
register or in the accumulator. If the operand is a memory location, its address
ORA
memory with is specified by the contents of HL registers. S, Z, P are modified to
M
accumulator reflect the result of the operation. CY and AC are reset.
Example: ORA B or ORA M
The contents of the accumulator are logically ORed with the 8-bit
Logical OR
8-bit data (operand) and the result is placed in the accumulator. S, Z, P are
ORI immediate with
data modified to reflect the result of the operation. CY and AC are reset.
accumulator
Example: ORI 86H
Each binary bit of the accumulator is rotated left by one position. Bit
Rotate D7 is placed in the position of D0 as well as in the Carry flag. CY is
RLC none
accumulator left modified according to bit D7. S, Z, P, AC are not affected.
Example: RLC
Each binary bit of the accumulator is rotated right by one position.
Rotate
Bit D0 is placed in the position of D7 as well as in the Carry flag.
RRC none accumulator
CY is modified according to bit D0. S, Z, P, AC are not affected.
right
Example: RRC
Each binary bit of the accumulator is rotated left by one position
Rotate through the Carry flag. Bit D7 is placed in the Carry flag, and the
RAL none accumulator left Carry flag is placed in the least significant position D0. CY is
through carry modified according to bit D7. S, Z, P, AC are not affected.
Example: RAL
Each binary bit of the accumulator is rotated right by one position
Rotate
through the Carry flag. Bit D0 is placed in the Carry flag, and the
accumulator
RAR none Carry flag is placed in the most significant position D7. CY is
right through
modified according to bit D0. S, Z, P, AC are not affected.
carry
Example: RAR
T.Y.EII Microprocessor-III N.KAPOOR
10

Complement The contents of the accumulator are complemented. No flags are

CMA none
accumulator affected.Example: CMA
Complement The Carry flag is complemented. No other flags are affected.
CMC none
carry Example: CMC
Set Carry
STC none Set Carry
Example: STC