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Chapter - 6 Evolution of Msp430 Family Microcontrollers: S.No. Name of The Sub-Title Page No
Chapter - 6 Evolution of Msp430 Family Microcontrollers: S.No. Name of The Sub-Title Page No
CHAPTER - 6
Table of Contents
6.1 Introduction
requires low power will be chosen for the entire low power design
with this ultra low power family of microcontrollers which have rich
features for low power system design. It is the platform of very low
with Von Neumann architecture and was designed for low power
applications [47]. The MSP indicates that this is equally employed for
both analog and digital signal inputs. For this an ADC with a
operated in standby mode with a typical current well below 1mA. Due
it indicates ROM. For ASSPs, the second letter indicates the type of
segments. Many of them are ASSPs and some of them are general
devices too.
this controller is combined with five low power modes. Maximum code
features of MSP430 micro controller are shown in figure 6.1 and the
cost.
over registers are used as general purpose registers. Other devices are
connected to CPU via data bus, address bus and control bus, which
converters.
MSP430F1611
Among them one is active mode and other five are low-power modes
from one of these five low-power modes. The six operating modes
I. Active mode AM
In Active mode, all clock cycles are active and power consumption
will be high.
In this mode, the CPU is actually disabled and ACLK and SMCLK
In this mode also, CPU is disabled and the ACLK and SMCLK
In this mode CPU is disabled, MCLK & SMCLK are disabled. DCOs
In this mode CPU, MCLK and SMCLK and DCOs dc generators are
Fig 6.3 depicts the graph drawn between operating modes and current
consumption of MSP430.
mode can be saved on the stack during ISR. It can be returned back
individual control register settings. All I/O port pins & RAM /registers
clear that in active mode, the CPU is active and all enabled clocks are
active. Whereas in low power mode 4, CPU and all the clocks are
requires very less power about 2A and all interrupts are active. For
needed.
Unique CPU register cycles are employed for more usage of long
software subroutines.
6.2.3 Peripherals
peripherals are connected to the CPU through address, data & control
I. DMA controller
powered applications.
When it drops lower than a user required level, the CPU starts
bit length. All the I/O ports are programmed individually. The
V. Watchdog timer
prescribed intervals.
addressing modes of 7-bit and 10-bit with master and slave mode
I2C data transfer mode with two dedicated DMA channels are
VIII. Timer_A3
IX. Timer_B7
etc.
X. Comparator_A
to digital.
XI. ADC12
XII. DAC12
them.
and debugging the application code. The main advantage of the four-
wire mode is speed. The main advantage of the two-wire SBW mode is
electrical characteristics are always useful. The Figure 6.5 shows the
variation of the supply voltage range with the frequency during the
Vcc=2.2V Vcc=3V
72
The curves indicate that the output current levels saturate for the Port
increase in the voltage levels of Vcc, the saturation levels also changes.
are shown in the Table 6.1. From the Table it is clear that even in the worst
case of active mode for Vcc =3 V, the maximum power dissipation is around
600A and the power dissipation for the low power mode 4 is only about 0.5
many biomedical and wires sensor applications. The leakage currents of the
Table 6.1: The typical power consumption values for various low-power
modes
73
Low-power mode, 50 60
(LPM0) 2.2V A
I(LPM0) f(MCLK)=0 MHz, TA=-400C to
f(SMCLK)=1MHz, 850C 95 75
f(ACLK)=32,768 Hz 3V
XTS=0, SELM=(0,1)
(see Note1)
Low-power mode, 2.2V 11 14
I(LPM2) (LPM2) TA=-400C to A
f(MCLK)=f(SMCLK)=0MHz, 850C 3V 17 22
f(ACLK)=32,768 Hz,
SCG0=0
Low-power mode, TA=-400C 1.3 1.6
(LPM3) TA=250C 2.2V 1.3 1.6
f(MCLK)=f(SMCLK)=0MHz, TA=850C 3.0 6.0
I(LPM3) f(ACLK)=32,768 Hz, TA=-400C 2.6 3.0 A
SCG0=1. (See Note 2) TA=250C 3V 2.6 3.0
TA=850C 4.4 8.0
Low-power mode, TA=-400C 0.2 0.5
I(LPM4) (LPM4) TA=250C 2.2V 0.2 0.5 A
f(MCLK)=0 MHz, TA=850C /3V 2.0 5.0
f(SMCLK)=0MHz,
f(ACLK)=0 Hz, SCG0=0